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Memory-Mapped High-Performance Features
Data access is limited to 8-byte, 16-byte, or 32-byte sections of flash page in wrap mode. The ARM core uses the
Wrap 4 access (64-bit data) for L1 cache. The ARM core uses Wrap 4 and Wrap 8 accesses (64-bit data) for L2
cache. The cores use the Wrap 8 accesses for unaligned accesses. During the read request to the SPI memory-map-
ped hardware, the memory subsystem master of the processor provides the address of a critical word instead of the
line base. The read-data starts at the address specified in the instruction. Once it reaches the end boundary of the 8,
16, or 32-byte section, the output automatically wraps around to the beginning boundary to the line base address.
The data fetch continues. It is not necessary to deassert the SPI SPI_SEL[n] signal or resend the read header to
wrap to the cache line base when servicing misaligned cache fill requests.
The Byte Sequence in Wrap Modes table shows byte sequences in various wrap modes.
Table 16-10: Byte Sequence in Wrap Modes
Starting Address
0
1
7
15
31
The burst with wrap feature allows applications to fetch a critical address quickly. Applications then fill the cache
afterwards within a fixed length (8/16/32-byte) of data without issuing multiple read commands. Certain applica-
tions can benefit from this feature to improve cache fill efficiency and overall performance of system code execution.
Do not use the merge and wrap feature together. Using wrap bursts can unintentionally disable merging
NOTE:
(merging cannot occur for unaligned wrapping bursts). A wrap burst can start fetching data words in the
middle of the cache line and cannot be merged with the next access.
Execute-In-Place (XIP, SPI2 only)
Execute-In-Place, most commonly known as XIP, allows software code to execute directly from an SPI flash device
rather than downloading the code and executing it out of RAM. XIP, also known as Command Skip mode, is a
general term and can be applied to fetching data as well.
There is a difference between XIP mode and standard mode. In XIP mode, after the SPI memory device is selected
(CS# =LOW), the memory device does not decode the first input byte as command code. Instead, it expects the
read header to directly start with address bytes. In standard mode, the memory decodes the first input byte it re-
ceives as a command code.
The XIP mode dramatically reduces random access time for applications that require fast code execution without
shadowing the memory content on a RAM. The SPI memory-mapped hardware provides a control bit,
SPI_MMRDH.CMDSKIP to skip the command from read header.
Some SPI memory devices require configuration of their control register to enable the XIP mode of operation, using
the non-memory-mapped mode of the processor SPI. Typically, during the dummy cycle period, the mode bits are
used to confirm the XIP operation and the SPI_MMRDH.MODE field must be set appropriately. A dummy
16–24
8-Byte Wrap (cache_line = 8 byte)
0-1-2- . . . -6-7
1-2- 3-. . . -7-0
7-0-1- . . . -5-6
15-8-9- . . . -13-14
31-24-25-. . . .-29-30
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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