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Table 14-5: ADSP-SC58x PINT Trigger List Slaves
Trigger ID
Name
ADSP-SC58x PADS Register List
The PADS controls signal hysteresis and other system interface signal features for a number of module interfaces.
Table 14-6: ADSP-SC58x PADS Register List
Name
PADS_DAI0_IE
PADS_DAI1_IE
PADS_PCFG0
PORT Architectural Concepts
These sections describe in more detail how the PORT module connects externally to pins and internally to the
MMR bus. Ports are named alphabetically beginning with A.
•
Internal Interfaces
•
External Interfaces
•
GPIO Functionality
•
Port Multiplexing Control
Internal Interfaces
All of the pin multiplexing, GPIO, and pin interrupt control block MMRs can be accessed through the MMR bus.
There is no DMA support. Each of the pin interrupt (PINTx) modules has its own dedicated interrupt request out-
put signal that connects directly to the system event controller (SEC).
External Interfaces
The pin multiplexing hardware can be seen as a layer between the on-chip peripherals and the silicon pads connect-
ing to the physical pins/balls or the package, as controlled by the PORT unit.
GPIO Functionality
By default, the PORT sets every GPIO pin to input mode. The input drivers are not enabled, which avoids the need
for unnecessary current sinks and external termination resistors on unused pins.
Input Mode
The default mode of every GPIO pin after reset is input mode, but the input drivers are not enabled. To enable
GPIO input drivers, set the bits corresponding to the PORT pins in the appropriate input enable register
(PORT_INEN). When enabled, a read from the
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
None
Description
DAI0 Port Input Enable Control Register
DAI1 Port Input Enable Control Register
Peripheral PAD Configuration0 Register
PORT_DATA
Sensitivity
register returns the logical state of the input pins.
PORT Functional Description
14–5
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