Analog Devices ADSP-SC58 Series Hardware Reference Manual page 182

System Clock Buffer Status Register
The
CGU_SCBF_STAT
CGU_CCBF_DIS.CCBF0 bit clears the CGU_SCBF_STAT.SCLK0BF bit after a number of cycles. To guaran-
tee that the correct value is read, this register should be read twice and the second result used.
OCLKBF (R)
OCLK Buffer
DCLKBF (R)
DCLK1 Buffer
Figure 3-12: CGU_SCBF_STAT Register Diagram
Table 3-18: CGU_SCBF_STAT Register Fields
Bit No.
(Access)
3 OCLKBF
(R/NW)
2 DCLKBF
(R/NW)
1 SCLK1BF
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register shows which system clock buffer(s) are disabled. For example clearing the
15 14 13 12 11
0 0 0 0 0
31 30 29 28 27
0 0 0 0 0
Bit Name
OCLK Buffer.
The CGU_SCBF_STAT.OCLKBF bit reports the status of the
CGU_SCBF_DIS.OUTCLKBF bit where 0 = enabled and 1 = disabled.
DCLK1 Buffer.
The CGU_SCBF_STAT.DCLKBF bit reports the status of the
CGU_SCBF_DIS.DCLKBF bit where 0 = enabled and 1 = disabled.
SCLK1 Buffer.
The CGU_SCBF_STAT.SCLK1BF bit reports the status of the
CGU_SCBF_DIS.SCLK1BF bit where 0 = enabled and 1 = disabled.
10 9 8 7 6 5 4 3
0 0 0 0 0 0 0 0
26 25 24 23 22 21 20 19
0 0 0 0 0 0 0 0
Description/Enumeration
0 Enabled
1 Disabled
0 Enabled
1 Disabled
0 Enabled
1 Disabled
ADSP-SC58x CGU Register Descriptions
2 1 0
0 0 0
SCLK0BF (R)
SCLK0 Buffer
SCLK1BF (R)
SCLK1 Buffer
18 17 16
0 0 0
3–31