Analog Devices SHARC ADSP-2136 Series Manuals

Manuals and User Guides for Analog Devices SHARC ADSP-2136 Series. We have 1 Analog Devices SHARC ADSP-2136 Series manual available for free PDF download: Hardware Reference Manual

Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual (656 pages)

Brand: Analog Devices | Category: Computer Hardware | Size: 5 MB

Table of Contents
3
Preface
31
Purpose of this Manual
31
Intended Audience
31
Manual Contents
32
What's New in this Manual
34
Technical or Customer Support
36
Supported Processors
37
Product Information
37
Myanalog.com
38
Processor Product Information
38
Related Documents
39
Online Technical Documentation
40
Accessing Documentation from Visualdsp
40
Accessing Documentation from Windows
41
Accessing Documentation from the Web
41
Conventions
42
ADSP-2136X SHARC Design Advantages
45
SHARC Family Product Offerings
49
Processor Architectural Overview
50
Processor Core
51
Processor Peripherals
51
I/O Processor
51
Digital Applications Interface (DAI)
53
Development Tools
54
Architecture Enhancements
54
Parallel Port Enhancements
54
I/O Architecture Enhancements
55
Instruction Set Enhancements
55
DMA Controller Operation
58
DMA Transfers between Internal Memory
59
General Procedure for Configuring DMA
60
Summary
61
IOP Registers
61
Standard DMA Parameter Registers
62
Standard DMA Status Registers
64
Chaining DMA Status Registers
65
Data Buffers
65
DMA Channel Allocation
66
DMA Channel Priority
67
DMA Channel Arbitration Modes
70
Peripheral DMA Bus
70
Rotating Priority by Group
71
DMA Channel Interrupts
72
Internal Transfer Completion
72
DMA Channel Interrupt Priorities
72
Interrupt Versus Channel Priorities
73
DMA Controller Addressing
74
Internal Index Register Addressing
74
DMA Chaining
76
TCB Memory Storage
76
Chain Pointer Register
77
Chain Assignment
78
Starting Chain Loading
80
TCB Chain Loading Priority
81
Chain Insert Mode (Sports Only)
81
DMA Start and Stop Conditions
81
Configuring Iop/Core Interaction
82
Interrupt-Driven I/O
83
Polling DMA Channel Status
84
Standard DMA Status
85
Chaining DMA Status
85
TCB Storage
86
Serial Port TCB
86
Parallel Port TCB
86
Spi Tcb
87
I/O Processor Register Access
88
IOP Access Conditions
88
Interrupt Latency
89
TCB Chain Loading Access
90
IOP Register Access Arbitration
90
IOP Performance
91
Memory-To-Memory Port Dma
93
Features
94
Functional Description
94
DMA Channels
94
Buffer
95
Interrupts
95
Data Throughput
95
Programming Model
96
Programming Example
96
Parallel Port
99
Features
100
Pin Descriptions
101
Multiplexed Pin Functions
102
Functional Description
102
Multiplexed Operation
102
Address Cycles
102
Data Cycles
103
Data Buffers
104
Read Path
104
Write Path
105
Operation Modes
106
8-Bit Mode
106
16-Bit Mode
107
Parallel Port Registers
108
Control Register (PPCTL)
109
Data Buffer Register (RXPP/TXPP)
109
Data Transfer Types
109
DMA Transfers
110
DMA Internal Word Count Register (ICPP)
110
External Word Count Register (ECPP)
110
Chained DMA Transfers
111
DMA Chain Pointer Register (PPCP)
111
DMA Transfer Rules
111
Core-Driven Transfers
112
Interrupt Driven Accesses
113
Status-Driven Transfers (Polling)
114
Known-Duration Accesses
114
Core-Stall Driven Transfers
115
Interrupts
116
DMA Interrupts
117
Core Interrupts
117
Throughput
117
8-Bit Access
118
16-Bit Access
119
8-Bit Versus 16-Bit SRAM Modes
120
Parallel Port Effect Latency
121
Programming Model
121
Configuring the Parallel Port for DMA
122
Configuring a Chained DMA
122
Configuring the Parallel Port for Core Access
123
Programming Examples
124
Digital Application Interface
127
Features
127
Functional Description
129
Signal Naming Conventions
131
DAI Peripherals
132
I/O Pin Buffers
133
Pin Buffers as Signal Output
134
Pin Buffers as Signal Input
136
Programmable Pull-Up Resistors
137
Pin Buffers as Open Drain
137
Miscellaneous Buffers
138
Signal Routing Matrix by Groups
139
DAI Group Routing
140
Rules for SRU Connections
142
Making SRU Connections
142
Routing Capabilities
146
Default Routing
147
Interrupt Controller
150
System Versus Exception Interrupts
150
Functional Description
151
Interrupt Channels
151
Interrupt Priorities
151
Miscellaneous Interrupts
152
Core Versus DAI Interrupts
152
Interrupt Events
153
Servicing Interrupts
154
Debug Features
155
Shadow Registers
155
Loop Back Routing
156
Programming Model
157
Serial Ports
159
Features
162
Pin Descriptions
164
SRU Configuration
164
SRU SPORT Receive Master
165
SRU SPORT Signal Integrity
165
Functional Description
167
Registers
168
Control Registers (Spctlx)
170
Multichannel Control Registers (Spmctlxy)
170
Data Buffers
171
Transmit Buffers (Txspxa/B)
171
Transmit Path
172
Receive Buffers (Rxspxa/B)
172
Receive Path
173
Buffer Status
173
Multichannel Buffer Status
175
Selecting Operating Modes
176
Mode Selection
177
Data Word Formats
178
Word Length (SLEN)
178
Endian Format (LSBF)
179
Data Packing (PACK)
179
Data Type (DTYPE)
180
Companding the Data Stream
181
Companding as a Function
182
Clock Signal Options
183
Master Clock Divider Registers (DIVX)
183
Master Clock
183
Master Frame Sync
184
Slave Mode
184
Clock Source (ICLK, MSTR)
185
Sampling Edge (CKRE)
185
Frame Sync Options
186
Framed Versus Unframed Frame Syncs
186
Internal Versus External Frame Syncs (IFS, IMFS, MSTR)
187
Logic Level Frame Syncs (LFS, LMFS)
188
Early Versus Late Frame Syncs (LAFS)
189
Data-Independent Frame Sync (One Channel)
190
Data Independent Frame Sync (Two Channels)
191
Operating Modes
192
Standard Serial Mode
192
Timing Control Bits
192
Clocking Options
193
Frame Sync Options
193
Left-Justified Mode
194
Master Serial Clock and Frame Sync Rates
194
Left-Justified Mode Timing Control Bits
195
Frame Sync Channel First (L_FIRST)
195
I 2 S Mode
196
I 2 S Mode Timing Control Bits
197

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Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual (656 pages)

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