Analog Devices ADSP-SC58 Series Hardware Reference Manual page 719

SPI_CTL.SOSI bit is cleared, the order is reversed. Since dual I/O mode uses both pins to transmit or receive
data, only one channel can be enabled, either transmit or receive. Flow control through the SPI_RDY pin is sup-
ported. Interrupt request generation is unaffected by dual I/O mode. However, the interrupt service interval is re-
duced, since the individual transfer latency is halved.
Changing to quad SPI mode must be done when the SPI is in a quiescent state.
Figure 16-8: Dual I/O Mode Transfer Protocol for CPHA=0, SOSI=1, 8-Bit Transfer, LSBF=0.
Figure 16-9: Dual I/O Mode Transfer Protocol for CPHA=1, SOSI=0, 8-Bit Transfer, LSBF=0.
Quad I/O Mode (SPI2 only)
In quad SPI mode, the SPI_MISO and SPI_MOSI pins, in tandem with the SPI_D2 and SPI_D3 pins, are
configured to operate in the same direction. The SPI uses the SPI_CTL.SOSI bit to determine the order of bits
on the pins. When set, the processor sends:
• The first bit on the SPI_MOSI pin
• The second bit on the SPI_MISO pin
• The third bit on the SPI_D2 pin
• The fourth bit on the SPI_D3 pin
If the SPI_CTL.SOSI bit is cleared, the order is reversed. Since quad SPI mode uses all four pins to transmit or
receive data, only one channel can be enabled as either transmit or receive. Flow control through the SPI_RDY pin
is supported. Interrupt generation is unaffected by quad SPI mode.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Cycle
1
Number
SPI_CLK
(CPOL=0)
SPI_CLK
(CPOL=1)
MSB
SPI_MOSI
SPI_MISO 6
Slave
Select
Cycle
1
Number
SPI_CLK
(CPOL=0)
SPI_CLK
(CPOL=1)
6
SPI_MOSI
SPI_MISO MSB
Slave
Select
3 4
2
1
5 3
4 2 LSB
2 3 4
4 2 LSB
1
5 3
SPI Functional Description
16–13