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ADSP-SC58x GICDST Register Descriptions
Shared Peripheral Interrupt Security Register
The
GICDST_SPI_SECURITY[n]
GIC.
VALUE[31:16] (R/W)
Shared Peripheral Interrupt Security
Interrupt Security
Figure 7-46: GICDST_SPI_SECURITY[n] Register Diagram
Table 7-47: GICDST_SPI_SECURITY[n] Register Fields
Bit No.
(Access)
31:0
VALUE
(R/W)
7–78
register provides a security status bit for each interrupt supported by the
15
0
VALUE[15:0] (R/W)
Shared Peripheral Interrupt Security
Interrupt Security
31
0
Bit Name
Shared Peripheral Interrupt Security Interrupt Security.
The GICDST_SPI_SECURITY[n].VALUE bits control the security status of the
corresponding interrupt.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
Description/Enumeration
6
5
4
3
2
1
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
0
0
0
0
0
0
0
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