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ADSP-SC58x PORT Register Descriptions
Port x GPIO Data Clear Register
The
PORT_DATA_CLR
mode or input mode. For more information, see the
PX15 (R/W1C)
Port x Bit 15 Data Clear
PX14 (R/W1C)
Port x Bit 14 Data Clear
PX13 (R/W1C)
Port x Bit 13 Data Clear
PX12 (R/W1C)
Port x Bit 12 Data Clear
PX11 (R/W1C)
Port x Bit 11 Data Clear
PX10 (R/W1C)
Port x Bit 10 Data Clear
PX9 (R/W1C)
Port x Bit 9 Data Clear
PX8 (R/W1C)
Port x Bit 8 Data Clear
Figure 14-8: PORT_DATA_CLR Register Diagram
Table 14-9: PORT_DATA_CLR Register Fields
Bit No.
(Access)
15
PX15
(R/W1C)
14
PX14
(R/W1C)
14–18
register operates differently for port bits/pins, depending on whether the bit/pin is output
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Port x Bit 15 Data Clear.
The PORT_DATA_CLR.PX15 bit clears the pin without impacting other pins of the
port.
Port x Bit 14 Data Clear.
The PORT_DATA_CLR.PX14 bit clears the pin without impacting other pins of the
port.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
PORT_DATA
register description.
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 No Effect
1 Clear Bit. Write 1 for signal low in output mode.
0 No Effect. Write 0 has no effect in output mode.
1 Clear Bit. Write 1 for signal low in output mode.
1
0
0
0
PX0 (R/W1C)
Port x Bit 0 Data Clear
PX1 (R/W1C)
Port x Bit 1 Data Clear
PX2 (R/W1C)
Port x Bit 2 Data Clear
PX3 (R/W1C)
Port x Bit 3 Data Clear
PX4 (R/W1C)
Port x Bit 4 Data Clear
PX5 (R/W1C)
Port x Bit 5 Data Clear
PX6 (R/W1C)
Port x Bit 6 Data Clear
PX7 (R/W1C)
Port x Bit 7 Data Clear
17
16
0
0
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