Analog Devices ADSP-SC58 Series Hardware Reference Manual page 802

Glitch filtering is accomplished by counting 16 system clocks from the time the receiver detects an initial pulse. If
the pulse is absent when the counter expires, the receiver interprets it as a glitch. Otherwise, the receiver interprets it
as a zero. This assessment is acceptable because glitches originating from on-chip capacitive cross-coupling typically
do not last for more than a fraction of the system clock (SCLK0_0) period. Appropriate shielding avoids sources
outside of the chip and not part of the transmitter. The only other source of a glitch is the transmitter itself. The
processor relies on the transmitter to perform within specification. If the transmitter violates the specification, un-
predictable results can occur. The 4-bit counter adds an extra level of protection at a minimal cost.
Because SCLK0_0 can change across systems, the longest glitch tolerated is inversely proportional to the
NOTE:
SCLK0_0 frequency.
A counter that is clocked at the 16x bit-time sample clock determines the receive sampling window. The sampling
window is resynchronized with each start bit by centering the sampling window around the start bit.
The polarity of receive data is selectable, using the UART_CTL.RPOLC bit. The IrDA Receiver Pulse Detection
figure provides examples of each polarity type.
Figure 17-8: IrDA Receiver Pulse Detection
MDB Transmit Operation
In MDB mode, receive and transmit paths operate independently from each other, except for sharing bit rate and
frame formats for both transfer directions.
Transmit operation is initiated by writing the
register transmits the written word with the appending address bit set low. A write to the
transmits the written word with the appended address bit set high. The data is moved into the
where it is shifted out at the bit rate programmed by the
bits appended, as required.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
0
RECEIVED
IrDA
PULSE
IR POL = 1
0
RECEIVED
IrDA
PULSE
IR POL = 0
8/16
SAMPLING
WINDOWN
PULSE
DETECT
OR
OUTPUT
RECOVERED
NRZ INPUT
UART_THR
1
1
16/16 8/16
0
1
or registers. A write to the
UART_TAIP
register, with start, stop, address, and parity
UART_CLK
UART Data Transfer Modes
16/16
UART_THR
UART_TAIP register
UART_TSR register,
17–15