Functional Description; A5 Block Diagram; Control Co-Processor (Cp15) - Analog Devices ADSP-SC58 Series Hardware Reference Manual

Functional Description

• Generic Interrupt Controller (GIC)
• Level 2 Cache Controller (L2CC)
• Memory Management Unit (MMU)
Functional Description
The following sections provide information on the function of the sub-system.

A5 Block Diagram

The following figure shows the primary blocks of the Cortex A5 sub-system. The performance increases with access-
es to lower levels of memory as follows:
1. Level 1 – cache on-chip, separate data/code (highest)
2. Level 2 – cache on-chip, unified
3. Level 3 – memory external, (lowest)
Figure 2-1: A5 Sub-System Block Diagram

Control Co-Processor (CP15)

The system control co-processor, CP15, controls and provides status information for the functions implemented in
the processor. The main functions of the system control co processor are:
2–2
EMBEDDED TRACE MACROCELL CoreSight INTERFACE
(ETM) INTERFACE
DEBUG
DATA PROCESSING UNIT (DPU)
DATA MICRO-TLB
DATA CACHE
DATA STORE
UNIT (DCU)
BUFFER (STB)
32 KB
BUS INTERFACE UNIT (BIU)
ARM Cortex-A5 BUS MASTER PORT
GENERIC INTERRUPT
CONTROLLER
®
(PrimeCell PL-390)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
TM
NEON MEDIA
CP15
PROCESSING
ENGINE
PREFETCH UNIT AND BRANCH PREDICTOR (PFU)
INSTRUCTION MICRO-TLB
INSTRUCTION CACHE
MAIN TRANSMISSION
LOOKINSIDE BUFFER (TLB)
L2 CACHE
DATA MASTER PORTS
CONTROLLER
SHARC PROCESSORS
(CoreLink TM PL-310)
256 KB
SYSTEM FABRIC
CORTEX-A5
PROCESSOR
UNIT (ICU)
32 KB
TO OTHER CORES