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ADSP-SC58x DPM Register Descriptions
Control Register
The
register controls sleep modes selections and PLL operations of the DPM. A write protect feature
DPM_CTL
permits locking out changes to this register.
Figure 5-1: DPM_CTL Register Diagram
Table 5-5: DPM_CTL Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
5–6
15
14
13
0
0
0
31
30
29
0
0
0
LOCK (R/W)
Lock
Bit Name
Lock.
If the global lock bit is set (SPU_CTL.GLCK bit =1) and the DPM_CTL.LOCK bit is
set, the
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
DPM_CTL
register is read only (locked).
0 Unlock
1 Lock
4
3
2
1
0
0
0
0
0
0
20
19
18
17
16
0
0
0
0
0
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