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Latency
The SMPU adds latency to all the transactions to the memory except reads when read speculation is enabled
(SMPU_CTL.RSDIS =0). In this case, read accesses are always forwarded to the memory and read responses are
generated according to the SMPU settings. If read speculation is disabled (SMPU_CTL.RSDIS =1), reads are
blocked if they cause a security or protection violation. The SMPU generates the SCB read response that corre-
sponds to a blocked transaction.
If read speculation is enabled, the SMPU adds 1 clock cycle latency to the read transaction. If read speculation is
disabled, the SMPU adds 2 clock cycles latency to the read transaction.
SMPU Operating Modes
The SMPU does not have any strict modes of operation. However, it can be configured for region-based protection
where a master with a particular ID can be blocked or allowed based on settings in the
Region-based protection is programmed with registers:
•
SMPU_RCTL[n]
•
SMPU_RADDR[n]
•
SMPU_RIDA[n]
•
SMPU_RIDMSKA[n]
•
SMPU_RIDB[n]
•
SMPU_RIDMSKB[n]
Exclusive Accesses. On the ADSP-SC5xx processors, the hardware supports the exclusive accesses. The exclusive ac-
cesses are supported for the SMPU instances that correspond to SMC, DMC 0, DMC 1 and Core_L2_0. The ex-
clusive accesses are automatically enabled when one of the cores (ARM Core 0, SHARC+ Core 1, and SHARC+
Core 2) executes the exclusive access instruction. Refer to the Programming Reference manual for more details on
how the exclusive access works.
SMPU Interrupt Signals
There is one interrupt signal associated with the SMPU. If interrupts are enabled, the SMPU_STAT.IRQ bit is set.
The SMPU_IRQ signal is asserted when the SMPU detects a memory access violation. The target address triggering
the interrupt is found in the
cause of the interrupt.
Write errors are prioritized over read errors.
Protection violations (an ID-based violation) can trigger the SMPU interrupt, and can be enabled independently.
The protection violation interrupt is enabled by setting the SMPU_CTL.PINTEN bit.
The SMPU interrupt is asserted for any of the following conditions:
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SMPU_IADDR
register. The
SMPU_IDTLS
register provides further details about the
SMPU Operating Modes
SMPU_RCTL[n]
register.
13–11
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