Page 1 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference Revision 1.0, September 2017 Part Number 82-100129-01...
Page 2 Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Ana- log Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.
Page 3: Table Of Contents
Contents Introduction Power and Clock Management (DPM/RCU/CGU/CDU) ................1–2 System Interrupts and Triggers (SEC/TRU) ....................1–3 System Memory (L2CTL/DMC/SMC/OTPC/SMPU) ................. 1–4 Direct Memory Access (DMA/MDMA/EMDMA/CRC)................1–7 Peripherals ..............................1–9 General-Purpose I/O (GPIO) Peripherals....................1–9 DAI/SRU Peripherals ..........................1–14 Dedicated Pin Peripherals......................... 1–15 System Accelerators (FFT/FIR/IIR/HAE/SINC) ..................
Page 4 A5 Configurations ............................2–7 Clock Generation Unit (CGU) CGU Features ..............................3–1 CGU Functional Description......................... 3–1 ADSP-SC58x CGU Register List........................ 3–2 ADSP-SC58x CGU Interrupt List ......................3–2 ADSP-SC58x CGU Trigger List ......................... 3–3 CGU Definitions............................3–3 CGU PLL Block Diagram .......................... 3–4 CGU Operating Modes ..........................
Page 5 Oscillator Watchdog Register ........................3–24 PLL Control Register ..........................3–26 Revision ID Register ..........................3–28 System Clock Buffer Disable Register ...................... 3–29 System Clock Buffer Status Register ......................3–31 Status Register ............................3–33 Time Stamp Counter 32 LSB Register ..................... 3–36 Time Stamp Counter 32 MSB Register ....................
Page 6 DPM Definitions ............................5–1 DPM Operating Modes ..........................5–2 Reset State ..............................5–2 Full-on Mode.............................. 5–2 DPM Event Control ............................5–3 DPM Programming Model..........................5–3 ADSP-SC58x DPM Register Descriptions ....................5–5 Control Register ............................5–6 Peripherals Disable Register 0 ........................5–7 Peripherals Disable Register 1 ........................
Page 7 Message Set Bits Register ......................... 6–20 System Interface Disable Register ......................6–21 System Interface Status Register ......................6–22 Status Register ............................6–23 Software Vector Register 0 ........................6–25 Software Vector Register 1 ........................6–26 Software Vector Register 2 ........................6–27 SVECT Lock Register ..........................
Page 8 Core/SEC Handshaking Requirements to Ensure Proper Interrupt Handling ........7–20 Configuring a System Source as a Fault ....................7–20 Configuring the WDOG Expiry Event to Issue a System Reset ............. 7–21 SEC Programming Restrictions ........................ 7–21 ADSP-SC58x SEC Register Descriptions ....................7–22 SCI Active Register n ..........................
Page 9 GIC Functional Description ........................7–59 GIC Block Diagram ..........................7–60 ADSP-SC58x GICDST Register List ....................7–60 ADSP-SC58x GICCPU Register List....................7–60 ADSP-SC58x GICDST Register Descriptions ..................7–61 GIC Port 0 Enable ..........................7–62 Software Generated Interrupt Priority Register ................. 7–63 Shared Peripheral Interrupt Priority Register ..................
Page 10 GIC Port 0 Enable ........................... 7–89 Software Generated Interrupt Priority Register ..................7–90 Shared Peripheral Interrupt Priority Register ................... 7–91 Software Generated Interrupt Active Register ..................7–92 Software Generated Interrupt Control Register ..................7–93 Software Generated Interrupt Clear-Pending Register ................7–95 Software Generated Interrupt Pending Set Register .................
Page 11 Configuring a Simple Trigger Sequence....................8–14 Toggle a GPIO on Timer Expiry Event ....................8–14 TRU Event Control ............................. 8–14 TRU Status and Error Signals........................8–14 ADSP-SC58x TRU Register Descriptions ....................8–14 Error Address Register ..........................8–16 Global Control Register ........................... 8–17 Master Trigger Register ...........................
Page 12 Error Type 0 Address Register ......................... 9–16 Error Type 1 Address Register ......................... 9–17 ECC Error Address 0 Register ......................... 9–18 ECC Error Address 1 Register ......................... 9–19 ECC Error Address 2 Register ......................... 9–20 ECC Error Address 3 Register ......................... 9–21 ECC Error Address 4 Register .........................
Page 13 Page and Bank Interleaving ........................10–7 System Crossbar Slave Interface........................ 10–7 Read/Write Command and Data Buffers....................10–8 Peripheral Bus Slave Interface ........................10–8 Architectural Concepts ..........................10–8 Controller On Die Termination (ODT)....................10–9 Mode Register Set and Extended Mode Register Set Command ............10–9 DDR3 Reset Functionality ........................
Page 14 Data Calibration Data 0 Register ......................10–33 Data Calibration Data 1 Register ......................10–34 Efficiency Control Register ........................10–35 Shadow EMR1 DDR2 Register ......................10–39 Shadow EMR2 Register (DDR2)/Shadow EMR Register (LPDDR) ............. 10–41 Shadow MR Register (DDR2/LPDDR), Shadow MR0 Register (DDR3) ..........10–43 Shadow MR1 Register (DDR3) ......................
Page 15 Static Memory Controller (SMC) SMC Features .............................. 11–1 SMC Definitions ............................11–1 SMC Functional Description ........................11–3 ADSP-SC58x SMC Register List......................11–4 SMC Architectural Concepts ........................11–4 Avoiding Bus Contention ........................11–5 ARDY Input Control ..........................11–6 SMC Operating Modes..........................11–6 Asynchronous Flash Mode........................
Page 16 Bank 2 Control Register ........................11–33 Bank 2 Extended Timing Register ......................11–36 Bank 2 Timing Register ......................... 11–38 Bank 3 Control Register ........................11–40 Bank 3 Extended Timing Register ......................11–43 Bank 3 Timing Register ......................... 11–45 One-Time Programmable Memory Controller (OTPC) OTPC Features............................
Page 17 Memory Writes............................13–4 Memory Reads ............................13–4 ID Comparison ............................13–5 Memory Region............................13–8 SMPU Definitions ........................... 13–9 SMPU Block Diagram..........................13–10 SMPU Architectural Concepts ....................... 13–10 SMPU Operating Modes ........................... 13–11 SMPU Interrupt Signals ..........................13–11 SMPU Status and Error Signals ......................... 13–12 SMPU Programming Example........................
Page 18 General-Purpose Ports (PORT) PORT Features ............................14–2 PORT Functional Description........................14–2 ADSP-SC58x PORT Register List......................14–3 ADSP-SC58x PINT Register List......................14–3 ADSP-SC58x PINT Interrupt List ......................14–4 ADSP-SC58x PINT Trigger List ......................14–4 ADSP-SC58x PADS Register List......................14–5 PORT Architectural Concepts........................14–5 Internal Interfaces ..........................
Page 19 Port x GPIO Input Enable Register ....................... 14–48 Port x GPIO Input Enable Clear Register ....................14–51 Port x GPIO Input Enable Set Register ....................14–54 Port x GPIO Lock Register ........................14–57 Port x Multiplexer Control Register ....................... 14–59 Port x GPIO Polarity Invert Register .....................
Page 20 ADSP-SC58x LP DMA Channel List....................... 15–3 Block Diagram............................15–3 External Connections ..........................15–3 Internal Blocks ............................15–4 Architectural Concepts ..........................15–4 Link Port Protocol..........................15–4 FIFO Buffers ............................15–7 Handshake for Link Port Enable Process ....................15–9 Clocking ............................. 15–10 Multi-Processor Connectivity ......................
Page 21 Shadow Output Transmit Buffer Register ....................15–26 Serial Peripheral Interface (SPI) SPI Features..............................16–1 SPI Functional Description.......................... 16–2 ADSP-SC58x SPI Register List ........................ 16–2 ADSP-SC58x SPI Interrupt List ......................16–3 ADSP-SC58x SPI Trigger List........................16–4 ADSP-SC58x SPI DMA Channel List...................... 16–5 SPI Block Diagram...........................
Page 22 SPI Interrupt Signals ..........................16–28 Data Interrupts............................16–28 Status Interrupts............................. 16–29 Error Conditions ............................ 16–29 SPI Programming Concepts........................16–30 Master Operation in Non-DMA Modes ....................16–30 Slave Operation in Non-DMA Modes ....................16–31 Configuring DMA Master Mode......................16–32 Configuring DMA Slave Mode Operation....................16–33 ADSP-SC58x SPI Register Descriptions ....................
Page 23 Universal Asynchronous Receiver/Transmitter (UART) UART Features ............................17–1 UART Functional Description ........................17–2 ADSP-SC58x UART Register List......................17–2 ADSP-SC58x UART Interrupt List ......................17–3 ADSP-SC58x UART Trigger List ......................17–4 ADSP-SC58x UART DMA Channel List ....................17–4 UART Block Diagram ..........................17–5 UART Architectural Concepts ........................
Page 24 Interrupt Masks............................17–18 Interrupt Servicing ..........................17–18 Transmit Interrupts ..........................17–19 Receive Interrupts........................... 17–20 Status Interrupts............................. 17–21 Multi-Drop Bus Events........................... 17–22 UART Programming Model ........................17–22 Detecting Autobaud ..........................17–22 Using Common Initialization Steps......................17–23 Using Core Transfers ..........................17–23 Using DMA Transfers..........................
Page 25 EPPI Features .............................. 18–1 EPPI Functional Description ........................18–2 ADSP-SC58x EPPI Register List......................18–3 ADSP-SC58x EPPI Interrupt List ......................18–3 ADSP-SC58x EPPI Trigger List ....................... 18–4 RGB Data Formats ........................... 18–4 Data Clipping............................18–4 Data Mirroring............................18–5 Windowing............................... 18–6 Preamble, Blanking and Stripping Support....................18–6 EPPI Definitions ............................
Page 26 Data Enable in General-Purpose 2 Frame Sync Transmit Mode ............18–21 General-Purpose 3 Frame Sync Mode....................18–21 Supported Data Formats ........................18–22 Receive Data Formats .......................... 18–22 Transmit Data Formats ........................18–24 Data Transfer Modes ..........................18–25 Data Packing for Receive Modes ......................18–25 Data Packing for Transmit Modes .......................
Page 27 Configuring 16-Bit Receive Mode ....................... 18–37 Configuring 18-Bit Receive Mode ....................... 18–38 Configuring 8-Bit Split Receive Mode....................18–39 Configuring 10/12/14/16-Bit Split Receive Mode with SPLTWRD=0 ..........18–42 Configuring 16-Bit Split Receive Mode with SPLTWRD=1..............18–43 Configuring 8-Bit Transmit Mode....................... 18–44 Configuring 10/12/14-Bit Transmit Modes ..................
Page 28 Vertical Transfer Count Register ......................18–81 Vertical Delay Count Register ........................ 18–82 Pulse-Width Modulator (PWM) PWM Features ............................19–1 Functional Description ..........................19–1 ADSP-SC58x PWM Register List ......................19–2 ADSP-SC58x PWM Interrupt List ......................19–4 ADSP-SC58x PWM Trigger List......................19–5 PWM Definitions.............................
Page 29 Output Disable and Cross-Over Modes....................19–26 Brushless DC Motor (Electronically Commutated Motor) Control............. 19–27 Heightened-Precision Edge Placement ....................19–28 Sample Waveforms for High- and Low-Side with Precision Placement..........19–30 Emulation Mode............................. 19–32 Event Control ............................19–32 Trip Control Unit ..........................19–33 Programming Model ..........................
Page 30 Channel B-High Duty-1 Register ......................19–61 Channel B-High Heightened-Precision Duty-1 Register ............... 19–62 Channel B-High Full Duty0 Register ....................19–63 Channel B-High Full Duty1 Register ....................19–64 Channel B-Low Duty-0 Register ......................19–65 Channel B-Low Heightened-Precision Duty-0 Register ................. 19–66 Channel B-Low Duty-1 Register ......................
Page 31 Channel D Control Register ........................ 19–101 Channel D-High Duty-0 Register ....................... 19–103 Channel D-High Pulse Heightened-Precision Duty Register 0 ............19–104 Channel D-High Pulse Duty Register 1 ....................19–105 Channel D High Pulse Heightened-Precision Duty Register 1 ............19–106 Channel D-High Full Duty0 Register ....................19–107 Channel D-High Full Duty1 Register ....................
Page 32 ADSP-SC58x TIMER Register List......................20–2 ADSP-SC58x TIMER Interrupt List ....................... 20–2 ADSP-SC58x TIMER Trigger List ......................20–3 Timer Block Diagram..........................20–4 Internal Interface ............................20–4 Internal Timer Connections ........................20–4 External Interface ............................. 20–5 GP Timer Operating Modes ........................20–5 General Operation............................
Page 33 ADSP-SC58x TIMER Register Descriptions .................... 20–25 Broadcast Delay Register ........................20–26 Broadcast Period Register ........................20–27 Broadcast Width Register ........................20–28 Data Interrupt Latch Register ........................ 20–29 Data Interrupt Mask Register ........................ 20–30 Error Type Status Register ........................20–31 Run Register ............................20–33 Run Clear Register ..........................
Page 34 External Interface ............................ 21–4 ADSP-SC58x WDOG Register Descriptions ....................21–4 Count Register ............................21–5 Control Register ............................21–6 Watchdog Timer Status Register ......................21–7 Real Time Clock (RTC) RTC Features............................... 22–1 RTC Functional Description........................22–1 ADSP-SC58x RTC Register List ......................22–2 ADSP-SC58x RTC Interrupt List ......................
Page 35 Register Access............................22–10 ADSP-SC58x RTC Register Descriptions ....................22–11 RTC Alarm Register ..........................22–12 RTC Clock Register ..........................22–13 Interrupt Enable Register ........................22–14 RTC Initialization Register ........................22–16 RTC Initialization Status Register ......................22–17 RTC Status Register ..........................22–18 RTC Stop Watch Register ........................
Page 36 Configuring Boundary Compare and Boundary Zero Modes ..............23–8 Configuring GP Counter Push-Button Operation ................23–8 GP Counter Programming Concepts......................23–8 CNT Input Noise Filtering ........................23–8 Capturing Counter Interval and CNT_CNTR Read Timing ..............23–9 Capturing Time Interval Between Successive Counter Events ............. 23–11 GP Counter Event Control ........................
Page 37 ACM External Pin Timing ........................24–6 ACM Architectural Concepts........................24–10 Clocking.............................. 24–10 Block Diagram ............................ 24–10 Trigger Inputs ............................. 24–11 Timers..............................24–13 Event Register Pairs..........................24–14 Event Comparators Unit ........................24–14 Timing Generation Unit ........................24–15 Status Flags and Interrupts ........................24–15 Event Order Registers..........................
Page 38 CAN Functional Description ........................25–2 ADSP-SC58x CAN Register List......................25–2 ADSP-SC58x CAN Interrupt List ......................25–3 External Interface ............................. 25–4 Architectural Concepts ..........................25–4 Block Diagram ............................25–5 Mailbox Control............................ 25–6 Protocol Fundamentals.......................... 25–7 CAN Operating Modes..........................25–8 Data Transfer Modes ..........................25–8 Transmit Operations ..........................
Page 39 Programmable Warning Limits ......................25–20 Error Handling............................ 25–20 Error Frames ............................25–21 Error Levels ............................25–22 CAN Debug and Test Modes........................25–23 ADSP-SC58x CAN Register Descriptions ....................25–25 Abort Acknowledge 1 Register ....................... 25–28 Abort Acknowledge 2 Register ....................... 25–29 Acceptance Mask (H) Register .......................
Page 40 Mailbox Word 3 Register ........................25–61 Mailbox ID 0 Register ........................... 25–62 Mailbox ID 1 Register ........................... 25–63 Mailbox Length Register ........................25–64 Mailbox Time Stamp Register ....................... 25–65 Mailbox Configuration 1 Register ......................25–66 Mailbox Configuration 2 Register ......................25–67 Mailbox Direction 1 Register .........................
Page 41 MSI Features..............................26–1 MSI Functional Description ........................26–2 ADSP-SC58x MSI Register List ....................... 26–2 ADSP-SC58x MSI Interrupt List ......................26–4 ADSP-SC58x MSI Trigger List......................... 26–4 MSI Block Diagram..........................26–4 MSI Architectural Concepts ........................26–5 Bus Interface Unit (BIU)........................26–6 Host Interface Unit (HIU) ......................... 26–6 Interrupt Controller Unit ........................
Page 42 Data Transmit ............................26–23 Data Receive............................26–25 Data Transfer Commands........................26–27 Transmission and Reception with Internal DMAC (IDMAC) ..............26–27 MSI Event Control ............................ 26–27 MSI Status and Error Signals........................26–28 MSI Programming Model.......................... 26–30 MSI Programming Concepts ........................26–30 Initializing the MSI ..........................
Page 43 Current Buffer Descriptor Address Register ................... 26–55 Bus Mode Register ..........................26–56 Byte Count Register ..........................26–58 Card Detect Register ..........................26–59 Card Threshold Control Register ......................26–60 Clock Divider Register .......................... 26–61 Clock Enable Register ..........................26–62 Command Register ..........................26–63 Command Argument Register .......................
Page 44 Universal Serial Bus (USB) USB Features ............................... 27–1 USB Functional Description........................27–2 USB Architectural Concepts ........................27–2 Multi-Point Support..........................27–3 On-Chip Bus Interfaces......................... 27–4 FIFO Configuration ..........................27–4 Clocking..............................27–5 UTMI Interface ............................ 27–5 ADSP-SC58x USB Register List....................... 27–5 ADSP-SC58x USB Interrupt List ......................27–8 ADSP-SC58x USB Trigger List ........................
Page 45 Peripheral Mode, Bulk IN, Transfer Size Unknown ................. 27–27 Peripheral Mode, ISO IN, Small MaxPktSize................... 27–28 Peripheral Mode, ISO IN, Large MaxPktSize .................. 27–28 Peripheral Mode, Bulk OUT, Transfer Size Known................27–29 Peripheral Mode, Bulk OUT, Transfer Size Unknown..............27–29 Peripheral Mode, ISO OUT, Small MaxPktSize................
Page 46 Host Mode Reset..........................27–42 Host Mode Suspend ..........................27–43 Suspending and Resuming the Controller ................... 27–43 Suspend or Resume by Inactivity on the USB Bus (L0 to L2 State) in Peripheral Mode....27–43 Suspend or Resume by Inactivity on the USB Bus (L0 To L2 State) in Host Mode......27–44 Suspend or Resume by an LPM Transaction (L0 To L1 State) in Peripheral Mode......
Page 47 Battery Charging Control Register ......................27–78 Host High-Speed Return to Normal Register ..................27–79 High-Speed Timeout Register ....................... 27–80 Chirp Timeout Register ......................... 27–81 Device Control Register ......................... 27–82 DMA Channel n Address Register ......................27–84 DMA Channel n Count Register ......................27–85 DMA Channel n Control Register ......................
Page 48 EPn Transmit Polling Interval Register ....................27–139 EPn Transmit Maximum Packet Length Register ................27–140 EPn Transmit Type Register ........................ 27–141 EPn Number of Bytes Received Register ....................27–143 EPn Receive Configuration and Status (Host) Register ................ 27–144 EPn Receive Configuration and Status (Peripheral) Register ..............27–149 EPn Receive Polling Interval Register ....................
Page 49 LPM Attribute Register ........................27–196 LPM Control Register ......................... 27–197 LPM Function Address Register ......................27–199 LPM Interrupt Enable Register ......................27–200 LPM Interrupt Status Register ......................27–202 Low-Speed EOF 1 Register ........................27–205 MPn Receive Function Address Register ....................27–206 MPn Receive Hub Address Register .....................
Page 50 Functional Description ..........................28–3 ADSP-SC58x MLB Register List......................28–4 ADSP-SC58x MLB Interrupt List ......................28–5 Media LB Protocol ........................... 28–5 MLB Architectural Concepts ........................28–6 MediaLB Block Diagram .......................... 28–6 MediaLB Interface............................ 28–7 Routing Fabric............................28–8 Data Buffer RAM..........................28–8 Channel Table RAM ..........................
Page 51 ADSP-SC58x MLB Register Descriptions ....................28–27 Peripheral Channel Mask 0 Register ...................... 28–29 Peripheral Channel Mask 1 Register ...................... 28–30 Peripheral Channel Status 0 Register ..................... 28–31 Peripheral Channel Status 1 Register ..................... 28–32 Bus Control Register ..........................28–33 MediaLB Control 0 Register ........................28–35 Control 1 Register ..........................
Page 52 System Status Register ........................... 28–62 MediaLB 6-pin Control 0 Register ......................28–64 PCI Express PCIe Features .............................. 29–2 Functional Description ..........................29–3 ADSP-SC58x PCIE Register List ......................29–3 ADSP-SC58x PCIE Interrupt List ......................29–10 ADSP-SC58x PCIE Trigger List......................29–10 Definitions ............................. 29–10 Top-level Block Diagram and Description ....................
Page 53 Inbound Programming Example (BAR Match Mode) ................. 29–33 Inbound Programming Example (Address Match Mode)..............29–34 Outbound Programming Example ...................... 29–35 Non DMA Transfers..........................29–36 Transmit Transaction Layer Packets (TLP) ..................29–36 Receive Transaction Layer Packets (TLP) .................... 29–37 DMA Transfers............................29–37 Read Transfer ............................
Page 54 Enumeration............................29–50 Enumeration Driver Example......................29–51 DMA Transfers............................29–52 DMA Write Transfer Example......................29–52 DMA Read Transfer Example......................29–53 Device Reset ............................29–53 Cold Reset............................29–54 Hot Reset ............................29–54 ADSP-SC58x Product Specific Information ....................29–55 ADSP-SC58x PCIE Register Descriptions ....................29–56 Acknowledge Frequency and L0-L1 ASPM Control Register ..............
Page 55 Peripheral and SCB Bridge Slave Error Response Register ..............29–93 Bus Order Manager Watchdog Off Register ..................29–94 Bus Multiple Outbound Decomposition SubReq Control Register ............29–95 ACE Cache Coherency Control Register 1 ..................... 29–96 ACE Cache Coherency Control Register 3 ..................... 29–97 PCIe Capabilities, ID, Next Pointer Register ..................
Page 56 DMA SAR High Read Channel Register ..................... 29–136 DMA SAR Low Read Channel Register ....................29–137 DMA Transfer Size Read Channel Register ..................29–138 DMA Write Abort IMWr Address High Register ................. 29–139 DMA Write Abort IMWr Address Low Register .................. 29–140 DMA Write Channel Arbitration Weight Low Off Register ..............
Page 57 Endpoint Base Address Register 1 ......................29–168 Endpoint Base Address Mask Register 2 ....................29–169 Endpoint Base Address Register 2 ......................29–170 Endpoint Base Address Mask Register 3 ....................29–171 Endpoint Base Address Register 3 ......................29–172 Endpoint Base Address Mask Register 4 ....................29–173 Endpoint Base Address Register 4 ......................
Page 58 iATU Region Control 3 Register ......................29–211 iATU Region Control 3 Register ......................29–212 IATU Lower Base Inbound Address Register ..................29–213 IATU Lower Base Outbound Address Register ..................29–214 IATU Inbound Limit Address Register ....................29–215 IATU Outbound Limit Address Register ..................... 29–216 IATU Lower Target Address Inbound Register ..................
Page 59 MSI Controller Interrupt 4 Enable Register ..................29–252 MSI Controller Interrupt 5 Enable Register ..................29–253 MSI Controller Interrupt 6 Enable Register ..................29–254 MSI Controller Interrupt 7 Enable Register ..................29–255 MSI Controller Interrupt 0 Mask Register ..................29–256 MSI Controller Interrupt 1 Mask Register ..................
Page 60 Queue Status Register .......................... 29–290 Interrupt Bridge Line and Pin Control Register .................. 29–291 Capability Pointer Register........................29–294 Class Code and Revision ID Register ....................29–295 Root Complex Configuration Register ....................29–296 Root Control and Capabilities Register ....................29–297 Device Capabilities Register ........................
Page 61 Segmented-Buffer VC0 Completion Receive Queue Control Register ..........29–336 Segmented-Buffer VC0 Non-Posted Receive Queue Control Register ..........29–337 Segmented-Buffer VC0 Posted Receive Queue Control Register ............29–338 Virtual Channel Transmit Arbitration Register 1 ................. 29–340 Virtual Channel Transmit Arbitration Register 2 ................. 29–342 Vendor Specific DLLP Register ......................
Page 62 Clock Stretching During Repeated Start....................30–11 TWI Programming Model......................... 30–12 General Setup ............................30–12 Slave Mode ............................. 30–13 Master Mode Program Flow ........................30–14 Master Mode Clock Setup ........................30–15 Master Mode Transmit ........................... 30–15 Master Mode Receive..........................30–16 ADSP-SC58x TWI Register Descriptions ....................30–17 SCL Clock Divider Register ........................
Page 63 ADSP-SC58x EMAC Interrupt List ...................... 31–10 ADSP-SC58x EMAC Trigger List ......................31–11 EMAC Definitions ..........................31–11 EMAC Block Diagram and Interfaces..................... 31–12 EMAC CORE Subblocks ........................31–14 EMAC PHY Interface ......................... 31–16 RGMII Board Design Recommendations.................... 31–17 Clock Sources ............................31–19 EMAC Architectural Concepts .......................
Page 64 SMI Read Operation........................31–68 EMAC Management Counters (MMC) ....................31–68 MMC Receive Interrupt Register ....................31–70 MMC Transmit Interrupt Register ....................31–70 MMC Receive Checksum Offload Interrupt Register ..............31–70 EMAC Precision Time Protocol (PTP) Engine ................... 31–70 IEEE1588 and the PTP Engine ....................... 31–70 Block Diagram ..........................
Page 65 Performing Normal Transmit and Receive Operations ..............31–104 Stopping and Starting Transfers ......................31–104 Interrupts and Interrupt Service Routines ..................31–105 Enabling Checksum for Transmit and Receive .................. 31–106 Programming the System Time Module .................... 31–106 Programming the PTP for Frame Detection and Time Stamping............31–107 Programming for Auxiliary Time Stamps ..................
Page 66 DMA Rx Descriptor Current Register ....................31–143 DMA Rx Interrupt Watch Dog Register ....................31–144 DMA Rx Poll Demand register ......................31–145 DMA Status Register ........................... 31–146 DMA Tx Buffer Current Register ......................31–151 DMA Tx Descriptor List Address Register ..................31–152 DMA Tx Descriptor Current Register ....................
Page 67 Channel 2 Credit Shaping Control Register ..................31–190 Channel 2 Avg Traffic Transmitted Status Register ................31–191 Channel 2 High Credit Value Register ....................31–192 Channel 2 Idle Slope Credit Value Register ..................31–193 Channel 2 Low Credit Value Register ....................31–194 Channel 2 Control Bits for Slot Function Register ................
Page 68 Layer 3 Address1 Register ........................31–241 Layer 3 Address2 Register ........................31–242 Layer 3 Address3 Register ........................31–243 Layer 4 Address Register ........................31–244 Low Power Idle Control and Status Register ..................31–245 Low Power Idle Timeout Register ......................31–247 MAC Configuration Register .......................
Page 69 Rx IPv4 Datagrams Fragmented Frames Register ................31–292 Rx IPv4 Datagrams Fragmented Octets Register ................. 31–293 Rx IPv4 Datagrams (Good) Register ....................31–294 Rx IPv4 Datagrams Good Octets Register ................... 31–295 Rx IPv4 Datagrams Header Errors Register ..................31–296 Rx IPv4 Datagrams Header Errors Register ..................31–297 Rx IPv4 Datagrams No Payload Frame Register ..................
Page 70 Rx Unicast Frames (Good) Register ..................... 31–322 Rx UDP Error Frames Register ......................31–323 Rx UDP Error Octets Register ......................31–324 Rx UDP Good Frames Register ......................31–325 Rx UDP Good Octets Register ......................31–326 Rx Undersize (Good) Register ......................31–327 Rx VLAN Frames (Good/Bad) Register ....................
Page 71 PPS 3 Target Time Nanoseconds Register ................... 31–358 PPS 3 Target Time Seconds Register ....................31–359 PPS 3 Width Register .......................... 31–360 PPS Control Register ........................... 31–361 Time Stamp Low Seconds Register ...................... 31–364 Time Stamp Seconds Update Register ....................31–365 Time Stamp Status Register .........................
Page 72 Tx Single Collision (Good) Register ....................31–392 Tx Unicast Frames (Good/Bad) Register ....................31–393 Tx Underflow Error Register ....................... 31–394 Tx VLAN Frames (Good) Register ...................... 31–395 VLAN Tag Register ..........................31–396 VLAN Hash Table Register ......................... 31–398 VLAN Tag Inclusion or Replacement Register ..................31–399 Watchdog Timeout Register ........................
Page 73 Trigger Masking ..........................32–14 Interrupt Masking ..........................32–14 Modulator Clock ..........................32–14 Filter Configuration ..........................32–14 Primary Filter Parameters........................32–15 Primary DMA Configuration and Data Interrupts................32–15 Secondary Filter Parameters ........................ 32–16 Overload Detection ..........................32–16 ADSP-SC58x SINC Register Descriptions ....................32–17 Bias for Group 0 Register ........................
Page 74 Rate Control for Group 0 Register ......................32–48 Rate Control for Group 1 Register ......................32–50 Status Register ............................32–52 Digital Audio Interface (DAI) SRU Features ............................... 33–1 Functional Description ..........................33–2 ADSP-SC58x DAI Register List ....................... 33–2 ADSP-SC58x DAI Interrupt List ......................33–4 DAI Block Diagram..........................
Page 75 Unused DAI Connections.......................... 33–18 DAI Operating Modes ..........................33–18 DAI Pin Buffer Polarity.......................... 33–18 DAI Miscellaneous Buffer Polarity ......................33–18 DAI System Interrupt Controller (SIC) ..................... 33–19 Signal Routing Unit Effect Latency......................33–21 DAI Programming Model.......................... 33–21 Debug Features ............................33–21 DAI Sources Overview..........................
Page 76 Serial Data Routing Control Register 1 ....................33–61 Serial Data Routing Control Register 2 ....................33–62 Serial Data Routing Control Register 3 ....................33–63 Serial Data Routing Control Register 4 ....................33–64 Serial Data Routing Control Register 5 ....................33–65 Serial Data Routing Control Register 6 ....................
Page 77 Serial Port (SPORT) Features................................ 34–1 Signal Descriptions ............................34–2 SRU Programming ............................34–6 Functional Description ..........................34–6 ADSP-SC58x SPORT Register List......................34–6 ADSP-SC58x SPORT Interrupt List ....................... 34–7 ADSP-SC58x SPORT Trigger List ......................34–9 ADSP-SC58x SPORT DMA Channel List..................... 34–10 Block Diagram............................
Page 78 Left-Justified Mode .......................... 34–30 Right-Justified Mode........................34–31 Multichannel (TDM) Mode ........................ 34–33 Packed I S Mode..........................34–36 Gated Clock Mode ..........................34–37 Data Transfers and Interrupts ........................34–38 Data Buffers ............................34–38 Data Buffer Status ..........................34–40 Single-Word (Core) Transfers ......................... 34–40 DMA Transfers............................
Page 79 Half SPORT 'A' Divisor Register ......................34–77 Half SPORT 'B' Divisor Register ......................34–78 Half SPORT 'A' Error Register ......................34–79 Half SPORT 'B' Error Register ......................34–81 Half SPORT 'A' Multichannel Control Register ................... 34–83 Half SPORT 'B' Multichannel Control Register ................... 34–85 Half SPORT 'A' Multichannel Status Register ..................
Page 80 Cross Mode Connections ........................35–6 Operating Modes ............................35–6 Normal Mode ............................35–6 Bypass Mode ............................35–7 One-Shot Mode............................35–7 PCG Event Control ..........................35–8 External Event Trigger........................... 35–8 External Event Trigger Delay......................35–8 Audio System Example ..........................35–9 Clock Configuration Examples ....................... 35–10 Programming Model..........................
Page 81 Functional Description ..........................36–2 ADSP-SC58x ASRC Register List ......................36–2 ASRC Interrupt List ..........................36–2 ASRC Block Diagram ..........................36–2 SRU Programming ........................... 36–3 Clocking ..............................36–3 I/O Ports ..............................36–3 De-Emphasis Filter ........................... 36–4 Mute Control ............................36–4 SRC Core ..............................36–4 RAM FIFO ............................
Page 82 Masking..............................36–10 Service ..............................36–10 Programming Model..........................36–10 Debug Features ............................36–10 ADSP-SC58x ASRC Register Descriptions ....................36–10 Control Register for ASRC 0 and 1 ....................... 36–12 Control Register for ASRC 2 and 3 ....................... 36–17 Mute Register ............................36–22 Ratio Register for ASRC 0 and 1 ......................
Page 83 Emphasized Audio Data........................37–10 Single-Channel Double-Frequency Mode..................37–10 Clock Recovery Modes ........................37–10 Interrupts..............................37–11 Sources ..............................37–11 Transmit Block Start ........................... 37–11 Receiver Status ............................ 37–11 Receiver Error............................37–11 Masking..............................37–11 Service ..............................37–12 Programming Model..........................37–12 Programming the Transmitter ........................ 37–12 Programming the Receiver........................
Page 84 Transmit Status B0 Register ........................37–33 Transmit Status B1 Register ........................37–34 Transmit Status B2 Register ........................37–35 Transmit Status B3 Register ........................37–36 Transmit Status B4 Register ........................37–37 Transmit Status B5 Register ........................37–38 Transmit User Buffer A0 Register ......................37–39 Transmit User Buffer A1 Register ......................
Page 85 Data Address Alignment ........................38–10 Descriptor Set Address Alignment ....................38–10 DMA Channel Peripheral DMA Bus....................38–11 Peripheral Control Commands ......................38–11 Peripheral-Control Command Restrictions ..................38–13 Memory DMA and Triggering ......................38–14 Medium Band Width DMA Channel MMR Access Bus ..............38–16 DMA Channel Operation Flow......................
Page 86 Event Signals ............................38–31 Work Unit State Events ......................... 38–32 Peripheral Interrupt Request Events ...................... 38–32 Peripheral Data Request Events ......................38–33 DMA Channel Triggers ......................... 38–33 Issuing Triggers ............................. 38–33 Waiting For Triggers ..........................38–34 DMA Channel Programming Model ......................38–35 Mode Configuration..........................
Page 87 Previous Initial Descriptor Pointer Register ................... 38–61 Status Register ............................38–62 Inner Loop Count Start Value Register ....................38–65 Current Count (1D) or Intra-row XCNT (2D) Register ................ 38–66 Inner Loop Address Increment Register ....................38–67 Outer Loop Count Start Value (2D only) Register ................. 38–68 Current Row Count (2D only) Register ....................
Page 88 Delay Line DMA............................ 39–13 ADSP-SC58x EMDMA Register Descriptions ..................39–15 External Base Address Register ......................39–17 Circular Buffer Length Register ......................39–18 Chain Pointer Register .......................... 39–19 Internal Count Register ......................... 39–20 External Count Register ........................39–21 External Memory DMA Control Register ....................39–22 Internal Index Register ..........................
Page 89 Look-up Table ............................40–6 Data Mirroring............................40–6 FIFO Status and Data Requests........................ 40–7 CRC Operating Modes ..........................40–8 Data Transfer Modes ..........................40–8 Memory Scan Compute-and-Compare Mode..................40–9 Memory Scan Data Verify ........................40–10 Memory Transfer Compute-and-Compare Mode ................40–10 Memory Transfer Data Fill Mode......................
Page 90 Interrupt Enable Set Register ......................... 40–35 Polynomial Register ..........................40–36 CRC Current Result Register ........................ 40–37 CRC Final Result Register ........................40–38 Status Register ............................40–39 Housekeeping ADC (HADC) HADC Features ............................41–1 HADC Functional Description........................41–1 ADSP-SC58x HADC Register List......................41–2 ADSP-SC58x HADC Interrupt List ......................
Page 91 System Security Security Features ............................42–1 Security Functional Description........................42–2 Security Mode Configuration ........................42–4 Status and Error Signals ..........................42–4 System Protection Unit (SPU) SPU Features ............................... 43–1 SPU Functional Description ........................43–1 ADSP-SC58x SPU Register List....................... 43–1 ADSP-SC58x SPU Interrupt List ......................43–2 Peripheral Register Write Protection......................
Page 92 Security Packet Engine (PKTE) PKTE Features............................. 44–1 PKTE Functional Description ........................44–1 ADSP-SC58x PKTE Register List ......................44–1 ADSP-SC58x PKTE Interrupt List ......................44–3 PKTE Definitions ............................ 44–4 Cipher Module ............................44–5 Hash Module............................44–5 Pseudo-Random Number Generator ......................44–6 Packet Engine Processing Details......................
Page 93 Autonomous Ring Mode (ARM) ......................44–26 Target Command Mode (TCM) ......................44–27 Direct Host Mode (DHM) ........................44–27 PKTE Event Control ..........................44–28 PKTE Interrupt Signals.......................... 44–28 PKTE Programming Model........................44–30 PKTE Mode Configuration........................44–33 PKTE Programming Concepts ....................... 44–33 Packet Engine Descriptor ........................
Page 94 Packet Engine Configuration Register ....................44–58 PE Clock Control Register ........................44–61 PKTE Continue Register ........................44–63 Packet Engine Control Register ......................44–64 Starting Entry of 256-byte Data Input/Output Buffer ................44–69 Packet Engine Destination Address ......................44–70 Packet Engine DMA Configuration Register ..................44–71 Packet Engine Endian Configuration Register ..................
Page 95 ARC4 i and j Pointer Register ......................44–108 SA Command 0 ........................... 44–109 SA Command 1 ........................... 44–114 SA Inner Hash Digest Registers ......................44–118 SA Key Registers ..........................44–119 SA Initialization Vector Register ......................44–120 SA Outer Hash Digest Registers ......................44–121 SA Ready Indicator ..........................
Page 96 Modular Inversion with a Prime Modulus................... 45–14 ECC Operations............................. 45–14 ADSP-SC58x PKA Register Descriptions ....................45–20 PKA Vector_A Length ........................... 45–21 PKA Vector_A Address .......................... 45–22 PKA Vector_B Length ........................... 45–23 PKA Vector_B Address .......................... 45–24 PKA Compare Result ..........................45–25 PKA Vector_C Address ..........................
Page 97 Type Control Register ..........................46–11 True Random Number Generator (TRNG) TRNG Features ............................47–1 TRNG Functional Description ........................47–1 ADSP-SC58x TRNG Register List......................47–1 Random Number Generation ........................47–2 Locking Detection and Prevention......................47–3 Run Testing .............................. 47–3 Monobit Testing............................47–4 Poker Testing............................
Page 98 TRNG LFSR Access Register ......................... 47–26 TRNG LFSR Access Register ......................... 47–27 TRNG Monobit Test Result Register ....................47–28 TRNG Output Registers ........................47–29 TRNG Poker Test Result Registers ......................47–30 TRNG Run Count Registers ......................... 47–31 TRNG Run Test State and Result Registers ................... 47–32 TRNG Status Register ...........................
Page 99 Interrupt Mask Register ......................... 48–13 Offset Register ............................48–14 Status Register ............................48–15 Temperature Value Register ........................48–16 Harmonic Analysis Engine (HAE) HAE Features............................... 49–1 HAE Functional Description ........................49–2 ADSP-SC58x HAE Register List ......................49–2 ADSP-SC58x HAE Interrupt List ......................49–3 ADSP-SC58x HAE Trigger List........................
Page 100 ADSP-SC58x HAE Register Descriptions ....................49–17 Configuration 0 Register ........................49–18 Configuration 1 Register ........................49–19 Configuration 2 Register ........................49–20 Configuration 3 Register ........................49–22 Configuration 4 Register ........................49–23 DIDT Coefficient Register ........................49–24 DIDT Gain Register ..........................49–25 Harmonic n Index Register ........................
Page 101 Fast Convolution ............................50–8 ADSP-SC58x FFTA Register Descriptions ....................50–9 Control Register ............................ 50–10 Instruction Memory Register ......................... 50–11 Loop Counter Value Register ......................... 50–12 Program Counter Register ........................50–13 FFT/IFFT Scale Factor Register ......................50–14 Status Register ............................50–15 Thread Count Offset Register .......................
Page 102 Single Rate Processing ..........................51–8 Single Iteration............................51–8 Floating-point Multi-Iteration....................... 51–8 Window Processing ..........................51–8 Multi-Rate Processing ..........................51–9 Decimation............................... 51–9 Interpolation ............................51–9 Channel Processing ..........................51–10 Floating-Point Data Format........................51–11 Fixed-Point Data Format ........................51–11 Data Transfer............................. 51–12 Chain Assignment ..........................
Page 103 Sources ..............................51–19 Window Complete ..........................51–19 All Channels Complete ........................51–20 MAC Status ............................51–20 Service ..............................51–20 Effect Latency ............................51–21 Write Effect Latency ..........................51–21 FIR Throughput ............................51–21 ADSP-SC58x FIR Register Descriptions ....................51–21 FIR Chain Pointer Register ........................51–23 FIR Coefficient Count Register ......................
Page 104 Features................................ 52–1 Clocking ..............................52–1 Functional Description ..........................52–1 ADSP-SC58x IIR Register List......................... 52–3 ADSP-SC58x IIR Interrupt List ......................52–4 ADSP-SC58x IIR Trigger List ........................52–4 Multiply and Accumulate (MAC) Unit ..................... 52–4 Input Data and Biquad State ........................52–5 Coefficient Memory ..........................
Page 105 Dynamic Coefficient Processing Notes ....................52–12 Writing to Local Memory ........................52–13 Reading from Local Memory ........................52–13 Single Step Mode............................ 52–13 Save Biquad State of the IIR ........................52–13 Programming Example ........................... 52–14 ADSP-SC58x IIR Register Descriptions ....................52–15 Chain Pointer Register ..........................
Page 106 Boot ROM and Booting the Processor SRAM Requirements ........................... 53–1 Preboot Operations............................53–3 Start-up Sequence............................. 53–3 Core Reset Sequencing .......................... 53–3 Core 0 Start-up ............................. 53–5 Core 1 Start-up ............................. 53–6 Core 2 Start-up ............................. 53–7 Idle On Entry ............................53–8 Fault Configuration ..........................
Page 107 Link Port Slave Boot Mode........................53–31 UART Slave Boot Mode ........................53–32 Boot Loader Stream ........................... 53–35 Block Types ............................53–39 Single-Block Boot Streams ........................53–46 Direct Code Execution .......................... 53–47 Multi-Application Boot Streams ......................53–48 CRC32 Protection ..........................53–49 Secure Boot..............................
Page 108 adi_rom_GetAddress() ........................53–69 adi_rom_MemCompare()........................53–70 adi_rom_MemCopy().......................... 53–71 adi_rom_MemCrc() ..........................53–72 adi_rom_MemDma() .......................... 53–72 adi_rom_MemFill() ..........................53–75 adi_rom_PeriphDma() ........................53–76 adi_rom_otp_cfg() ..........................53–77 adi_rom_otp_get() ..........................53–77 adi_rom_otp_lock()..........................53–78 adi_rom_otp_pgm() ..........................53–78 callback() ............................. 53–79 initcode()............................. 53–81 Data Structures ............................53–81 struct ADI_ROM_BOOT_BUFFER ....................53–81 struct ADI_ROM_BOOT_CONFIG ....................
Page 109 struct ROM_BOOT_MDMA_REGS ....................53–112 struct ROM_DMA_MDMA_CONFIG.................... 53–113 struct ROM_DMA_PDMA_CONFIG ..................... 53–114 struct otp_data ..........................53–115 Enumerations ............................53–118 enum ADI_ROM_BOOT_KEY_TYPE .................... 53–118 enum ADI_ROM_BOOT_TYPE ..................... 53–118 enum OTPCMD..........................53–119 enum ROM_BOOT_MDMA_CRC_SUPPORT ................53–121 enum ROM_BOOT_RESULT......................53–121 enum ROM_CORE_ID........................53–128 enum ROM_DMA_DONE_DETECT_METHOD................. 53–129 enum ROM_DMA_MDMA_ID.......................
Page 110 SCB Programming Model.......................... 54–13 SCB Programming Concepts........................54–15 ADSP-SC58x SCB0 Register Descriptions ....................54–20 Read Quality of Service for Master n ..................... 54–21 Write Quality of Service for Master n ....................54–22 ADSP-SC58x SCB1 Register Descriptions ....................54–22 Mst00 Interface Block Sync Mode ......................54–23 ADSP-SC58x SCB3 Register Descriptions ....................
Page 111 Triggers ..............................55–7 SWU Programming Model .......................... 55–7 SWU Mode Configuration ........................55–8 Configuring the SWU for Bandwidth Mode ..................55–8 Configuring the SWU for Watchpoint Mode ..................55–9 ADSP-SC58x SWU Register Descriptions ....................55–10 Count Register n ........................... 55–11 Control Register n ..........................
Page 112 Debug Access Ports........................... 56–8 Trace Unit ..............................56–9 Programmable Flow Trace (CSPFT)...................... 56–9 System Trace Module (STM) ......................56–10 Embedded Cross Trigger (ECT) ......................56–10 CTI Debug Trigger Tables........................56–12 ADSP-SC58x CSPFT Register Descriptions ..................... 56–14 Address Comparator Access Type Register ..................... 56–16 Address Comparator Value Register .......................
Page 113 Peripheral ID1 Register ......................... 56–47 Peripheral ID2 Register ......................... 56–48 Peripheral ID3 Register ......................... 56–49 Peripheral ID4 Register ......................... 56–50 Status Register ............................56–51 Synchronization Frequency Register ...................... 56–52 TraceEnable Control Register ........................ 56–53 TraceEnable Event Register ........................56–54 CoreSight Trace ID Register ........................56–57 Trigger Event Register ...........................
Page 114 For timing, electrical, and package specifications, see the processor data sheet. Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices processors. The manual assumes the audience has a working knowledge of the appropriate processor architecture and instruction set. Pro- grammers who are unfamiliar with Analog Devices processors can use this manual, but should supplement it with other texts, such as programming reference books and data sheets, that describe their target architecture.
Page 115 Also note, MyAnalog.com is a free feature of the Analog Devices Web site that allows customization of a Web page to display only the latest information about products you are interested in. You can choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests, including documentation errata against all manuals.
Page 116 EngineerZone EngineerZone is a technical support forum from Analog Devices. It allows you direct access to ADI technical sup- port engineers. You can search FAQs and technical information to get quick answers to your embedded processing and DSP design questions.
Page 117 Mixed-Signal Control Processors ® The ADSP-CM40x processors are based on the ARM Cortex -M4 core and are designed for motor control and industrial applications. The ADSP-CM41x processors are based on the ARM Cortex-M4 and ARM Cortex-M0 cores and are de- signed for motor control and industrial applications.
Page 118 • Real-Time Counter (RTC) • Serial Interfaces • Serial Ports (SPORTs) • Serial Peripheral Interface (SPI, SPIHP) • Universal Asynchronous Receiver/Transmitter (UART) • Two-Wire Interface (TWI) • Control Area Network (CAN) • Universal Serial Bus (USB) • Parallel Interfaces • Enhanced Parallel Peripheral Interface (EPPI) •...
Page 119 • System Trace Module (STM) The following list provides information on the organization and contents of each chapter of this manual. Note that not every chapter follows this organization exactly nor does every chapter contain all of the topics listed. •...
Page 120 Example Description Non-keyword placeholders appear in text with italic style format. filename NOTE: NOTE: For correct operation, ... A note provides supplementary information on a related topic. In the online ver- sion of this book, the word NOTE: appears instead of this symbol. CAUTION: CAUTION: Incorrect device operation may result if ...
Page 121 • Many bit and bit field descriptions include enumerations, identifying bit values and related functionality. Un- less otherwise indicated (with a prefix), these enumerations are decimal values. ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference cxxi...
Page 122: Introduction
Introduction 1 Introduction The ADSP-SC58x and ADSP-215xx processors are members of the SHARC+ family of products. The ADSP- SC58x processor is based on the SHARC+ dual-core processor and the ARM Cortex-A5 processor cores. As shown in the ADSP-SC58x Functional Block Diagram, by integrating a rich set of industry-leading system pe- ripherals and memory (see product data sheet), the ARM/SHARC+ processor is the platform of choice for next- generation applications that require RISC-like programmability, multimedia support, and leading-edge signal proc- essing in one integrated package.
Page 123: Power And Clock Management (Dpm/Rcu/Cgu/Cdu)
The ADSP-SC58x/ADSP-215xx SHARC+ processors are members of the SIMD SHARC+ family of DSPs that fea- ture Analog Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit floating-point processors are optimized for high performance audio/floating-point applications with their large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and innovative digital audio interfaces (DAI).
Page 124: System Interrupts And Triggers (Sec/Tru)
System Interrupts and Triggers (SEC/TRU) Set RCU_STAT_SWRST = 1 Software System Reset Set RCU_CRCTL_CR[n] = 1 Software Core Reset Fault Reset from SEC (Set RCU_CTL.SRSTREQEN) Watchdog System Reset Hardware Reset from /SYS_HWRST Pin External Hardware Reset System Reset Trigger (RCU0_SYSRST0/1) from TRU Programmable Triggered Hardware Reset System Reset from SEC Programmable Triggered Hardware Reset...
Page 125: System Memory (L2Ctl/Dmc/Smc/Otpc/Smpu)
System Memory (L2CTL/DMC/SMC/OTPC/SMPU) System Event Controller (SEC) There are two interrupt controllers— the System Event Controller (SEC) and Generic Interrupt Controller (GIC). The generic interrupt controller is used for the ARM core, and the system event controller is used for the SHARC+ cores.
Page 126 System Memory (L2CTL/DMC/SMC/OTPC/SMPU) L2 Memory Controller (L2CTL) L2 System Memory has significant bandwidth for core accesses, but it is important to note that L2 responds slower to core accesses than L1 memories. L2 SRAM is the ideal storage for multiple processor cores to share data and instruction resources, such as semaphores, shared buffers, and code libraries.
Page 127 System Memory (L2CTL/DMC/SMC/OTPC/SMPU) System Memory Protection from SMPU0 SMC Address Pins (SMC0_A25:01, on PORT Pins) System MMR Write-Protection (WP48) from SPU SMC Data Pins (SMCx_D15:00, on PORT Pins) ∙ Core/Cache Access Arbitration in SCB0 Only Enable Secure Peripheral (SECUREP48) from SPU ∙...
Page 128: Direct Memory Access (Dma/Mdma/Emdma/Crc)
Direct Memory Access (DMA/MDMA/EMDMA/CRC) Direct Memory Access (DMA/MDMA/EMDMA/CRC) DMA Controller (DMA) The processors use Direct Memory Access (DMA) to transfer data within memory spaces or between a memory space and a peripheral. The processors can specify data transfer operations and return to normal processing while the fully integrated DMA controller carries out the data transfers independent of processor activity.
Page 129 Direct Memory Access (DMA/MDMA/EMDMA/CRC) DMA/MDMA Automated Descriptor Fetches from Memory Triggers to/from TRU Slaves/Masters DMA Data Complete Interrupts to SEC/GIC Manual Core Writes to SMMRs DMA Channel Errors to SEC/GIC Automated FIFO Reads from Peripherals Automated Buffer Writes via SCBs to Memory Enable Secure Peripheral (SECUREPx) from SPU* MDMA CRC System MMR Write-Protection (WPx) from SPU*...
Page 130: Peripherals
Peripherals CRC Polynomial (CRC_POLY) CRC Datacount Expiration Interrupts to SEC/GIC Expected Checksum (CRC_COMP) CRC Error Interrupts to SEC/GIC Automated Reads from Memory Automated Writes to Memory System MMR Write-Protection (WP10-11) from SPU Enable Secure Peripheral (SECUREP10-11) from SPU Clocked by SCLK0_0 Figure 1-15: CRC System Diagram Peripherals The SHARC+ processor contains a rich set of industry leading system peripherals.
Page 131 Peripherals Link Ports (LP) Link Port (LP) allow the processor to connect to other processors or peripheral link ports using a simple com- munication protocol for high-speed parallel data transfer. This peripheral allows various I/O peripheral interconnec- tion schemes to I/O peripheral devices, as well as co-processing and multiprocessing schemes. PB_14:07 Pins LP1_D7:0 LP DMA Data Interrupts to SEC/GIC...
Page 132 Peripherals UART PB_03:02 Pins UART TX/RX DMA Data Interrupts to SEC/GIC PC_15:13 Pins UARTx_TX UART TX/RX DMA Error Interrupts to SEC/GIC PD_00 Pin UARTx_RX UART Status Interrupts to SEC/GIC PD_13:12 Pins UARTx_RTS PE_02:01 Pins UART_TX/RXDMA Triggers to/from TRU Slaves/Masters UARTx_CTS PE_11:10 Pins System MMR Write-Protection (WP87:82, 33:31) from SPU Enable Secure Peripheral (SECUREP87:82, 33:31) from SPU...
Page 133 Peripherals inputs. Since integration provides relative position, some devices also feature a zero-position input (zero marker). The GP counter can use the zero position input feature to establish a reference point for verifying that the acquired position does not drift over time. In addition, the GP counter can use the incremental position information to de- termine speed, if the time intervals are measured.
Page 134 Peripherals Mobile Storage Interface (MSI) Mobile Storage Interface (MSI) is a fast, synchronous controller that uses various protocols to communicate with MMC, SD, and SDIO cards. It addresses the growing storage need in embedded systems, hand held, and con- sumer electronics applications that require low power. MSI0_Dx PF_09:02 Pins MSI Status Interrupt to SEC/GIC...
Page 135: Dai/Sru Peripherals
Peripherals EMAC ETHx_TXDy EMAC Status Interrupts (EMACx_STAT) to SEC/GIC ETHx_MDC EMAC Status Triggers (EMACx_STAT) to TRU Slaves ETHx_MDIO ETHx_RXDy PA_15:00 Pins ETHx_RXCLK_REFCLK PB_06:00 Pins ETHx_RXCTL_CRS PF_15:13 Pins System MMR Write-Protection (WP56:55) from SPU ETHx_TXCTL_TXEN PG_05:00 Pins Enable Secure Peripheral (SECUREP56:55) from SPU ETHx_TXCLK ETHx_PTPPPSy ETHx_PTPCLKIN0...
Page 136: Dedicated Pin Peripherals
Peripherals SPORT SPT_ACLK SPORT DMA Channel A/B Data Interrupts to SEC/GIC SPT_ADx SPORT Channel A/B Status Interrupts to SEC/GIC SPT_AFS SPORT DMA Channel A/B Error Interrupts to SEC/GIC DAI0_PIN20:1 Pins SPT_ATDV SPORT DMA Channel A/B Triggers DAI1_PIN20:1 Pins to/from TRU Slaves/Masters SPT_BCLK SPT_BDx SPT_BFS...
Page 137 Peripherals Differential Data Pins (USB_DM/DP) USB DMA Complete Interrupts to SEC/GIC OTG Host/Device Pin (USB_ID) USB Status Interrupts to SEC/GIC USB Status Triggers to TRU Slaves VBUS Control Pin (USB_VBC) USB_CLKIN Pin System MMR Write-Protection (WP154:153) from SPU Clocked by SYSCLK_0 Enable Secure Peripheral (SECUREP154:153) from SPU Figure 1-31: USB System Diagram Media Local Bus (6-pin) (MLB)
Page 138: System Accelerators (Fft/Fir/Iir/Hae/Sinc)
System Accelerators (FFT/FIR/IIR/HAE/SINC) HADC External Multiplexor Control Pins HADC Event Interrupt to SEC/GIC (HADC0_MUX2:0) HADC Conversion Done Trigger to TRU Slaves Analog Input Channel Pins (HADC0_VIN7:0) End of Conversion/Serial Data Pin (HADC0_EOC_DOUT) System MMR Write-Protection (WP63) from SPU Enable Secure Peripheral (SECUREP63) from SPU Clocked by SCLK0_0 Figure 1-34: HADC System Diagram System Accelerators (FFT/FIR/IIR/HAE/SINC)
Page 139 System Accelerators (FFT/FIR/IIR/HAE/SINC) IIR Accelerator (IIR) The processor includes an IIR Accelerator (IIR) implemented in hardware that reduces the processing load on the core, freeing it up for other tasks. System MMR Write-Protection IIR DMA Interrupt (IIR0_DMA) to SEC/GIC (WP156) from SPU IIR Status Interrupt (IIR0_STAT) to SEC/GIC Enable Secure Peripheral (SECUREP156) from SPU...
Page 140: Security And Protection (Spu/Pkte/Pkic/Pka/Trng)
Security and Protection (SPU/PKTE/PKIC/PKA/TRNG) SINC SINC0_CLK0 PB_01 Pin SINC Status Interrupt (SINC0_STAT) to SEC/GIC SINC0_D0 PA_14 Pin SINC Pair Overload Triggers (SINC0_Px_OVLD) to TRU Slaves SINC0_D1 PA_15 Pin SINC Data Move Triggers (SINC0_DATAx) to TRU Slaves SINC0_D2 PB_00 Pin SINC0_D3 PB_04 Pin System MMR Write-Protection (WP60) from SPU Enable Secure Peripheral (SECUREP60) from SPU...
Page 141: Safety (Wdog/Tmu/Vmu)
Safety (WDOG/TMU/VMU) Safety (WDOG/TMU/VMU) Signal Watchdogs (WDOG) The eight general-purpose Watchdog Timer (WDOG) timers feature modes to monitor off-chip signals. The Watchdog Period mode monitors whether external signals toggle with a period within an expected range. The Watchdog Width mode monitors whether the pulse widths of external signals are within an expected range. Both modes help to detect undesired toggling (or lack thereof ) of system-level signals.
Page 142 System Debug (SCB/SWU/DBG/TAPC/CSPFT/STM) (traffic) as required. A hierarchical model, built from multiple SCBs, provides a power and area efficient system interconnect, which satisfies the performance and flexibility requirements of a specific system. • The System Watchpoint Unit (SWU) is a single module used for transaction monitoring. The SWU is attached to each system slave through the system crossbar interface and provides ports for all address channel signals for the system crossbar.
Page 143: Arm Cortex-A5 Sub-System
ARM Cortex-A5 Sub-System 2 ARM Cortex-A5 Sub-System ® ® The ADSP-SC589 processor includes an ARM Cortex-A5 core. The ARM Cortex-A5 processor is the smallest, lowest cost and lowest power ARMv7 application processor. The A5 sub-system in the ADSP-SC589 processor in- cludes a Floating-Point Unit, NEON Media Processing Engine, Generic Interrupt Controller and a Level 2 Cache Controller.
Page 144: Functional Description
Functional Description • Generic Interrupt Controller (GIC) • Level 2 Cache Controller (L2CC) • Memory Management Unit (MMU) Functional Description The following sections provide information on the function of the sub-system. A5 Block Diagram The following figure shows the primary blocks of the Cortex A5 sub-system. The performance increases with access- es to lower levels of memory as follows: 1.
Page 145: L1 Cache
Functional Description • Overall system control and configuration • MMU configuration and management • Cache configuration and management • System performance monitoring All system architecture functions are controlled by reading or writing a general purpose processor register (Rt) from or to a set of registers (CRn) located within co-processor 15. The Op1, Op2, and CRm fields of the instruction can also be used to select registers or operations.
Page 146: L2 Cache
Functional Description The MMU enables tasks or applications to be written in a way that requires them to have no knowledge of the physical memory map of the system, or about other programs that might be running simultaneously. This enables you to use the same virtual memory address space for each program.
Page 147: Floating-Point Unit (Fpu)
Functional Description • Direct mapped to 8-way associativity (fixed) • Prefetching capability • Event monitoring • Software option to enable exclusive cache configuration • Additional Buffers: • Line Fill Buffers (LFBs) • Line Read Buffers (LRBs) • Eviction Buffers (EBs) •...
Page 148: Neon
Functional Description • Support for single-precision and double-precision floating-point formats • Support for conversion between half-precision and single-precision • Support for Fused Multiply Accumulate (FMA) operations • Normalized and de-normalized data are all handled in hardware • Trap-less operation enabling fast execution NeON The Cortex-A5 NEON MPE extends the Cortex-A5 functionality to provide support for the ARM v7 Advanced SIMD v2 and Vector Floating-Point v4 (VFPv4) instruction sets.
Page 149: Generic Interrupt Controller (Gic)
Functional Description Generic Interrupt Controller (GIC) The GIC is an ARM Architecture compliant System-on-Chip (SoC) peripheral. It is a high-performance, area-opti- mized interrupt controller. The GIC implements the ARM Generic Interrupt Controller Architecture. The GIC takes interrupts asserted at the system level and signals them to each connected processor as appropriate. The GIC has the following features.
Page 150 Functional Description A5 Configurations Table 2-2: A5 Core Configuration Core Feature Comment JAZELLE Support Implemented NEON Engine Implemented Implemented Instruction cache size 32 KB Data cache size 32 KB A5 Configuration Signals Table 2-3: A5 Configuration Signals Configuration A5 TRM Signal Name Comment Default Exception Handler Endianness CFGEND...
Page 151 Functional Description Table 2-5: L2CC Configuration Signals (Continued) Configuration L2CC TRM Signal Name Comment Cache controller cache ID CACHEID[5:0] Address filtering Enable out of reset CFGADDRFILTEN Enabled Address filtering End Address out of reset CFGADDRFILTEND[11:0] 0xFFF Address filtering Start Address out of reset CFGADDRFILTSTART[11:0] 0x201 Endian mode for accessing configuration registers out of reset...
Page 152: Clock Generation Unit (Cgu)
Clock Generation Unit (CGU) 3 Clock Generation Unit (CGU) The Clock Generation Unit (CGU) includes the phase locked loop (PLL) and the PLL control unit (PCU). The PLL generates a master clock that runs at a frequency that is a multiple of the CLKIN input clock frequency. The PCU divides down the master clock to generate various system clocks and synchronization signals.
Page 153: Adsp-Sc58X Cgu Register List
CGU Functional Description Change other clock frequencies The CGU allows programs to change the CCLKn, SYSCLK, SCLKn, DCLK, and OCLK frequencies by writ- ing values to the CGU_DIV register. Any time the clock frequency is changed, the OCLK, CCLKn, SYSCLK, DCLK and SCLKn clocks exit the frequency change sequence aligned.
Page 154: Adsp-Sc58X Cgu Trigger List
CGU Functional Description Table 3-2: ADSP-SC58x CGU Interrupt List Interrupt Name Description Sensitivity Channel CGU0_EVT CGU0 Event Edge CGU1_EVT CGU1 Event Edge ADSP-SC58x CGU Trigger List Table 3-3: ADSP-SC58x CGU Trigger List Masters Trigger ID Name Description Sensitivity CGU0_EVT CGU0 Event Edge CGU1_EVT CGU1 Event...
Page 155: Cgu Pll Block Diagram
CGU Functional Description The clock generation unit (CGU) is comprised of the PLL and PCU. The CGU generates the clocks listed in the Clock Descriptions table. Table 3-5: Clock Descriptions Clock Description CCLK0_0 CCLK0 derived from CGU0 CCLK1_0 CCLK1 derived from CGU0 SYSCLK_0 SYSCLK derived from CGU0 SCLK0_0...
Page 156 CGU Functional Description BYPASS CCLK0EN CCLK0_x CSEL[4:0] CSEL CCLK1EN CCLK1_x SYSSEL[4:0] SYSCLK_0 SSEL S0SEL[2:0] SYS_CLKINx SCLK0EN Charge Pump/ SCLK0_x /1 or /2 PLLCLK Loop Filter S0SEL S1SEL[2:0] SCLK1EN SCLK1_x MSEL S1SEL DSEL[4:0] MSEL[6:0] DCLKEN DCLK_x DSEL OSEL[6:0] OCLKEN OCLK_x OSEL Figure 3-1: CGU PLL Block Diagram (x=0 CGU0, x=1 CGU1) The SYS_CLKOUT Generation figure is a conceptual representation of the CLKOUT module.
Page 157: Cgu Operating Modes
CGU Operating Modes CGU Operating Modes The CGU does not have configurable operating modes, but CGU operations affect the operating modes of other modules. Some CGU operation issues that affect operation of other modules include the following: • The PLL of the CGU operates in either normal mode (CGU clock divisors applied) or bypass mode (CGU PLL is bypassed and clock divisors ignored).
Page 158: Oscillator Watchdog
CGU Event Control • A write access to the CGU_CTL.DF bit field occurs or a write access to the CGU_CTL.MSEL bit field occurs while the PLL is locking. The CGU_STAT.WDFMSERR bit state indicates this error. If this error occurs, wait until the PLL has finished locking, clear the error, and rewrite the desired value change.
Page 159: Cgu Programming Model
CGU Programming Model The CGU uses the CGU_OSCWDCTL.BOUF asynchronous control bit field to indicate the desired upper fail limit for the bad oscillation detection. Set the CGU_OSCWDCTL.BOUEN bit to enable upper-limit bad oscillation detec- tion. A bad oscillation detection condition signals a fault before any processor operations occur. This detection oc- curs (even in bypass mode) whenever a clock frequency exceeds its specifications.
Page 160: Changing Clock Frequencies
Configuring CGU Modes *pREG_CGU0_PLLCTL |= BITM_CGU_PLLCTL_PLLBPCL; // come out of bypass and enter Full ON while( (pADI_CGU0 ->STAT & 0xF) != 0x5 ) { } // poll // now clocks are running with hardware default divisors. // now program can change frequencies If desired the program can put the PLL again into bypass.
Page 161: Changing The Cclkn Or Sysclk Frequency Without Modifying The Pllclk Frequency
Configuring CGU Modes a. To change the PLL frequency while the cores are idle, write to the CGU_CTL register with the CGU_CTL.WFI bit =1. b. To change the PLL frequency while the cores are active, write to the register with the CGU_CTL CGU_CTL.WFI bit =0.
Page 162: Changing The Oclk Frequency
Configuring CGU Modes Writing to the CGU_DIV register is allowed while the processor is in active (PLL bypassed) mode. But, the effect of the write is visible only after the transition to full-on (PLL not bypassed) mode. Accessing the DDR memory while changing the SYSCLK frequency is not supported and can have unpredictable results.
Page 163: Shutting Off Cclkn From Another Master
Configuring CGU Modes CGU_STAT register exits this sequence with the CGU_STAT.CLKSALGN bit =0. Poll the CGU_STAT.CLKSALGN bit to discover when the clocks are aligned. Any write to the register intended CGU_DIV to align clocks or to change a clock select field while the CGU_STAT.CLKSALGN bit =1 (clocks alignment in pro- gress) triggers an MMR access bus error.
Page 164: Pll Bypass And Pll Disable
Configuring CGU Modes NOTE: The frequency of any processor core clock to the SYSCLK is either 1:1 or 2:1 only. PLL Bypass and PLL Disable Writing 1 to the CGU_PLLCTL.PLLBPST bit tells the PLL to apply OSC_CLKIN clock to CCLK, SYSCLK, SCLK0, SCLK1, DCLK (PLL Bypass), and OCLK outputs.
Page 165 ADSP-SC58x CGU Register Descriptions Table 3-8: ADSP-SC58x CGU Register List (Continued) Name Description CGU_REVID Revision ID Register CGU_SCBF_DIS System Clock Buffer Disable Register CGU_SCBF_STAT System Clock Buffer Status Register CGU_STAT Status Register CGU_TSCOUNT0 Time Stamp Counter 32 LSB Register CGU_TSCOUNT1 Time Stamp Counter 32 MSB Register CGU_TSCTL Time Stamp Control Register...
Page 166: Core Clock Buffer Disable Register
ADSP-SC58x CGU Register Descriptions Core Clock Buffer Disable Register register controls each core's clock buffer to determine if the CCLK is enabled. CGU_CCBF_DIS CCBF1 (R/W) CCBF0 (R/W) Core Clock Buffer 1 Core Clock Buffer 0 LOCK (R/W) Lock Figure 3-3: CGU_CCBF_DIS Register Diagram Table 3-9: CGU_CCBF_DIS Register Fields Bit No.
Page 167: Core Clock Buffer Status Register
ADSP-SC58x CGU Register Descriptions Core Clock Buffer Status Register register shows which core clock buffer(s) are disabled. For example clearing the CGU_CCBF_STAT CGU_CCBF_DIS.CCBF0 bit clears the CGU_CCBF_STAT.CCBF0 bit after a number of cycles. To guarantee that the correct value is read, this register should be read twice and the second result used. CCBF1 (R) CCBF0 (R) Core Clock Buffer 1...
Page 168: Clkout Select Register
ADSP-SC58x CGU Register Descriptions CLKOUT Select Register selects the signal that the CGU drives through the CLKOUT multiplexer. Also, this regis- CGU_CLKOUTSEL ter selects the divisor for the USBCLK output. CLKOUTSEL (R/W) CLKOUT Select LOCK (R/W) USBCLKSEL (R/W) Lock USBCLK Select Figure 3-5: CGU_CLKOUTSEL Register Diagram Table 3-11: CGU_CLKOUTSEL Register Fields Bit No.
Page 169 ADSP-SC58x CGU Register Descriptions Table 3-11: CGU_CLKOUTSEL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 4 CLKO2 5 CLKO3 6 CLKO5 7 CLKO7 8 CLKO8 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved...
Page 170: Control Register
ADSP-SC58x CGU Register Descriptions Control Register controls the clock generation divisors for SYS_CLKIN and the PLL. Read after write accesses to the CGU_CTL CGU_CTL register returns the new value even if the clock's frequency change is still in progress. MSEL (R/W) DF (R/W) Multiplier Select Divide Frequency...
Page 171 ADSP-SC58x CGU Register Descriptions Table 3-12: CGU_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 14:8 MSEL Multiplier Select. (R/W) The CGU_CTL.MSEL bit field selects the multiplier in the PLLCLK equation: PLLCLK frequency = (SYS_CLKIN frequency / (DF+1)) * MSEL Where the value of MSEL is between 1 and 127.
Page 172: Clocks Divisor Register
ADSP-SC58x CGU Register Descriptions Clocks Divisor Register register controls clock divisors for core clocks, system clocks, external (off core) memory clocks, and CGU_DIV output clock. Read after write accesses to the CGU_DIV register returns the new value even if the clock's frequency change is still in progress.
Page 173 ADSP-SC58x CGU Register Descriptions Table 3-13: CGU_DIV Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ALGN Align. (R0/W) The CGU_DIV.ALGN directs the CGU to align the PLL-based clocks. The divisor se- lections (CGU_DIV.CSEL, CGU_DIV.SYSSEL, CGU_DIV.S0SEL, CGU_DIV.S1SEL, CGU_DIV.DSEL, and/or CGU_DIV.OSEL) do not have to change.
Page 174 ADSP-SC58x CGU Register Descriptions Table 3-13: CGU_DIV Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) S0SEL SCLK 0 Divisor. (R/W) The CGU_DIV.S0SEL selects the divisor in the SCLK0 equation: SCLK0 frequency = (SYSCLK frequency) / CGU_DIV.S0SEL Where the value of CGU_DIV.S0SEL is between 1 and 7. 0 S0SEL = 8 1-7 S0SEL = 1 to 7 CSEL...
Page 175 ADSP-SC58x CGU Register Descriptions Oscillator Watchdog Register register configures the CGU to allow the detection of the absence of input clock transitions CGU_OSCWDCTL and provides a fault warning via the SYS_FAULT pin. The CGU_OSCWDCTL register also detects and reports input oscillator frequencies above and below specified limits, in order to specifically detect harmonic or sub-harmonic crystal oscillator behavior.
Page 176 ADSP-SC58x CGU Register Descriptions Table 3-14: CGU_OSCWDCTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 12:8 BOUF Bad Oscillator Upper Frequency limit. (R/W) The CGU_OSCWDCTL.BOUF bits indicate the desired upper fail limit for the bad os- cillation detection. 0 Enable buffer 1 Disable buffer CNGEN Clock not Good enabled.
Page 177 ADSP-SC58x CGU Register Descriptions PLL Control Register register contains bits that enable and disable the PLL as well as control its function. CGU_PLLCTL PLLEN (R/W) PLLBPST (R/W) PLL Enable PLL Bypass Set PLLDIS (R/W) PLLBPCL (R/W) PLL Disable PLL Bypass Clear LOCK (R/W) Lock Figure 3-9: CGU_PLLCTL Register Diagram...
Page 178 ADSP-SC58x CGU Register Descriptions Table 3-15: CGU_PLLCTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PLLBPST PLL Bypass Set. (R/W) Setting (=1) the CGU_PLLCTL.PLLBPST bit bypasses the PLL and all the clocks run on CLKIN. 0 Use PLL 1 Bypass PLL ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference 3–27...
Page 179 ADSP-SC58x CGU Register Descriptions Revision ID Register register reports the version of the CGU. CGU_REVID MAJOR (R) REV (R) Major Version Incremental Version ID Figure 3-10: CGU_REVID Register Diagram Table 3-16: CGU_REVID Register Fields Bit No. Bit Name Description/Enumeration (Access) MAJOR Major Version.
Page 180 ADSP-SC58x CGU Register Descriptions System Clock Buffer Disable Register register controls each system's clock buffer to determine if the SCLKn buffer is enabled. CGU_SCBF_DIS OUTCLKBF (R/W) SCLK0BF (R/W) OCLK Buffer SCLK0 Buffer DCLKBF (R/W) SCLK1BF (R/W) DCLK Buffer SCLK1 Buffer LOCK (R/W) Lock Figure 3-11: CGU_SCBF_DIS Register Diagram...
Page 181 ADSP-SC58x CGU Register Descriptions Table 3-17: CGU_SCBF_DIS Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) SCLK1BF SCLK1 Buffer. (R/W) The CGU_SCBF_DIS.SCLK1BF bit enables (=0, default) or disables (=1) SCLK1s buffer. 0 Enable buffer 1 Disable buffer SCLK0BF SCLK0 Buffer. (R/W) The CGU_SCBF_DIS.SCLK0BF bit enables (=0, default) or disables (=1) SCLK0s buffer.
Page 182 ADSP-SC58x CGU Register Descriptions System Clock Buffer Status Register register shows which system clock buffer(s) are disabled. For example clearing the CGU_SCBF_STAT CGU_CCBF_DIS.CCBF0 bit clears the CGU_SCBF_STAT.SCLK0BF bit after a number of cycles. To guaran- tee that the correct value is read, this register should be read twice and the second result used. OCLKBF (R) SCLK0BF (R) OCLK Buffer...
Page 183 ADSP-SC58x CGU Register Descriptions Table 3-18: CGU_SCBF_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) SCLK0BF SCLK0 Buffer. (R/NW) The CGU_SCBF_STAT.SCLK0BF bit reports the status of the CGU_SCBF_DIS.SCLK0BF bit where 0 = enabled and 1 = disabled. 0 Enabled 1 Disabled 3–32 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference...
Page 184 ADSP-SC58x CGU Register Descriptions Status Register register reflects the PLL status and errors detected during the PLL configuration. This register may CGU_STAT be cleared asynchronously by a reset signal from the RCU module. All bits---except those defined as W1C (write-1- to-clear)---are read only.
Page 185 ADSP-SC58x CGU Register Descriptions Table 3-19: CGU_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) WDIVERR Write to DIV Error. (R/W1C) The CGU_STAT.WDIVERR bit indicates a write access to the CGU_DIV register (to trigger an alignment sequence or to change the CGU_DIV.CSEL, CGU_DIV.SYSSEL, CGU_DIV.S0SEL, CGU_DIV.S1SEL, or CGU_DIV.DSEL bit values) while the PLL is locked, but still aligning the clocks.
Page 186 ADSP-SC58x CGU Register Descriptions Table 3-19: CGU_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 2 Subharmonic CLKIN 3 Harmonic CLKIN 4 No AUX_CLK 5 CLKIN > Upper Frequency Limit (BOUF) 6 Reserved 7 Multiple Limit Faults CLKSALGN Clock Alignment. (R/NW) The CGU_STAT.CLKSALGN bit indicates whether a clock alignment sequence is in progress.
Page 187 ADSP-SC58x CGU Register Descriptions Time Stamp Counter 32 LSB Register register address is used to read the CoreSight time stamp counter LSB 32-bit (bits [31:0]) CGU_TSCOUNT0 value. VALUE[15:0] (R) TSCOUNT0 Value VALUE[31:16] (R) TSCOUNT0 Value Figure 3-14: CGU_TSCOUNT0 Register Diagram Table 3-20: CGU_TSCOUNT0 Register Fields Bit No.
Page 188 ADSP-SC58x CGU Register Descriptions Time Stamp Counter 32 MSB Register register address is used to read the CoreSight time stamp counter MSB 32-bit (bits [63:32]) CGU_TSCOUNT1 value. VALUE[15:0] (R) Timestamp Counter 32 MSB VALUE[31:16] (R) Timestamp Counter 32 MSB Figure 3-15: CGU_TSCOUNT1 Register Diagram Table 3-21: CGU_TSCOUNT1 Register Fields Bit No.
Page 189 ADSP-SC58x CGU Register Descriptions Time Stamp Control Register register controls the operation of the CoreSight time stamp counter. CGU_TSCTL TSDIV (R/W) EN (R/W) Counter's Clock Divider Counter Enable LOAD (R/W) Load Counter LOCK (R/W) Lock Figure 3-16: CGU_TSCTL Register Diagram Table 3-22: CGU_TSCTL Register Fields Bit No.
Page 190 ADSP-SC58x CGU Register Descriptions Time Stamp Counter Initial 32 LSB Value Register register holds the least significant bits (bits [31:0]) value that is initially loaded to the Core- CGU_TSVALUE0 Sight time stamp counter. VALUE[15:0] (R/W) Counter's 32 LSB Initial Value VALUE[31:16] (R/W) Counter's 32 LSB Initial Value Figure 3-17: CGU_TSVALUE0 Register Diagram...
Page 191 ADSP-SC58x CGU Register Descriptions Time Stamp Counter Initial MSB Value Register register holds the most significant bits (bits [63:32]) value that is initially loaded to the CGU_TSVALUE1 CoreSight time stamp counter. VALUE[15:0] (R/W) Counter's Initial 32 MSB Value VALUE[31:16] (R/W) Counter's Initial 32 MSB Value Figure 3-18: CGU_TSVALUE1 Register Diagram Table 3-24: CGU_TSVALUE1 Register Fields...
Page 192 Clock Distribution Unit (CDU) 4 Clock Distribution Unit (CDU) The Clock Distribution Unit (CDU) consists of an array of multiplexors that select clocks originated from up to four different clock sources. These sources are different clocks that are generated from the CGUs. The multiplexors are configured by software.
Page 193 CDU Functional Description This configuration provides the flexibility to meet the specific clock requirements of the different modules in the system (core, DDR, or CAN module) without compromising the clocking of other modules. Such a flexibility is not possible with a single CGU in the system. With two CGUs: •...
Page 194 CDU Functional Description Table 4-1: Clock Descriptions (Continued) Clock Description SCLK0_1 SCLK0 derived from CGU1 SCLK1_1 SCLK1 derived from CGU1 DCLK_1 DCLK derived from CGU1 OCLK_1 OCLK derived from CGU1 CDU_CLKOn Clocks that come out from the CDU that go to different blocks. CDU Clock Configuration Options The CDU Targets table provides information on clock source and destination options.
Page 195 CDU Functional Description CGU0 SYS_CLKIN0 CCLK0 CCLK1 CLKO0 SHARC0 SYSCLK SCLK0 SCLK1 DCLK OCLK Clocking Options for SHARC0 core CGU0 SYS_CLKIN0 CCLK0 CCLK1 CLKO1 SHARC1 SYSCLK SCLK0 SCLK1 DCLK OCLK Clocking Options for SHARC1 core CGU0 SYS_CLKIN0 CCLK0 CCLK0 CLKO2 SYSCLK SCLK0 SCLK1...
Page 196 CDU Functional Description CGU0 SYS_CLKIN0 CCLK0 CCLK1 SYSCLK SCLK0 SCLK1 DCLK OCLK OCLK4 CGU1 CCLK0 SYS_CLKIN1 CCLK1 SCLK0 SCLK1 DCLK OCLK Figure 4-4: CDU Clock Options - CAN The S/PDIF clock is ideally programmed to operate at 200 MHz (out of the four options). CGU0 SYS_CLKIN0 CCLK0...
Page 197 CDU Programming Model CGU0 SYS_CLKIN0 CCLK0 CCLK1 SYSCLK SCLK0 SCLK1 DCLK OCLK OCLK8 LINKPORT CGU1 CCLK0 SYS_CLKIN1 CCLK1 SCLK0 SCLK1 DCLK OCLK Figure 4-7: CDU Clock Options Link Port The MSI clock can operate at up to 52 MHz for MMC/eMMC operation. The MSI clock can be selected from CGU1 when the OCLK from CGU0 cannot be used.
Page 198 CDU Programming Model • To change the PLL frequency while all cores are idle, set the CGU_CTL.WFI bit (=1). • To change the PLL frequency while the cores are active, clear the CGU_CTL.WFI bit (=0). 4. Read the register. Verify that: CGU_STAT •...
Page 199 ADSP-SC58x CDU Register Descriptions 7. Write to the CDU_CFG[n].SEL bit to select the clock source (the CDU_CFG[n].EN bit should =1). 8. Read the CDU_CFG[n] register. Verify that the CDU_CLKINSEL has the programmed value. 9. Verify that the CDU_STAT.CLKO0 through CDU_STAT.CLKO9 bits =0. ADSP-SC58x CDU Register Descriptions Clock Distribution Unit (CDU) contains the following registers.
Page 200 ADSP-SC58x CDU Register Descriptions CDU Configuration registers control the configuration of the clock multiplexors. CDU0_CFG[n] corresponds to CDU_CFG[n] output clock CDU_CLKO[n]. SEL (R/W) EN (R/W) Select Clock Input Clock Output Enabled LOCK (R/W) Lock Bit Figure 4-9: CDU_CFG[n] Register Diagram Table 4-5: CDU_CFG[n] Register Fields Bit No.
Page 201 ADSP-SC58x CDU Register Descriptions CLKIN Select register controls the configuration of the CLKIN multiplexors. One bit is assigned to each CDU_CLKINSEL CGU in the system. This bit selects either CLKIN0 or CLKINn CGUn inputs. CGU1 (R/W) CGU1 CLKINn Select LOCK (R/W) Lock Bit Figure 4-10: CDU_CLKINSEL Register Diagram Table 4-6: CDU_CLKINSEL Register Fields...
Page 202 ADSP-SC58x CDU Register Descriptions CDU Revision ID MAJOR (R) REV (R) Major Version ID Incremental Version ID Figure 4-11: CDU_REVID Register Diagram Table 4-7: CDU_REVID Register Fields Bit No. Bit Name Description/Enumeration (Access) MAJOR Major Version ID. (R/NW) Incremental Version ID. (R/NW) ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference 4–11...
Page 203 ADSP-SC58x CDU Register Descriptions CDU Status register reflects the status a change in the configuration of the clock muxes. CDU_STAT CLKO9 (R) CLKO0 (R) CDU_CLKO9 Status CDU_CLKO0 Status CLKO8 (R) CLKO1 (R) CDU_CLKO8 Status CDU_CLKO1 Status CLKO7 (R) CLKO2 (R) CDU_CLKO7 Status CDU_CLKO2 Status CLKO6 (R)
Page 204 ADSP-SC58x CDU Register Descriptions Table 4-8: CDU_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) CLKO8 CDU_CLKO8 Status. (R/NW) 0 No Configuration Change in Progress 1 Configuration Change in Progress CLKO7 CDU_CLKO7 Status. (R/NW) 0 No Configuration Change in Progress 1 Configuration Change in Progress CLKO6 CDU_CLKO6 Status.
Page 205 Dynamic Power Management (DPM) 5 Dynamic Power Management (DPM) The dynamic power management (DPM) unit of the processor controls transitions between different power-saving modes. DPM Features The DPM allows programs to control the power mode of the processor as follows. •...
Page 206 DPM Operating Modes Acronym for the dynamic power management (DPM) controller. Full-on mode The normal operating mode in which all clock domains are derived from the PLL. Acronym for the PLL control unit (PCU). Acronym for the phase-locked loop (PLL). Acronym for the reset control unit (RCU).
Page 207 DPM Event Control DPM Event Control The DPM event is triggered when an enabled wake-up is asserted. The DPM generates bus errors when a misaligned access to a register occurs. It also generates errors when an attempt is made to access unused DPM address space or a write-protected register.
Page 208 DPM Programming Model Table 5-2: DPM_PER_DIS0 Register Mapping (Continued) Peripheral Name Gated Module clocks DPM_PER_DIS0 bit DAI1 SCLK0 CLK05 SYSCLK HAE0 SCLK0 SINC0 SCLK0 MLB0 SYSCLK EMAC0 (GigE) CLKO7 SCLK0 EMAC1(10/100) SCLK0 MSI0 CLKO9 SCLK0 EMDMA0/CH0 SCLK0 EMDMA0/CH1 SCLK0 PCIe CLKO6 SYSCLK CRYPTO ACCELERATOR-0(EIP-150/...
Page 209 ADSP-SC58x DPM Register Descriptions Table 5-3: DPM_PER_DIS1 Register Mapping Peripheral Name Gated Module Clocks DPM_PER_DIS1 bit TWI0 SCLK0 TWI1 SCLK0 TWI2 SCLK0 USB0 SCLK0 USB1 SCLK0 ADSP-SC58x DPM Register Descriptions Dynamic Power Management (DPM) contains the following registers. Table 5-4: ADSP-SC58x DPM Register List Name Description DPM_CTL...
Page 210 ADSP-SC58x DPM Register Descriptions Control Register register controls sleep modes selections and PLL operations of the DPM. A write protect feature DPM_CTL permits locking out changes to this register. LOCK (R/W) Lock Figure 5-1: DPM_CTL Register Diagram Table 5-5: DPM_CTL Register Fields Bit No.
Page 211 ADSP-SC58x DPM Register Descriptions Peripherals Disable Register 0 register is used to shut off the clocks to peripherals that are not used in an application to DPM_PER_DIS0 save clock switching power. VALUE[15:0] (R/W) Peripheral Disable LOCK (R/W) VALUE[30:16] (R/W) Lock Bit Peripheral Disable Figure 5-2: DPM_PER_DIS0 Register Diagram Table 5-6: DPM_PER_DIS0 Register Fields...
Page 212 ADSP-SC58x DPM Register Descriptions Table 5-6: DPM_PER_DIS0 Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 14 EMDMA0/CH0 15 PCIe-Slave 16 CRYPTO ACCELERATOR-0 (EIP-150/PKP) 17 CRYPTO ACCELERATOR-1 (EIP-150/PKP) 18 SMPU-SMC 19 Reserved 20 SMPU-L2CTL-CL2-0 21 SMPU-L2CTL-DL2-0 22 SMPU-L2CTL-CL2-1 23 SMPU-L2CTL-DL2-1 24 SMPU-L2CTL-CL2-2 25 SMPU-L2CTL-DL2-2 26 SMPU-PCIE-SLV...
Page 213 ADSP-SC58x DPM Register Descriptions Peripherals Disable Register 1 register is used to shut off the clocks to peripherals that are not used in an application to DPM_PER_DIS1 save clock switching power. VALUE[15:0] (R/W) Peripheral Disable LOCK (R/W) VALUE[18:16] (R/W) Lock Bit Peripheral Disable Figure 5-3: DPM_PER_DIS1 Register Diagram Table 5-7: DPM_PER_DIS1 Register Fields...
Page 214 ADSP-SC58x DPM Register Descriptions Table 5-7: DPM_PER_DIS1 Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 5–10 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference...
Page 215 ADSP-SC58x DPM Register Descriptions Revision ID register provides the revision of the DPM module. DPM_REVID MAJOR (R) REV (R) Major Version ID Incremental Version ID Figure 5-4: DPM_REVID Register Diagram Table 5-8: DPM_REVID Register Fields Bit No. Bit Name Description/Enumeration (Access) MAJOR Major Version ID.
Page 216 ADSP-SC58x DPM Register Descriptions Status Register register contains bits that report the state of the module and various errors. DPM_STAT PRVMODE (R) CURMODE (R) Previous Mode Current Mode HVBSYERR (R/W1C) ADDRERR (R/W1C) HV Busy Error Address Error LWERR (R/W1C) Lock Write Error Figure 5-5: DPM_STAT Register Diagram Table 5-9: DPM_STAT Register Fields Bit No.
Page 217 ADSP-SC58x DPM Register Descriptions Table 5-9: DPM_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 0 Reset 1 Full-On 2 Reserved 3 Reserved 4 Reserved 5-15 Reserved CURMODE Current Mode. (R/NW) The DPM_STAT.CURMODE bit field indicates the current mode of the the module. 0 Reserved 1 Full-On 2 Reserved...
Page 218 Reset Control Unit (RCU) 6 Reset Control Unit (RCU) Reset is the initial state of the whole processor at power-on or the run-time state of any core, as controlled by anoth- er core in the device via the RCU or as a a result of a hardware or software triggered event. In this state, all control registers are set to their default values and functional units are idle.
Page 219 RCU Functional Description RCU Functional Description This section provides information on the function of RCU module. Hardware reset using SYS_HWRST pin Asserting the SYS_HWRST pin resets all functional units, except the real time clock (RTC) (if present). Hardware reset through RCU The RCU can perform a full system reset which can be initiated through hardware blocks like the SEC, the TRU, and the oscillator watchdog.
Page 220 RCU Functional Description Table 6-1: ADSP-SC58x RCU Register List (Continued) Name Description RCU_STAT Status Register RCU_SVECT0 Software Vector Register 0 RCU_SVECT1 Software Vector Register 1 RCU_SVECT2 Software Vector Register 2 RCU_SVECT_LCK SVECT Lock Register ADSP-SC58x RCU Trigger List Table 6-2: ADSP-SC58x RCU Trigger List Masters Trigger ID Name Description...
Page 221 RCU Functional Description System Reset (by source) Software can trigger the reset by writing to the RCU_CTL register or by another functional unit such as the TRU or any of the generic reset inputs. RCU Architectural Concepts To understand the architecture of the RCU, it is important to consider the reset sources and how differing resets affect the functional units of the processor.
Page 222 Resetting the ARM Core through Another Core or System Master write error occurs if an attempt is made to write a lock RCU register. The address error occurs if a read-only register is written to or if an attempt is made to a reserved address within the RCU MMR address range. Resetting the ARM Core through Another Core or System Mas- The RCU allows reset of a given core n using another core or system master.
Page 223 Resetting a SHARC+ Core Through Another Core • CCR0 − SHARC0 core reset request bit in shared variable • IDLE0 − SHARC0 IDLE acknowledgement bit in shared variable • CCR1 − SHARC1 core reset request bit in shared variable • IDLE1 − SHARC1 IDLE acknowledgement bit in shared variable Use the following programming to reset the SHARC+ core.
Page 224 ADSP-SC58x RCU Register Descriptions 15. Poll the RCU_CRSTAT.CR[n] bit until core n is in reset. 16. Once the core is in reset, clear the RCU_SIDIS.SI[n] bit to re-enable the core interfaces. 17. Clear the RCU_CRCTL.CR[n] bit to take core n out of reset. 18.
Page 225 ADSP-SC58x RCU Register Descriptions Boot Code Register register can be used to determine if and how core boots. This register is set to its default values by RCU_BCODE RESET. IDLEONENTRY (R/W) NOKERNEL (R/W) Idle On Entry No Boot Kernel NOL2CONFIG (R/W) NOVECTINIT (R/W) No L2 Configuration No Vector Initialize...
Page 226 ADSP-SC58x RCU Register Descriptions Table 6-6: RCU_BCODE Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) NOCORE1 No Core 1 Present. (R/W) The RCU_BCODE.NOCORE1 bit indicates the presence of core 1. 0 Core does not exist 1 Core exists NOCORE0 No Core 0 Present.
Page 227 ADSP-SC58x RCU Register Descriptions Table 6-6: RCU_BCODE Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) NOCACHE No Cache. (R/W) The RCU_BCODE.NOCACHE bit configures the RCU to not perform a cache initiali- zation and to not enable the cache. 0 Enable and initialize cache 1 Do not initialize or enable cache NOMEMINIT No Memory Initialization.
Page 228 ADSP-SC58x RCU Register Descriptions Core Reset Outputs Control Register The RCU core reset control n registers (RCU_CRCTL) include a lock bit (RCU_CRCTL.LOCK) and a core reset bit (RCU_CRCTL.CR[n]) for each core reset signal on the product. CR[n] (R/W) Core Reset Outputs LOCK (R/W) Lock Figure 6-2: RCU_CRCTL Register Diagram...
Page 229 ADSP-SC58x RCU Register Descriptions Core Reset Outputs Status Register The RCU core reset status register (RCU_CRSTAT) contains status bits, indicating which core reset signals have been asserted. CR[n] (R/W1C) Core Reset Outputs Figure 6-3: RCU_CRSTAT Register Diagram Table 6-8: RCU_CRSTAT Register Fields Bit No.
Page 230 ADSP-SC58x RCU Register Descriptions Control Register The RCU control register (RCU_CTL) provides a register lock, enables for the core and system reset requests inputs and control for the Reset Output pin. CRSTREQEN (R/W) SYSRST (R0/W) Core Reset Request Enabled System Reset SRSTREQEN (R/W) RSTOUTASRT (R0/W) System Reset Request Enabled...
Page 231 ADSP-SC58x RCU Register Descriptions Table 6-9: RCU_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) RSTOUTDSRT Reset Out Deassert. (R0/W) The RCU_CTL.RSTOUTDSRT bit controls the deassertion of the system reset pin. 0 No Action 1 Deassert RSTOUT RSTOUTASRT Reset Out Assert. (R0/W) The RCU_CTL.RSTOUTASRT bit controls assertion of the system reset pin.
Page 232 ADSP-SC58x RCU Register Descriptions Message Register is a general-purpose register. It is intended to provide flexibility for Boot ROM code and to pass RCU_MSG predefined variables to the debugger. Please see the Booting chapter for product-specific details. C2IDLE (R/W) ERRCODE (R/W) Core 2 Idle ROM Error Code C1IDLE (R/W)
Page 233 ADSP-SC58x RCU Register Descriptions Table 6-10: RCU_MSG Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) CALLBACK Callback Call Flag. (R/W) The RCU_MSG.CALLBACK bit indicates that a flag has been set by the boot code prior to a callback call. 0 Flag not set 1 Flag set CALLINIT...
Page 234 ADSP-SC58x RCU Register Descriptions Table 6-10: RCU_MSG Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) HALTONAPP Halt on Application Call. (R/W) The RCU_MSG.HALTONAPP bit generates an emulation exception prior to an appli- cation call. 0 Do not generate exception 1 Generate exception L2INIT L2 Initialized.
Page 235 ADSP-SC58x RCU Register Descriptions Table 6-10: RCU_MSG Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ERRCODE ROM Error Code. (R/W) The RCU_MSG.ERRCODE bit indicates the error code of the ROM. It is valid only when in the error handler. 6–18 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference...
Page 236 ADSP-SC58x RCU Register Descriptions Message Clear Bits Register register is used to clear bits in register. Reading this register returns 0x00000000. RCU_MSG_CLR RCU_MSG CLR[15:0] (R0/W1C) Clear MSG Register Bits CLR[31:16] (R0/W1C) Clear MSG Register Bits Figure 6-6: RCU_MSG_CLR Register Diagram Table 6-11: RCU_MSG_CLR Register Fields Bit No.
Page 237 ADSP-SC58x RCU Register Descriptions Message Set Bits Register register is used to set bits in register. Reading this register returns 0x00000000. RCU_MSG_SET RCU_MSG SET[15:0] (R0/W1S) Set Message Bits SET[31:16] (R0/W1S) Set Message Bits Figure 6-7: RCU_MSG_SET Register Diagram Table 6-12: RCU_MSG_SET Register Fields Bit No.
Page 238 ADSP-SC58x RCU Register Descriptions System Interface Disable Register The RCU system interface disable register (RCU_SIDIS) lets the RCU assert a system interface disable request to functional units in the processor. This register is set to its default values by a hard reset or any system reset event. For information on mapping between RCU_SIDIS bits and functional units, see the RCU functional description.
Page 239 ADSP-SC58x RCU Register Descriptions System Interface Status Register The RCU system interface status register (RCU_SISTAT) indicates whether a functional unit has or has not ac- knowledged an RCU unit disable request. SI[n] (R) System Interface Disable Acknowledge [1:0] Figure 6-9: RCU_SISTAT Register Diagram Table 6-14: RCU_SISTAT Register Fields Bit No.
Page 240 ADSP-SC58x RCU Register Descriptions Status Register The RCU status register (RCU_STAT) contains status bits for all RCU reset sources, reset status, and boot mode inputs. Status bits for reset sources are sticky and can cleared by software. Error status bits are cleared by any reset event.
Page 241 ADSP-SC58x RCU Register Descriptions Table 6-15: RCU_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ADDRERR Address Error. (R/W1C) The RCU_STAT.ADDRERR bit indicates that the RCU generated an address error. This status bit is sticky; write-1-to-clear it. 0 No Error 1 Error Occurred 11:8 BMODE...
Page 242 ADSP-SC58x RCU Register Descriptions Software Vector Register 0 register contains the default location of the first instruction to execute after a reset. RCU_SVECT0 VALUE[15:0] (R/W) Core 0 Reset Vector VALUE[31:16] (R/W) Core 0 Reset Vector Figure 6-11: RCU_SVECT0 Register Diagram Table 6-16: RCU_SVECT0 Register Fields Bit No.
Page 243 ADSP-SC58x RCU Register Descriptions Software Vector Register 1 VALUE[15:0] (R/W) Reset Vector VALUE[31:16] (R/W) Reset Vector Figure 6-12: RCU_SVECT1 Register Diagram Table 6-17: RCU_SVECT1 Register Fields Bit No. Bit Name Description/Enumeration (Access) 31:0 VALUE Reset Vector. (R/W) 6–26 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference...
Page 244 ADSP-SC58x RCU Register Descriptions Software Vector Register 2 VALUE[15:0] (R/W) Reset Vector VALUE[31:16] (R/W) Reset Vector Figure 6-13: RCU_SVECT2 Register Diagram Table 6-18: RCU_SVECT2 Register Fields Bit No. Bit Name Description/Enumeration (Access) 31:0 VALUE Reset Vector. (R/W) ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference 6–27...
Page 245 ADSP-SC58x RCU Register Descriptions SVECT Lock Register The RCU software vector lock register (RCU_SVECT_LCK) provides a register lock and software vector n enable bits for each processor core on the product. This register is set to its default values by a hard reset or any system reset event.
Page 246 System Event Controller (SEC) and Generic Interrupt Controller (GIC) 7 System Event Controller (SEC) and Generic Interrupt Controller (GIC) There are two interrupt controllers—a generic interrupt controller (GIC) for the ARM core and the system event controller (SEC) for the SHARC cores. System event management is the responsibility of the system event controller (SEC).
Page 247 SEC Functional Description • Slave control port which provides access to all SEC registers for configuration, status, and interrupt or fault service model. • Global locking supports a register level protection model to prevent writes to “locked” registers. SEC Functional Description The following sections provide a functional description of the SEC.
Page 248 SEC Functional Description Table 7-1: ADSP-SC58x SEC Register List (Continued) Name Description SEC_FCOPP Fault COP Period Register SEC_FCOPP_CUR Fault COP Period Current Register SEC_FCTL Fault Control Register SEC_FDLY Fault Delay Register SEC_FDLY_CUR Fault Delay Current Register SEC_FEND Fault End Register SEC_FSID Fault Source ID Register SEC_FSRDLY...
Page 249 SEC Functional Description Table 7-3: ADSP-SC58x Combined SEC and GIC Interrupt List (Continued) Module Event/Interrupt SEC ID GIC ID SEC/GIC Interrupt Name SW Interrupt 2, supervisor call, core ID = 0 GIC_SOFT02 SW Interrupt 3, prefetch call, core ID = 0 GIC_SOFT03 SW Interrupt 4, data abort, core ID = 0 GIC_SOFT04...
Page 250 SEC Functional Description Table 7-3: ADSP-SC58x Combined SEC and GIC Interrupt List (Continued) Module Event/Interrupt SEC ID GIC ID SEC/GIC Interrupt Name GPTIMER GP TIMER0 Timer 0 TIMER0_TMR0 GPTIMER GP TIMER0 Timer 1 TIMER0_TMR1 GPTIMER GP TIMER0 Timer 2 TIMER0_TMR2 GPTIMER GP TIMER0 Timer 3 TIMER0_TMR3 EPWM...
Page 251 SEC Functional Description Table 7-3: ADSP-SC58x Combined SEC and GIC Interrupt List (Continued) Module Event/Interrupt SEC ID GIC ID SEC/GIC Interrupt Name SPORT SPORT1 Channel A Status SPORT1_A_STAT SPORT SPORT1 Channel B DMA SPORT1_B_DMA SPORT SPORT1 Channel B Status SPORT1_B_STAT SPORT SPORT4 Channel A DMA SPORT4_A_DMA...
Page 252 SEC Functional Description Table 7-3: ADSP-SC58x Combined SEC and GIC Interrupt List (Continued) Module Event/Interrupt SEC ID GIC ID SEC/GIC Interrupt Name CAN1 Transmit CAN1_TX CAN1 Status CAN1_STAT SPORT SPORT2 Channel A DMA SPORT2_A_DMA SPORT SPORT2 Channel A Status SPORT2_A_STAT SPORT SPORT2 Channel B DMA SPORT2_B_DMA...
Page 253 SEC Functional Description Table 7-3: ADSP-SC58x Combined SEC and GIC Interrupt List (Continued) Module Event/Interrupt SEC ID GIC ID SEC/GIC Interrupt Name UART UART1 Status UART1_STAT UART UART2 Transmit DMA UART2_TXDMA UART UART2 Receive DMA UART2_RXDMA UART UART2 Status UART2_STAT TWI0 Data TWI0_DATA TWI1 Data...
Page 254 SEC Functional Description Table 7-3: ADSP-SC58x Combined SEC and GIC Interrupt List (Continued) Module Event/Interrupt SEC ID GIC ID SEC/GIC Interrupt Name FFTA FFTA0 Receive DMA FFTA0_RXDMA FFTA FFTA0 Status FFTA0_STAT FIR0 DMA FIR0_DMA FIR0 Status FIR0_STAT IIR0 DMA IIR0_DMA IIR0 Status IIR0_STAT HADC...
Page 255 SEC Functional Description Table 7-3: ADSP-SC58x Combined SEC and GIC Interrupt List (Continued) Module Event/Interrupt SEC ID GIC ID SEC/GIC Interrupt Name SPORT SPORT1 Channel A DMA Error SPORT1_A_DMA_ERR SPORT SPORT1 Channel B DMA Error SPORT1_B_DMA_ERR SPORT SPORT4 Channel A DMA Error SPORT4_A_DMA_ERR SPORT SPORT4 Channel B DMA Error...
Page 256 SEC Functional Description Table 7-3: ADSP-SC58x Combined SEC and GIC Interrupt List (Continued) Module Event/Interrupt SEC ID GIC ID SEC/GIC Interrupt Name HAE0 RX DMA Channel 1 Error HAE0_RXDMA_CH1_ERR HAE0 TX DMA Channel 0 Error HAE0_TXDMA_ERR EPPI EPPI0 DMA Channel 0 Error EPPI0_CH0_DMA_ERR EPPI EPPI0 DMA Channel 1 Error...
Page 257 SEC Functional Description Table 7-3: ADSP-SC58x Combined SEC and GIC Interrupt List (Continued) Module Event/Interrupt SEC ID GIC ID SEC/GIC Interrupt Name PCIE PCIe Status PCIE0_STAT PCIE PCIe DMA Completion PCIE0_DMA 246 − 247 278 − 279 Reserved Reserved TRU0 Interrupt 0, core ID = 0 Reserved TRU_INT0 TRU0 Interrupt 1, core ID = 0...
Page 258 SEC Functional Description SEC Fault Interface, fault management subblock of the SEC. SEC Block Diagram The SEC Block Diagram shows the event management architecture. System sources connect to the SEC through the SSI. Each core has a dedicated SCI. The SFI provides fault action connections to the rest of the system.
Page 259 SEC Block Diagram SEC Fault Interface (SFI) FCTL FSTAT FSID TO (Trigger Out) SR (System Reset) Event Actions FDELAYCUR FDELAY (Fault / COP) Figure 7-3: SFI Block Diagram Fault Management System sources can be enabled as fault sources in the SEC_SCTL[n] register.
Page 260 SEC Block Diagram to the core. The SCI maintains the coherency for the system event service model implemented on the connected core. SEC Core Interface (SCI) CPMSK CPND CPLVL CACT IDLE CGMSK CCTL CSID Figure 7-4: SCI Overview Block Diagram SEC Source Interface (SSI) The SSI manages all of the system event sources.
Page 261 SEC Architectural Concepts System Interrupt Groups System sources can be assigned to groups using the SEC_SCTL[n].GRP bit field. Source groups allow fast context switching for system interrupts at each SCI. The SEC_CGMSK[n] register allows quick masking of interrupt groups of unlimited size with a single write operation. System Interrupt Flow An enabled and asserted system interrupt source is latched at the SSI and routed to the appropriate SCI based on the core target select (SEC_SCTL[n].CTG) bit field setting.
Page 262 SEC Architectural Concepts 1. The SEC compares the SEC_CPND[n] (A) register value to the SEC_CACT[n] register and if the interrupt in the register is a higher priority, continue. SEC_CPND[n] 2. The SEC copies (A) register to the register and asserts the interrupt signal. SEC_CPND[n] SEC_CSID[n] 3.
Page 263 SEC Programming Model • Proper configuration of a system interrupt source (for example a peripheral or DMA) • A core interrupt or event service model The core must be configured for response to system interrupts from the SEC. The SEC must be configured to ena- ble and map the system interrupt source to the correct SCI and to forward interrupts to the connected core.
Page 264 Programming Examples • Fault Output. This configuration alows the SEC to indicate the fault status based on the SEC_FCTL.CMS bit configuration. • Computer Operating Normally (COP) mode. To configure fault output for COP mode, set the SEC_FCTL.FOEN bit to enable fault output. Set the SEC_FCTL.CMS bit to select COP mode to toggle the fault pin when no fault is active.
Page 265 Programming Examples priority level, thus providing the flexibility to have lower-priority interrupt sources considered before higher- priority sources. ADDITIONAL INFORMATION: The SEC_CPMSK[n] SEC_CGMSK[n] registers must also can be programmed to mask the interrupts based on the customized levels and grouping. Core/SEC Handshaking Requirements to Ensure Proper Interrupt Handling Interrupt handling within an individual core requires specific handshaking with the SEC to ensure that nested inter- rupts are properly tracked and that new peripheral interrupts being raised within the SEC are either passed immedi-...
Page 266 Programming Examples 2. Write to the SEC_FCTL register to configure specific fault actions. 3. Write to the SEC_FDLY bit field to specify fault delay. 4. Write to the control register of a specific source to enable the source as a fault. Configuring the WDOG Expiry Event to Issue a System Reset Use the following procedure to configure the WDOG timer to issue a system reset.
Page 267 ADSP-SC58x SEC Register Descriptions Writing to SEC_FEND to end a fault with both the SEC_FCTL.FOEN bit and the SEC_FCTL.FIEN bit set can result in erroneous external fault detection. If this operation (ending a fault) and configuration (fault input and fault output enabled) are required by the application, clear the SEC_FCTL.FOEN bit prior to writing to SEC_FEND.
Page 268 ADSP-SC58x SEC Register Descriptions Table 7-4: ADSP-SC58x SEC Register List (Continued) Name Description SEC_GSTAT Global Status Register SEC_RAISE Global Raise Register SEC_SCTL[n] Source Control Register n SEC_SSTAT[n] Source Status Register n ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference 7–23...
Page 269 ADSP-SC58x SEC Register Descriptions SCI Active Register n The SEC SCI active interrupt register (SEC_CACT[n]) contains the source ID and priority of the highest priority active interrupt detected by the SEC prioritizer. PRIO (R) SID (R) Highest Active IRQ Priority Highest Active IRQ Source ID Figure 7-6: SEC_CACT[n] Register Diagram Table 7-5: SEC_CACT[n] Register Fields...
Page 270 ADSP-SC58x SEC Register Descriptions SCI Control Register n The SEC control register (SEC_CCTL[n]) contains SCI control bits for all system sources. WFI (R0/W) EN (R/W) Wait For Idle Enable RESET (R0/W) Reset LOCK (R/W) NMIEN (R/W) Lock NMI Enable Figure 7-7: SEC_CCTL[n] Register Diagram Table 7-6: SEC_CCTL[n] Register Fields Bit No.
Page 271 ADSP-SC58x SEC Register Descriptions Table 7-6: SEC_CCTL[n] Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) RESET Reset. (R0/W) When set, the SEC_CCTL[n].RESET bit resets all SCI registers to their default val- ues. 0 No Action 1 Reset Enable. (R/W) The SEC_CCTL[n].EN bit controls operation of the SCI.
Page 272 ADSP-SC58x SEC Register Descriptions SCI Group Mask Register n The SEC SCI group mask register (SEC_CGMSK[n]) contains selections for a group mask, an ungroup mask, and a register lock. This register contains the system interrupt group masks for the connected core. The core uses the SEC_CGMSK[n].UGRP and SEC_CGMSK[n].GRP fields to mask (disable) interrupts from the specified groups.
Page 273 ADSP-SC58x SEC Register Descriptions Table 7-7: SEC_CGMSK[n] Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 4 Mask group 2 5 Mask groups 0, 2 6 Mask groups 1, 2 7 Mask groups 0, 1, 2 8 Mask group 3 9 Mask groups 0, 3 10 Mask groups 1, 3 11 Mask groups 0, 1, 3...
Page 274 ADSP-SC58x SEC Register Descriptions SCI Priority Level Register n The SEC SCI priority level register (SEC_CPLVL[n]) contains selections for priority levels and a register lock. This register is used to divide the total number of priority levels into sub-levels. The sub-level priority resolution provides the tie breaker for simultaneously pending interrupts assigned to the same level.
Page 275 ADSP-SC58x SEC Register Descriptions Table 7-8: SEC_CPLVL[n] Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 6 7 MSBs (128 priority levels) 7 8 MSBs (256 priority levels) 7–30 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference...
Page 276 ADSP-SC58x SEC Register Descriptions SCI Priority Mask Register n The SEC SCI priority mask register (SEC_CPMSK[n]) contains the SCI priority mask for core n and includes a register lock. PRIO (R/W) IRQ Priority Mask LOCK (R/W) Lock Figure 7-10: SEC_CPMSK[n] Register Diagram Table 7-9: SEC_CPMSK[n] Register Fields Bit No.
Page 277 ADSP-SC58x SEC Register Descriptions Core Pending Register n The SCI pending interrupt register (SEC_CPND[n]) contains the source ID and priority of the highest priority pending interrupt detected by the SEC prioritizer. PRIO (R) SID (R) Highest Pending IRQ Priority Highest Pending IRQ Source ID Figure 7-11: SEC_CPND[n] Register Diagram Table 7-10: SEC_CPND[n] Register Fields Bit No.
Page 278 ADSP-SC58x SEC Register Descriptions SCI Source ID Register n The SCI source ID register (SEC_CSID[n]) contains the source ID of the interrupt last issued to core n. The SEC_CSID[n] register value is loaded by the SCI when a system interrupt indication is sent to core n. The SCI does not change the SEC_CSID[n] until after the interface receives an interrupt acknowledge from core n.
Page 279 ADSP-SC58x SEC Register Descriptions SCI Status Register n The SCI status register (SEC_CSTAT[n]) contains status bits, indicating the operational status of the SCI. WFI (R/W1C) ERR (R/W1C) Wait For Idle Error SIDV (R) ERRC (R) SID Valid Error Cause ACTV (R) PNDV (R) ACT Valid PND Valid...
Page 280 ADSP-SC58x SEC Register Descriptions Table 7-12: SEC_CSTAT[n] Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ACTV ACT Valid. (R/NW) The SEC_CSTAT[n].ACTV bit indicates (if set) that the current value in the SEC_CACT[n] register is valid. The SCI sets the SEC_CSTAT[n].ACTV bit when updating the SEC_CACT[n] registers with a new value.
Page 281 ADSP-SC58x SEC Register Descriptions Global End Register The SEC global end register (SEC_END) contains a source ID interrupt service end field (SEC_END.SID). When a core has finished servicing an interrupt, the core writes the SEC_END.SID field in the SEC_END register. This write causes the SEC to clear the SEC_SSTAT[n].ACT bit in the SEC_SSTAT[n] register of the corresponding...
Page 282 ADSP-SC58x SEC Register Descriptions Fault COP Period Register The SEC fault COP period register (SEC_FCOPP) contains the width value (count in (SEC) clock cycles) for the high and low phase of the computer operating properly (COP) toggled output on the COP pin. Note that the actual high/low phase value is the SEC_FCOPP.COUNT programmed value plus 1.
Page 283 ADSP-SC58x SEC Register Descriptions Fault COP Period Current Register The SEC fault COP period current register (SEC_FCOPP_CUR) contains the active count (in (SEC) clock periods) for the current phase (high or low) of the computer operating properly (COP) toggled output on the COP pin. The SEC loads the SEC_FCOPP_CUR register from the...
Page 284 ADSP-SC58x SEC Register Descriptions Fault Control Register The SEC fault control register (SEC_FCTL) contains fault control bits for all SEC channels. This register controls the operation of the System Fault Management Interface (SFI). TES (R/W) EN (R/W) Trigger Event Select Enable CMS (R/W) RESET (R0/W)
Page 285 ADSP-SC58x SEC Register Descriptions Table 7-16: SEC_FCTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) COP Mode Select. (R/W) The SEC_FCTL.CMS selects the SEC mode for handling fault input. In COP mode, the SEC toggles the COP pin to indicate that no fault is active and ceases toggling the pin to indicate that a fault is active.
Page 286 ADSP-SC58x SEC Register Descriptions Table 7-16: SEC_FCTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Enable. (R/W) The SEC_FCTL.EN bit controls the operational state of the SEC. Clearing the SEC_FCTL.EN bit halts the execution of the SEC without resetting status registers. Setting the SEC_FCTL.EN bit enables the SEC to begin or resume operation with the current configuration and status.
Page 287 ADSP-SC58x SEC Register Descriptions Fault Delay Register The SEC fault delay register (SEC_FDLY) contains the number (SEC_FDLY.COUNT field) of (SEC) clock peri- ods to delay from fault pending to fault active, when actions are enabled. COUNT[15:0] (R/W) Fault Delay COUNT[31:16] (R/W) Fault Delay Figure 7-18: SEC_FDLY Register Diagram Table 7-17: SEC_FDLY Register Fields...
Page 288 ADSP-SC58x SEC Register Descriptions Fault Delay Current Register The SEC fault delay current register (SEC_FDLY_CUR) contains the active count (SEC_FDLY_CUR.COUNT field) in (SEC) clock periods for the delay from fault pending to fault active, when actions are enabled. The count is loaded from the SEC_FDLY register when a fault becomes pending (SEC_FSTAT.PND bit is set).
Page 289 ADSP-SC58x SEC Register Descriptions Fault End Register The SEC fault end register (SEC_FEND) contains fault source ID and internal/external fields. This register receives fault end indication from a core. SID (R/W) Source ID FEXT (R/W) Fault External Figure 7-20: SEC_FEND Register Diagram Table 7-19: SEC_FEND Register Fields Bit No.
Page 290 ADSP-SC58x SEC Register Descriptions Fault Source ID Register The SEC fault source ID register (SEC_FSID) contains a fault source ID and internal/external fields. NOTE:These bits are not reset by system reset so that a fault that automatically triggers a system reset to avoid a fault may be analyzed after the reset occurs.
Page 291 ADSP-SC58x SEC Register Descriptions Fault System Reset Delay Register The SEC fault system reset delay register (SEC_FSRDLY) contains the number (SEC_FSRDLY.COUNT field) of (SEC) clock periods for the delay from a fault becoming active to system reset request assertion, if enabled. COUNT[15:0] (R/W) Fault System Reset Delay COUNT[31:16] (R/W)
Page 292 ADSP-SC58x SEC Register Descriptions Fault System Reset Delay Current Register The SEC fault system reset delay current register (SEC_FSRDLY_CUR) contains the active count (SEC_FSRDLY_CUR.COUNT field) in (SEC) clock periods for the delay from fault active to system reset assertion, if enabled. The count is loaded from the SEC_FSRDLY register when a fault becomes active (SEC_FSTAT.ACT bit is set).
Page 293 ADSP-SC58x SEC Register Descriptions Fault Status Register The SEC fault status register (SEC_FSTAT) indicates the operational status of the SFI. NPND (R) ERR (R/W1C) Next Pending Fault Error ACT (R) ERRC (R) Fault Active Error Cause PND (R) Pending Fault Figure 7-24: SEC_FSTAT Register Diagram Table 7-23: SEC_FSTAT Register Fields Bit No.
Page 294 ADSP-SC58x SEC Register Descriptions Table 7-23: SEC_FSTAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Pending Fault. (R/NW) The SEC_FSTAT.PND bit indicates a fault source has signaled a fault assertion to the SEC, but the SEC has not yet triggered the event actions due to the delay selected with SEC_FDLY register.
Page 295 ADSP-SC58x SEC Register Descriptions Global Control Register The SEC global control register (SEC_GCTL) provides register locking, reset, and enable for the SEC module. RESET (R0/W) EN (R/W) Reset Enable LOCK (R/W) Lock Figure 7-25: SEC_GCTL Register Diagram Table 7-24: SEC_GCTL Register Fields Bit No.
Page 296 ADSP-SC58x SEC Register Descriptions Global Status Register The SEC global status register (SEC_GSTAT) contains global status bits for the SEC. SCI (R) ERR (R/W1C) SCI ID for SCI Error Error ERRC (R) Error Cause LWERR (R/W1C) SID (R) Lock Write Error Source ID for SSI Error ADRERR (R/W1C) Address Error...
Page 297 ADSP-SC58x SEC Register Descriptions Table 7-25: SEC_GSTAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ERRC Error Cause. (R/NW) When the SEC updates the SEC_GSTAT.ERR bit, the SEC updates the SEC_GSTAT.ERRC bits to indicate the error type. Note that for SCI errors, the error status represents an OR of all the errors from each SCI.
Page 298 ADSP-SC58x SEC Register Descriptions Global Raise Register The SEC global raise register (SEC_RAISE) contains a source ID event set-to-pending field (SEC_RAISE.SID). When a source ID value is written to this field, the SEC raises the source's event status to pending. SID (R/W) Source ID Figure 7-27: SEC_RAISE Register Diagram...
Page 299 ADSP-SC58x SEC Register Descriptions Source Control Register n The SEC source control register (SEC_SCTL[n]) contains control bits to configure the SEC event sources. This register controls the configuration of the corresponding SEC event source. PRIO (R/W) IEN (R/W) Priority Level Select Interrupt Enable ERREN (R/W) FEN (R/W)
Page 300 ADSP-SC58x SEC Register Descriptions Table 7-27: SEC_SCTL[n] Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 19:16 Group Select. (R/W) The SEC_SCTL[n].GRP bits each select a specific group for the interrupt. Each system interrupt can be assigned to any combination of groups supported by the SEC_SCTL[n].GRP field.
Page 301 ADSP-SC58x SEC Register Descriptions Table 7-27: SEC_SCTL[n] Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Fault Enable. (R/W) The SEC_SCTL[n].FEN bit controls whether the SEC may forward an interrupt request to the SEC fault interface as a fault source. This bit does not affect the ability of an interrupt source to set an interrupt as pending.
Page 302 ADSP-SC58x SEC Register Descriptions Source Status Register n The SEC event source status register (SEC_SSTAT[n]) contains bits indicating the status of the corresponding event source n. An event source may be: pending, active, active and pending, or neither pending nor active. ACT (R/W1C) ERR (R/W1C) Active Source...
Page 303 GIC Overview Table 7-28: SEC_SSTAT[n] Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Pending Source. (R/W1C) The SEC_SSTAT[n].PND bit indicates the source has signaled an event request, but the event request has not been (or is not currently being) serviced. A SEC_SSTAT[n].PND bit is set by the SEC on detection of an assertion of the corre- sponding system source input.
Page 304 GIC Overview Each interrupt can be configured as a normal or a secure interrupt. Software force registers and software priority masking are also supported. The "Register Descriptions" section in this chapter provide brief descriptions of these ARM-based registers. For complete information refer to the ARM® Generic Interrupt Controller Architecture version 1.0 Architecture Specification.
Page 305 GIC Functional Description GIC Block Diagram The GIC Block Diagram shows the event management architecture. SYSTEM Distributer CORTEX A5 INTERRUPTS Port 0 Port 1 Figure 7-30: GIC Block Diagram ADSP-SC58x GICDST Register List GIC Distributor Port Table 7-29: ADSP-SC58x GICDST Register List Name Description GICDST_EN...
Page 306 GIC Functional Description Table 7-30: ADSP-SC58x GICCPU Register List Name Description GICCPU_BIN_PT_ALIAS Aliased Binary Point Register (ICCABPR) GICCPU_BIN_PT Binary Point Register (ICCBPR) GICCPU_CTL CPU Interface Control Register (ICCICR) GICCPU_EOI End of Interrupt Register (ICCEOIR) GICCPU_PND_HI Highest Pending Interrupt Register (ICCHPIR) GICCPU_INT_ACK Interrupt Acknowledge Register (ICCIAR) GICCPU_PRIO_MSK...
Page 307 ADSP-SC58x GICDST Register Descriptions GIC Port 0 Enable GICDST_EN register enables global monitoring of the peripheral interrupt signals and forwarding pending in- terrupts to the CPU interfaces. VALUE (R/W) Global Interrupt Monitor Enable Figure 7-31: GICDST_EN Register Diagram Table 7-32: GICDST_EN Register Fields Bit No.
Page 308 ADSP-SC58x GICDST Register Descriptions Software Generated Interrupt Priority Register GICDST_SGI_PRIO[n] register provides the 8-bit priority field for each interrupt supported by the GIC. This field stores the priority of the corresponding interrupt. VALUE (R/W) Software Generated Interrupt Priority Figure 7-32: GICDST_SGI_PRIO[n] Register Diagram Table 7-33: GICDST_SGI_PRIO[n] Register Fields Bit No.
Page 309 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Priority Register GICDST_SPI_PRIO[n] registers provide an 8-bit priority field for each interrupt supported by the GIC. This field stores the priority of the corresponding interrupt. VALUE (R/W) Priority Figure 7-33: GICDST_SPI_PRIO[n] Register Diagram Table 7-34: GICDST_SPI_PRIO[n] Register Fields Bit No.
Page 310 ADSP-SC58x GICDST Register Descriptions Software Generated Interrupt Active Register GICDST_SGI_ACTIVE registers provide a Set-active bit for each interrupt that the GIC supports. Writing to a Set-active bit Activates the corresponding interrupt. These registers are used when preserving and restoring GIC state.
Page 311 ADSP-SC58x GICDST Register Descriptions Software Generated Interrupt Control Register GICDST_SGI_CTL register controls the generation of SGIs.It is implementation defined whether this register has any effect when the forwarding of interrupts by Distributor is disabled by the GICD_CTLR settings. SATT (R/W) SGIINTID (R/W) Security Value of the SGI The Interrupt ID of the SGI...
Page 312 ADSP-SC58x GICDST Register Descriptions Table 7-36: GICDST_SGI_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) SATT Security Value of the SGI. (R/W) The GICDST_SGI_CTL.SATT bit is implemented only if the GIC includes the Se- curity Extensions. This field is writable only by a Secure access. Any Non-secure write to the GICD_SGIR generates an SGI only if the specified SGI is programmed as Group 1, regardless of the value of bit[15] of the write.
Page 313 ADSP-SC58x GICDST Register Descriptions Software Generated Interrupt Clear-Pending Register GICDST_SGI_PND_CLR register provides a clear pending bit for each interrupt supported by the GIC. Writing 1 to a clear-pending bit clears the pending status of the corresponding peripheral interrupt. Reading a bit identifies whether the interrupt is pending.
Page 314 ADSP-SC58x GICDST Register Descriptions Software Generated Interrupt Pending Set Register GICDST_SGI_PND_SET register provides a set-pending bit for each interrupt supported by the GIC. VALUE (R) Software Generated Interrupt Set-Pending Figure 7-37: GICDST_SGI_PND_SET Register Diagram Table 7-38: GICDST_SGI_PND_SET Register Fields Bit No. Bit Name Description/Enumeration (Access)
Page 315 ADSP-SC58x GICDST Register Descriptions Software Generated Interrupt Security Register GICDST_SGI_SECURITY registers provide a status bit for each interrupt supported by the GIC. Each bit controls whether the corresponding interrupt is in Group 0 or Group 1. Typically, when used with a processor that implements the ARM Security Extensions, Group 0 interrupts are Secure interrupts, and Group 1 interrupts are Non-secure interrupts, VALUE (R/W)
Page 316 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Register GICDST_SPI[n] register contains bits that provide the status of the SPI[987:0] inputs. STAT[15:0] (R) Shared Peripheral Interrupt Status STAT[31:16] (R) Shared Peripheral Interrupt Status Figure 7-39: GICDST_SPI[n] Register Diagram Table 7-40: GICDST_SPI[n] Register Fields Bit No.
Page 317 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Active Register GICDST_SPI_ACTIVE[n] register provides an active bit for each interrupt supported by the GIC. VALUE[15:0] (R/W) Active Bits VALUE[31:16] (R/W) Active Bits Figure 7-40: GICDST_SPI_ACTIVE[n] Register Diagram Table 7-41: GICDST_SPI_ACTIVE[n] Register Fields Bit No.
Page 318 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Configuration Register GICDST_SPI_CFG[n] register provides a 2-bit Int_config field for each interrupt supported by the GIC. VALUE[15:0] (R/W) Shared Peripheral Interrupt Configuration VALUE[31:16] (R/W) Shared Peripheral Interrupt Configuration Figure 7-41: GICDST_SPI_CFG[n] Register Diagram Table 7-42: GICDST_SPI_CFG[n] Register Fields Bit No.
Page 319 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Enable Clear Register GICDST_SPI_EN_CLR[n] register provides a clear-enable bit for each interrupt supported by the GIC. VALUE[15:0] (R/W) Shared Peripheral Interrupt Enable Clear Enable VALUE[31:16] (R/W) Shared Peripheral Interrupt Enable Clear Enable Figure 7-42: GICDST_SPI_EN_CLR[n] Register Diagram Table 7-43: GICDST_SPI_EN_CLR[n] Register Fields Bit No.
Page 320 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Enable Set Register GICDST_SPI_EN_SET[n] register provides a set-enable bit for each interrupt supported by the GIC. VALUE[15:0] (R/W) Shared Peripheral Interrupt Enable VALUE[31:16] (R/W) Shared Peripheral Interrupt Enable Figure 7-43: GICDST_SPI_EN_SET[n] Register Diagram Table 7-44: GICDST_SPI_EN_SET[n] Register Fields Bit No.
Page 321 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Pending Clear Register GICDST_SPI_PND_CLR[n] register provides a clear-pending bit for each interrupt supported by the GIC. VALUE[15:0] (R/W) Clear Pending Interrupt VALUE[31:16] (R/W) Clear Pending Interrupt Figure 7-44: GICDST_SPI_PND_CLR[n] Register Diagram Table 7-45: GICDST_SPI_PND_CLR[n] Register Fields Bit No.
Page 322 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Pending Set Register GICDST_SPI_PND_SET[n] register provides a set-pending bit for each interrupt supported by the GIC. VALUE[15:0] (R/W) Set Pending Interrupt VALUE[31:16] (R/W) Set Pending Interrupt Figure 7-45: GICDST_SPI_PND_SET[n] Register Diagram Table 7-46: GICDST_SPI_PND_SET[n] Register Fields Bit No.
Page 323 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Security Register GICDST_SPI_SECURITY[n] register provides a security status bit for each interrupt supported by the GIC. VALUE[15:0] (R/W) Shared Peripheral Interrupt Security Interrupt Security VALUE[31:16] (R/W) Shared Peripheral Interrupt Security Interrupt Security Figure 7-46: GICDST_SPI_SECURITY[n] Register Diagram Table 7-47: GICDST_SPI_SECURITY[n] Register Fields Bit No.
Page 324 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Processor Targets Register GICDST_SPI_TRGT[n] register provides an 8-bit CPU targets field for each interrupt supported by the GIC. VALUE (R/W) Shared Peripheral Interrupt Processor Targets Figure 7-47: GICDST_SPI_TRGT[n] Register Diagram Table 7-48: GICDST_SPI_TRGT[n] Register Fields Bit No.
Page 325 ADSP-SC58x GICCPU Register Descriptions Aliased Binary Point Register (ICCABPR) GICCPU_BIN_PT_ALIAS register Provides an alias for the non secure GICCPU_BIN_PT register. VALUE[15:0] (R/W) Aliased Priority Value VALUE[31:16] (R/W) Aliased Priority Value Figure 7-48: GICCPU_BIN_PT_ALIAS Register Diagram Table 7-50: GICCPU_BIN_PT_ALIAS Register Fields Bit No.
Page 326 ADSP-SC58x GICCPU Register Descriptions Binary Point Register (ICCBPR) GICCPU_BIN_PT register defines the point at which the priority value fields split into two parts, the group priority field and the sub-priority field. The group priority field is used to determine interrupt preemption. VALUE[15:0] (R/W) Binary Point Value VALUE[31:16] (R/W)
Page 327 ADSP-SC58x GICCPU Register Descriptions CPU Interface Control Register (ICCICR) GICCPU_CTL register enables the signaling of interrupts to the target processors. In a GIC that implements the Security Extensions, provides additional global controls for handling Secure interrupts. VALUE[15:0] (R/W) Control N VALUE[31:16] (R/W) Control N Figure 7-50: GICCPU_CTL Register Diagram...
Page 328 ADSP-SC58x GICCPU Register Descriptions End of Interrupt Register (ICCEOIR) A processor writes to the GICCPU_EOI register to inform the CPU interface that it has completed its interrupt service routine for the specified interrupt. VALUE[15:0] (R/W) End of Interrupt VALUE[31:16] (R/W) End of Interrupt Figure 7-51: GICCPU_EOI Register Diagram Table 7-53: GICCPU_EOI Register Fields...
Page 329 ADSP-SC58x GICCPU Register Descriptions Highest Pending Interrupt Register (ICCHPIR) GICCPU_PND_HI register indicates the Interrupt ID, and processor ID if appropriate, of the pending inter- rupt with the highest priority on the CPU interface. VALUE[15:0] (R) Hi Pend N VALUE[31:16] (R) Hi Pend N Figure 7-52: GICCPU_PND_HI Register Diagram Table 7-54: GICCPU_PND_HI Register Fields...
Page 330 ADSP-SC58x GICCPU Register Descriptions Interrupt Acknowledge Register (ICCIAR) The processor reads the GICCPU_INT_ACK register to obtain the interrupt ID of the signaled interrupt. This read acts as an acknowledge for the interrupt. VALUE[15:0] (RC) Interrupt Acknowledge ID VALUE[31:16] (RC) Interrupt Acknowledge ID Figure 7-53: GICCPU_INT_ACK Register Diagram Table 7-55: GICCPU_INT_ACK Register Fields Bit No.
Page 331 ADSP-SC58x GICCPU Register Descriptions Priority Mask Register (ICCIPMR) GICCPU_PRIO_MSK register provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signaled to the processor. VALUE[15:0] (R/W) Interrupt Priority Filter Value VALUE[31:16] (R/W) Interrupt Priority Filter Value Figure 7-54: GICCPU_PRIO_MSK Register Diagram Table 7-56: GICCPU_PRIO_MSK Register Fields...
Page 332 ADSP-SC58x GICCPU Register Descriptions Running Priority Register (ICCRPR) GICCPU_RUN_PRIO register indicates the priority of the highest priority interrupt that is active on the CPU interface. VALUE[15:0] (R) Run Priority N VALUE[31:16] (R) Run Priority N Figure 7-55: GICCPU_RUN_PRIO Register Diagram Table 7-57: GICCPU_RUN_PRIO Register Fields Bit No.
Page 333 ADSP-SC58x GICDST Register Descriptions Table 7-58: ADSP-SC58x GICDST Register List (Continued) Name Description GICDST_SGI_PND_SET Software Generated Interrupt Pending Set Register GICDST_SGI_SECURITY Software Generated Interrupt Security Register GICDST_SPI[n] Shared Peripheral Interrupt Register GICDST_SPI_ACTIVE[n] Shared Peripheral Interrupt Active Register GICDST_SPI_CFG[n] Shared Peripheral Interrupt Configuration Register GICDST_SPI_EN_CLR[n] Shared Peripheral Interrupt Enable Clear Register GICDST_SPI_EN_SET[n]...
Page 334 ADSP-SC58x GICDST Register Descriptions GIC Port 0 Enable register enables global monitoring of the peripheral interrupt signals and forwarding pending in- GICDST_EN terrupts to the CPU interfaces. VALUE (R/W) Global Interrupt Monitor Enable Figure 7-56: GICDST_EN Register Diagram Table 7-59: GICDST_EN Register Fields Bit No.
Page 335 ADSP-SC58x GICDST Register Descriptions Software Generated Interrupt Priority Register register provides the 8-bit priority field for each interrupt supported by the GIC. GICDST_SGI_PRIO[n] This field stores the priority of the corresponding interrupt. VALUE (R/W) Software Generated Interrupt Priority Figure 7-57: GICDST_SGI_PRIO[n] Register Diagram Table 7-60: GICDST_SGI_PRIO[n] Register Fields Bit No.
Page 336 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Priority Register registers provide an 8-bit priority field for each interrupt supported by the GIC. GICDST_SPI_PRIO[n] This field stores the priority of the corresponding interrupt. VALUE (R/W) Priority Figure 7-58: GICDST_SPI_PRIO[n] Register Diagram Table 7-61: GICDST_SPI_PRIO[n] Register Fields Bit No.
Page 337 ADSP-SC58x GICDST Register Descriptions Software Generated Interrupt Active Register registers provide a Set-active bit for each interrupt that the GIC supports. Writing to GICDST_SGI_ACTIVE a Set-active bit Activates the corresponding interrupt. These registers are used when preserving and restoring GIC state.
Page 338 ADSP-SC58x GICDST Register Descriptions Software Generated Interrupt Control Register register controls the generation of SGIs.It is implementation defined whether this register GICDST_SGI_CTL has any effect when the forwarding of interrupts by Distributor is disabled by the GICD_CTLR settings. SATT (R/W) SGIINTID (R/W) Security Value of the SGI The Interrupt ID of the SGI...
Page 339 ADSP-SC58x GICDST Register Descriptions Table 7-63: GICDST_SGI_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) SATT Security Value of the SGI. (R/W) The GICDST_SGI_CTL.SATT bit is implemented only if the GIC includes the Se- curity Extensions. This field is writable only by a Secure access. Any Non-secure write to the GICD_SGIR generates an SGI only if the specified SGI is programmed as Group 1, regardless of the value of bit[15] of the write.
Page 340 ADSP-SC58x GICDST Register Descriptions Software Generated Interrupt Clear-Pending Register register provides a clear pending bit for each interrupt supported by the GIC. GICDST_SGI_PND_CLR Writing 1 to a clear-pending bit clears the pending status of the corresponding peripheral interrupt. Reading a bit identifies whether the interrupt is pending.
Page 341 ADSP-SC58x GICDST Register Descriptions Software Generated Interrupt Pending Set Register register provides a set-pending bit for each interrupt supported by the GIC. GICDST_SGI_PND_SET VALUE (R) Software Generated Interrupt Set-Pending Figure 7-62: GICDST_SGI_PND_SET Register Diagram Table 7-65: GICDST_SGI_PND_SET Register Fields Bit No. Bit Name Description/Enumeration (Access)
Page 342 ADSP-SC58x GICDST Register Descriptions Software Generated Interrupt Security Register registers provide a status bit for each interrupt supported by the GIC. Each bit GICDST_SGI_SECURITY controls whether the corresponding interrupt is in Group 0 or Group 1. Typically, when used with a processor that implements the ARM Security Extensions, Group 0 interrupts are Secure interrupts, and Group 1 interrupts are Non-secure interrupts, VALUE (R/W)
Page 343 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Register register contains bits that provide the status of the SPI[987:0] inputs. GICDST_SPI[n] STAT[15:0] (R) Shared Peripheral Interrupt Status STAT[31:16] (R) Shared Peripheral Interrupt Status Figure 7-64: GICDST_SPI[n] Register Diagram Table 7-67: GICDST_SPI[n] Register Fields Bit No.
Page 344 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Active Register register provides an active bit for each interrupt supported by the GIC. GICDST_SPI_ACTIVE[n] VALUE[15:0] (R/W) Active Bits VALUE[31:16] (R/W) Active Bits Figure 7-65: GICDST_SPI_ACTIVE[n] Register Diagram Table 7-68: GICDST_SPI_ACTIVE[n] Register Fields Bit No.
Page 345 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Configuration Register register provides a 2-bit Int_config field for each interrupt supported by the GIC. GICDST_SPI_CFG[n] VALUE[15:0] (R/W) Shared Peripheral Interrupt Configuration VALUE[31:16] (R/W) Shared Peripheral Interrupt Configuration Figure 7-66: GICDST_SPI_CFG[n] Register Diagram Table 7-69: GICDST_SPI_CFG[n] Register Fields Bit No.
Page 346 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Enable Clear Register register provides a clear-enable bit for each interrupt supported by the GIC. GICDST_SPI_EN_CLR[n] VALUE[15:0] (R/W) Shared Peripheral Interrupt Enable Clear Enable VALUE[31:16] (R/W) Shared Peripheral Interrupt Enable Clear Enable Figure 7-67: GICDST_SPI_EN_CLR[n] Register Diagram Table 7-70: GICDST_SPI_EN_CLR[n] Register Fields Bit No.
Page 347 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Enable Set Register register provides a set-enable bit for each interrupt supported by the GIC. GICDST_SPI_EN_SET[n] VALUE[15:0] (R/W) Shared Peripheral Interrupt Enable VALUE[31:16] (R/W) Shared Peripheral Interrupt Enable Figure 7-68: GICDST_SPI_EN_SET[n] Register Diagram Table 7-71: GICDST_SPI_EN_SET[n] Register Fields Bit No.
Page 348 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Pending Clear Register register provides a clear-pending bit for each interrupt supported by the GIC. GICDST_SPI_PND_CLR[n] VALUE[15:0] (R/W) Clear Pending Interrupt VALUE[31:16] (R/W) Clear Pending Interrupt Figure 7-69: GICDST_SPI_PND_CLR[n] Register Diagram Table 7-72: GICDST_SPI_PND_CLR[n] Register Fields Bit No.
Page 349 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Pending Set Register register provides a set-pending bit for each interrupt supported by the GIC. GICDST_SPI_PND_SET[n] VALUE[15:0] (R/W) Set Pending Interrupt VALUE[31:16] (R/W) Set Pending Interrupt Figure 7-70: GICDST_SPI_PND_SET[n] Register Diagram Table 7-73: GICDST_SPI_PND_SET[n] Register Fields Bit No.
Page 350 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Security Register register provides a security status bit for each interrupt supported by the GICDST_SPI_SECURITY[n] GIC. VALUE[15:0] (R/W) Shared Peripheral Interrupt Security Interrupt Security VALUE[31:16] (R/W) Shared Peripheral Interrupt Security Interrupt Security Figure 7-71: GICDST_SPI_SECURITY[n] Register Diagram Table 7-74: GICDST_SPI_SECURITY[n] Register Fields Bit No.
Page 351 ADSP-SC58x GICDST Register Descriptions Shared Peripheral Interrupt Processor Targets Register register provides an 8-bit CPU targets field for each interrupt supported by the GICDST_SPI_TRGT[n] GIC. VALUE (R/W) Shared Peripheral Interrupt Processor Targets Figure 7-72: GICDST_SPI_TRGT[n] Register Diagram Table 7-75: GICDST_SPI_TRGT[n] Register Fields Bit No.
Page 352 Trigger Routing Unit (TRU) 8 Trigger Routing Unit (TRU) The TRU provides system-level sequence control without core intervention. The TRU maps trigger masters (genera- tors of triggers) to trigger slaves (receivers of triggers). Slave endpoints can be configured to respond to triggers in various ways.
Page 353 TRU Functional Description ADSP-SC58x TRU Register List The Trigger Routing Unit (TRU) provides simple sequence control of distributed modules without the penalties associated with core intervention (for example, interrupt overhead). The TRU receives trigger inputs from all master trigger inputs (MTI) and the TRU master trigger register (TRU_MTR). Based on these inputs, the TRU logic gener- ates trigger outputs that initiate slave operations in the processor core and peripherals.
Page 354 TRU Functional Description ADSP-SC58x Trigger List Table 8-3: ADSP-SC58x Trigger List Masters Trigger ID Name Description Sensitivity RESERVED_TRIG0 NC_RES0 CGU0 Event Edge CGU0_EVT CGU1_EVT CGU1 Event Edge C0_SNDEVT Core0 Send Event Core0 Wait For Interrupt C0_WFI C0_WFE Core0 Wait For Event TIMER0_TMR0_MST TIMER0 Timer 0 Edge...
Page 355 TRU Functional Description Table 8-3: ADSP-SC58x Trigger List Masters (Continued) Trigger ID Name Description Sensitivity SPORT3 Channel A DMA Edge SPORT3_A_DMA SPORT3_B_DMA SPORT3 Channel B DMA Edge SPORT4_A_DMA SPORT4 Channel A DMA Edge SPORT4 Channel B DMA Edge SPORT4_B_DMA SPORT5_A_DMA SPORT5 Channel A DMA Edge SPORT5_B_DMA...
Page 356 TRU Functional Description Table 8-3: ADSP-SC58x Trigger List Masters (Continued) Trigger ID Name Description Sensitivity IIR0 DMA Edge IIR0_DMA EPPI0_CH0_DMA EPPI0 Channel 0 DMA Edge EPPI0_CH1_DMA EPPI0 Channel 1 DMA Edge LP0 DMA Channel LP0_DMA LP1_DMA LP1 DMA Channel UART0_TXDMA UART0 Transmit DMA Edge UART0 Receive DMA...
Page 357 TRU Functional Description Table 8-3: ADSP-SC58x Trigger List Masters (Continued) Trigger ID Name Description Sensitivity CTI3 SYSCTI (CTI3) System Halt Slave 5 Edge CTI3_MST5 CTI3_MST6 CTI3 SYSCTI (CTI3) System Halt Slave 6 Edge CTI3_MST7 CTI3 SYSCTI (CTI3) System Halt Slave 7 Edge SEC0 Fault Edge...
Page 358 TRU Functional Description Table 8-3: ADSP-SC58x Trigger List Masters (Continued) Trigger ID Name Description Sensitivity SWU6 Debug Edge SWU6_DBG SWU5_DBG SWU5 Debug Edge SWU7_DBG SWU7 Debug Edge SWU8 Debug Edge SWU8_DBG SWU9_DBG SWU9 Debug Edge SWU10_DBG SWU10 Debug Edge SWU11 Debug Edge SWU11_DBG SWU12_DBG...
Page 359 TRU Functional Description Table 8-4: ADSP-SC58x Trigger List Slaves (Continued) Trigger ID Name Description Sensitivity PWM0 Trip Trigger Slave 1 Pulse PWM0_TRIP_TRIG1 PWM0_TRIP_TRIG2 PWM0 Trip Trigger Slave 2 Pulse PWM1_TRIP_TRIG0 PWM1 Trip Trigger Slave 0 Pulse PWM1 Trip Trigger Slave 1 Pulse PWM1_TRIP_TRIG1 PWM1_TRIP_TRIG2...
Page 360 TRU Functional Description Table 8-4: ADSP-SC58x Trigger List Slaves (Continued) Trigger ID Name Description Sensitivity HAE0 RX DMA Channel 1 Pulse HAE0_RXDMA_CH1 HAE0_TXDMA HAE0 TX DMA Channel 0 Pulse SINC0_SYNC0 SINC0 Synchronization Input 0 Pulse SINC0 Synchronization Input 1 Pulse SINC0_SYNC1 FFTA0_TXDMA FFTA0 Transmit DMA...
Page 361 TRU Functional Description Table 8-4: ADSP-SC58x Trigger List Slaves (Continued) Trigger ID Name Description Sensitivity STM0 Event 19 Pulse STM0_EVT19 STM0_EVT20 STM0 Event 20 Pulse STM0_EVT21 STM0 Event 21 Pulse STM0 Event 22 Pulse STM0_EVT22 STM0_EVT23 STM0 Event 23 Pulse STM0_EVT24 STM0 Event 24 Pulse...
Page 362 TRU Functional Description Table 8-4: ADSP-SC58x Trigger List Slaves (Continued) Trigger ID Name Description Sensitivity Standard BW MDMA Channel 0 Source (CRC Pulse MDMA0_SRC MDMA0_DST Standard BW MDMA Channel 0 Destination Pulse (CRC OUT) MDMA1_SRC Standard BW MDMA Channel 1 Source (CRC Pulse MDMA1_DST Standard BW MDMA Channel 1 Destination...
Page 363 TRU Functional Description Table 8-4: ADSP-SC58x Trigger List Slaves (Continued) Trigger ID Name Description Sensitivity SWU11 Enable Pulse SWU11_EN SWU12_EN SWU12 Enable Pulse SWU13_EN SWU13 Enable Pulse SWU14 Enable Pulse SWU14_EN SWU15_EN SWU15 Enable Pulse ACM0_TRIG2 ACM0 Trigger Input 2 Pulse ACM0 Trigger Input 3 Pulse...
Page 364 TRU Architectural Concepts TRU Architectural Concepts The TRU supports a simple trigger-in/trigger-out model for modules that comply with the triggering functional model. The TRU is the controller of the trigger system. Trigger outputs from trigger masters are mapped to trigger inputs of trigger slaves through a set of programmable registers (TRU_SSR[n]).
Page 365 TRU Programming Model Programming Examples The following examples shows the steps to create a single trigger and a Timer period expiry event automatically tog- gling a GPIO. Configuring a Simple Trigger Sequence The following example shows the steps to create a simple trigger. 1.
Page 366 ADSP-SC58x TRU Register Descriptions Table 8-5: ADSP-SC58x TRU Register List Name Description TRU_ERRADDR Error Address Register TRU_GCTL Global Control Register TRU_MTR Master Trigger Register TRU_SSR[n] Slave Select Register TRU_STAT Status Information Register ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference 8–15...
Page 367 ADSP-SC58x TRU Register Descriptions Error Address Register The TRU error address register (TRU_ERRADDR) holds the address from the memory-mapped register access gen- erating an access error of TRU registers. ADDR (R/W) Error Address Figure 8-2: TRU_ERRADDR Register Diagram Table 8-6: TRU_ERRADDR Register Fields Bit No.
Page 368 ADSP-SC58x TRU Register Descriptions Global Control Register The TRU global control register (TRU_GCTL) provides register locking, TRU reset, and TRU enable. MTRL (R/W) EN (R/W) MTR Lock Bit Non-MMR Enable RESET (R/W) Soft Reset LOCK (R/W) GCTL Lock Bit Figure 8-3: TRU_GCTL Register Diagram Table 8-7: TRU_GCTL Register Fields Bit No.
Page 369 ADSP-SC58x TRU Register Descriptions Table 8-7: TRU_GCTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Non-MMR Enable. (R/W) The TRU_GCTL.EN bit is read/write and must be set for the TRU to propagate trig- ger events. All TRU register read/write operations continue to operate independent of the TRU_GCTL.EN bit.
Page 370 ADSP-SC58x TRU Register Descriptions Master Trigger Register The TRU master trigger register (TRU_MTR) permits trigger generation through software by writing a trigger mas- ter ID value to one of the four fields in the TRU_MTR register. If the global lock is enabled (SPU_CTL.GLCK bit =1) and the TRU_GCTL.LOCK bit is set, the TRU_MTR register is read only.
Page 371 ADSP-SC58x TRU Register Descriptions Slave Select Register The TRU slave select registers (TRU_SSR[n]) each provide slave selection and register locking. SSR (R/W) SSRn Slave Select LOCK (R/W) SSRn Lock Figure 8-5: TRU_SSR[n] Register Diagram Table 8-9: TRU_SSR[n] Register Fields Bit No. Bit Name Description/Enumeration (Access)
Page 372 ADSP-SC58x TRU Register Descriptions Status Information Register The TRU status register (TRU_STAT) contains the status of register writes and sta- TRU_MTR TRU_SSR[n] tus of bus read/write errors. ADDRERR (R/W1C) LWERR (R/W1C) Address Error Status Lock Write Error Status Figure 8-6: TRU_STAT Register Diagram Table 8-10: TRU_STAT Register Fields Bit No.
Page 373 L2 System Memory 9 L2 System Memory L2 system memories have significant bandwidth for core accesses, but it is important to note that L2 responds slow- er to core accesses than L1 memories. L2 SRAM is the ideal storage for multiple processor cores to share data and instruction resources, such as semaphores, shared buffers, and code libraries.
Page 374 L2 System Memory Functional Description The following sections provide a functional description of the L2 system memory. ADSP-SC58x L2CTL Interrupt List Table 9-1: ADSP-SC58x L2CTL Interrupt List Interrupt Name Description Sensitivity Channel L2CTL0_ECC_ERR L2CTL0 ECC Error Level ADSP-SC58x L2CTL Register List The L2 memory controller (L2CTL) includes the controls to manage each L2 memory bank independently.
Page 375 L2 System Memory Functional Description ARM and eight banks of L2 RAM containing 32 Kbytes each. ARM's 0x00000000 location (reset ISR) is mapped to this block. The L2CTL1 block contains one bank of boot ROM for SHARC+ ID = 1 and eight banks of applica- tion ROM.
Page 376 L2 System Memory Architectural Concepts burst access to an ECC-enabled bank creates an extra latency of two SYSCLK_0 cycles. No extra latency is seen if the ECC is disabled. NOTE: Continuous 8/16-bit core access to an ECC-enabled L2 bank is not recommended from a throughput per- spective.
Page 377 L2 System Memory Architectural Concepts The Fixed Priority table shows the priority for fixed priority mode (with urgent priority disabled) for each SCB channel. If two cores (or the 64-bit Max BW DMA) simultaneously try to access L2 for the same instance (both read or both write), even to different banks, software allows only one master access at a time.
Page 378 L2 System Memory Architectural Concepts Table 9-4: Fixed Priority With Priority Elevation Channel Priority Level L2 Refresh Request 9 (highest) Port 0 Read Channel Urgent Request Port 0 Write Channel Urgent Request Port 1 Read Channel Urgent Request Port 1 Write Channel Urgent Request Port 0 Read Channel Normal Request Port 0 Write Channel Normal Request Port 1 Read Channel Normal Request...
Page 379 Data Integrity BIT POSITION ENCODED DATA BITS PARITY COVERAGE BIT POSITION ENCODED DATA BITS PARITY COVERAGE BIT POSITION ENCODED DATA BITS PARITY COVERAGE Figure 9-3: Hsaio Parity Bit Mapping During read operation, the parity bits become part of the syndrome equation. The new syndrome bits are now the XOR values of the 13 or 14 data bits plus the respective stored parity bit.
Page 380 Data Integrity Syndrome Syndromes not equal 0x00 Uncorrectable Syndromes having error an odd number of 1’s Syndrome: 0x07, 0x70, 0x73, 0x75, 0x76, 0x79, 0x7A, 0x7C, 0x7F One bit error Syndrome: 0x07, 0x1F, 0x2F, 0x37, 0x4F, 0x57, 0x67, 0x7F Syndrome: 0x68, 0x6E, 0x6D, 0x6B, Multi-bit error 0x79, 0x7A, 0x7C, 0x7F >1-bit error...
Page 381 Data Integrity 3. Execute SYNC instruction. 4. Set L2CTL_CTL.ECCMAP7-L2CTL_CTL.ECCMAP0 bits of interest. 5. Execute SYNC instruction. 6. Write checksum values using 32-bit store instructions. 7. If data cache enabled, make sure that it flushes out checksum values. 8. Execute SYNC instruction. 9.
Page 382 L2 System Memory Event Control • Applies an ECC algorithm to the two 32-bit words • Writes the corrected data back to memory While the atomic refresh operation is ongoing, other accesses to the same SRAM bank are locked-out. The L2CTL_STAT.RFRS status bit signals an ongoing refresh operation.
Page 383 ADSP-SC58x L2CTL Register Descriptions Table 9-5: ADSP-SC58x L2CTL Register List (Continued) Name Description L2CTL_ERRADDR1 ECC Error Address 1 Register L2CTL_ERRADDR2 ECC Error Address 2 Register L2CTL_ERRADDR3 ECC Error Address 3 Register L2CTL_ERRADDR4 ECC Error Address 4 Register L2CTL_ERRADDR5 ECC Error Address 5 Register L2CTL_ERRADDR6 ECC Error Address 6 Register L2CTL_ERRADDR7...
Page 384 ADSP-SC58x L2CTL Register Descriptions Control Register register includes a write protection bit, enables L2 banks, and selects mapping of banks (as ECC L2CTL_CTL RAM or data RAM). ECCMAP7 (R/W) BK0EDIS (R/W) ECC Map Bank 7 Bank 0 ECC Disable ECCMAP6 (R/W) BK1EDIS (R/W) ECC Map Bank 6 Bank 1 ECC Disable...
Page 385 ADSP-SC58x L2CTL Register Descriptions Table 9-6: L2CTL_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ECCMAP7 ECC Map Bank 7. (R/W) The L2CTL_CTL.ECCMAP7 bit selects whether L2 bank 7 addresses ECC RAM or data RAM. 0 Data RAM 1 ECC RAM ECCMAP6 ECC Map Bank 6.
Page 386 ADSP-SC58x L2CTL Register Descriptions Table 9-6: L2CTL_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ECCMAP1 ECC Map Bank 1. (R/W) The L2CTL_CTL.ECCMAP1 bit selects whether L2 bank 1 addresses ECC RAM or data RAM. 0 Data RAM 1 ECC RAM ECCMAP0 ECC Map Bank 0.
Page 387 ADSP-SC58x L2CTL Register Descriptions Table 9-6: L2CTL_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) BK2EDIS Bank 2 ECC Disable. (R/W) The L2CTL_CTL.BK2EDIS bit disables L2 bank 2 ECC operation. 0 Enable ECC 1 Disable ECC BK1EDIS Bank 1 ECC Disable. (R/W) The L2CTL_CTL.BK1EDIS bit disables L2 bank 1 ECC operation.
Page 388 ADSP-SC58x L2CTL Register Descriptions Error Type 0 Address Register register holds the address that created an access error on the L2 port 0 bus interface (cores). L2CTL_EADDR0 This register is be updated only if the corresponding error status bit (L2CTL_STAT.ERR0) is cleared. After the status bit is set for an error, further errors do not update the L2CTL_EADDR0 register until a W1C clears the corre-...
Page 389 ADSP-SC58x L2CTL Register Descriptions Error Type 1 Address Register register holds the address that created an access error on the L2 port 1 bus interface (DMA). L2CTL_EADDR1 This register is be updated only if the corresponding error status bit (L2CTL_STAT.ERR1) is cleared. After the status bit is set for an error, further errors do not update the L2CTL_EADDR1 register until a W1C clears the corre-...
Page 390 ADSP-SC58x L2CTL Register Descriptions ECC Error Address 0 Register register holds the address containing an ECC multi-bit error for the corresponding bank. L2CTL_ERRADDR0 The L2CTL updates this register only if the bank’s status bit (L2CTL_STAT.ECCERR0) is cleared. After the bank’s status bit is set for an error, further errors in the same bank are not detected until a W1C clears the status bit. VALUE[15:0] (R) ERRADDR Value VALUE[31:16] (R)
Page 391 ADSP-SC58x L2CTL Register Descriptions ECC Error Address 1 Register register holds the address containing an ECC multi-bit error for the corresponding bank. L2CTL_ERRADDR1 The L2CTL updates this register only if the bank’s status bit (L2CTL_STAT.ECCERR1) is cleared. After the bank’s status bit is set for an error, further errors in the same bank are not detected until a W1C clears the status bit. VALUE[15:0] (R) ERRADDR Value VALUE[31:16] (R)
Page 392 ADSP-SC58x L2CTL Register Descriptions ECC Error Address 2 Register register holds the address containing an ECC multi-bit error for the corresponding bank. L2CTL_ERRADDR2 The L2CTL updates this register only if the bank’s status bit (L2CTL_STAT.ECCERR2) is cleared. After the bank’s status bit is set for an error, further errors in the same bank are not detected until a W1C clears the status bit. VALUE[15:0] (R) ERRADDR Value VALUE[31:16] (R)
Page 393 ADSP-SC58x L2CTL Register Descriptions ECC Error Address 3 Register register holds the address containing an ECC multi-bit error for the corresponding bank. L2CTL_ERRADDR3 The L2CTL updates this register only if the bank’s status bit (L2CTL_STAT.ECCERR3) is cleared. After the bank’s status bit is set for an error, further errors in the same bank are not detected until a W1C clears the status bit. VALUE[15:0] (R) ERRADDR Value VALUE[31:16] (R)
Page 394 ADSP-SC58x L2CTL Register Descriptions ECC Error Address 4 Register register holds the address containing an ECC multi-bit error for the corresponding bank. L2CTL_ERRADDR4 The L2CTL updates this register only if the bank’s status bit (L2CTL_STAT.ECCERR4) is cleared. After the bank’s status bit is set for an error, further errors in the same bank are not detected until a W1C clears the status bit. VALUE[15:0] (R) ERRADDR Value VALUE[31:16] (R)
Page 395 ADSP-SC58x L2CTL Register Descriptions ECC Error Address 5 Register register holds the address containing an ECC multi-bit error for the corresponding bank. L2CTL_ERRADDR5 The L2CTL updates this register only if the bank’s status bit (L2CTL_STAT.ECCERR5) is cleared. After the bank’s status bit is set for an error, further errors in the same bank are not detected until a W1C clears the status bit. VALUE[15:0] (R) ERRADDR Value VALUE[31:16] (R)
Page 396 ADSP-SC58x L2CTL Register Descriptions ECC Error Address 6 Register register holds the address containing an ECC multi-bit error for the corresponding bank. L2CTL_ERRADDR6 The L2CTL updates this register only if the bank’s status bit (L2CTL_STAT.ECCERR6) is cleared. After the bank’s status bit is set for an error, further errors in the same bank are not detected until a W1C clears the status bit. VALUE[15:0] (R) ERRADDR Value VALUE[31:16] (R)
Page 397 ADSP-SC58x L2CTL Register Descriptions ECC Error Address 7 Register register holds the address containing an ECC multi-bit error for the corresponding bank. L2CTL_ERRADDR7 The L2CTL updates this register only if the bank’s status bit (L2CTL_STAT.ECCERR7) is cleared. After the bank’s status bit is set for an error, further errors in the same bank are not detected until a W1C clears the status bit. VALUE[15:0] (R) ERRADDR Value VALUE[31:16] (R)
Page 398 ADSP-SC58x L2CTL Register Descriptions Error Type 0 Register register holds information about the error transaction that has occurred on the bus for the corre- L2CTL_ET0 sponding L2 bus port 0 (cores). This register is updated only if the corresponding error status bit L2CTL_STAT.ERR0 is cleared.
Page 399 ADSP-SC58x L2CTL Register Descriptions Table 9-17: L2CTL_ET0 Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ROMERR ROM Error. (R/NW) The L2CTL_ET0.ROMERR bit indicates whether a write access went to a ROM area. ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference 9–27...
Page 400 ADSP-SC58x L2CTL Register Descriptions Error Type 1 Register register holds information about the error transaction that has occurred on the bus for the corre- L2CTL_ET1 sponding L2 bus port 1 (DMA). This register is updated only if the corresponding error status bit L2CTL_STAT.ERR1 is cleared.
Page 401 ADSP-SC58x L2CTL Register Descriptions Refresh Address Register register stores the refresh address value. When this register is written, L2 initiates an atomic read- L2CTL_RFA write operation to the address value written into the register. This is a read/write register, but a new value in the corresponding field has to be written only when there are no outstanding refresh request pending (L2CTL_STAT.RFRS =0).
Page 402 ADSP-SC58x L2CTL Register Descriptions Read Priority Count Register register stores the count value to be used for priority elevation for bus read channels. If a bus L2CTL_RPCR channel is not granted access from the bank arbiter, the channel waits for the programmed number of SYSCLK_0 cycles, before the request is elevated to a high priority request.
Page 403 ADSP-SC58x L2CTL Register Descriptions Status Register register indicates ECC error status, refresh register status, and bus error status. L2CTL_STAT ECCERR7 (R/W1C) ERR0 (R/W1C) ECC Error Bank 7 Error Port 0 ECCERR6 (R/W1C) ERR1 (R/W1C) ECC Error Bank 6 Error Port 1 ECCERR5 (R/W1C) RFRS (R) ECC Error Bank 5...
Page 404 ADSP-SC58x L2CTL Register Descriptions Table 9-21: L2CTL_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ECCERR4 ECC Error Bank 4. (R/W1C) The L2CTL_STAT.ECCERR4 bit indicates that an ECC double-bit error occurred inside L2 bank 4. 0 No Status 1 ECC Double Bit Error ECCERR3 ECC Error Bank 3.
Page 405 ADSP-SC58x L2CTL Register Descriptions Table 9-21: L2CTL_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ERR1 Error Port 1. (R/W1C) The L2CTL_STAT.ERR1 indicates whether the L2CTL has detected a bus access er- ror on L2s bus port 1. 0 No Error 1 Bus Access Error ERR0 Error Port 0.
Page 406 ADSP-SC58x L2CTL Register Descriptions Write Priority Count Register register stores the count value to be used for priority elevation for bus write channels. If a bus L2CTL_WPCR channel is not granted access from the bank arbiter, the channel waits for the programmed number of SYSCLK_0 cycles, before the request is elevated to a high priority request.
Page 407 Dynamic Memory Controller (DMC) 10 Dynamic Memory Controller (DMC) The dynamic memory controller (DMC) provides a glueless interface between DDR3/DDR2/LPDDR SDRAMs and the system crossbar interface (SCB). The DMC enables execution of instructions from, as well as transfer of data to and from, DDR3, DDR2 SDRAM or LPDDR SDRAM respectively. NOTE: The terms DDR2, DDR3, and LPDDR SDRAM are referred to generically as DDR SDRAM in the rest of this chapter unless otherwise noted.
Page 408 DMC Features • Provides page hit detection that supports multiple column accesses to the same row • User-specified active, precharge, and refresh commands. • Programmable SDRAM access timing parameters • Enables automatic refresh generation with programmable refresh intervals • Self-refresh mode to reduce system power consumption •...
Page 409 DMC Features Feature Exclusions The DMC exclusions are as follows: For DDR2: • 4-bit and 8-bit wide DDR2 DRAM memories are not supported • OCD is not supported • Burst interleaved accesses are not supported • Single-ended signaling mode not supported For DDR3: •...
Page 410 DMC Functional Description Table 10-1: ADSP-SC58x DMC Register List Name Description DMC_CFG Configuration Register DMC_CPHY_CTL Controller to PHY Interface Register DMC_CTL Control Register DMC_DLLCTL DLL Control Register DMC_DT_CALIB_ADDR Data Calibration Address Register DMC_DT_DATA_CALIB_DATA0 Data Calibration Data 0 Register DMC_DT_DATA_CALIB_DATA1 Data Calibration Data 1 Register DMC_EFFCTL Efficiency Control Register DMC_EMR1...
Page 411 DMC Functional Description Table 10-2: ADSP-SC58x DMC Register List Name Description DMC_CAL_PADCTL0 Calibration PAD Control 0 Register DMC_CAL_PADCTL2 Calibration PAD Control 2 Register DMC_PHY_CTL0 PHY Control 0 Register DMC_PHY_CTL1 PHY Control 1 Register DMC_PHY_CTL2 PHY Control 2 Register DMC_PHY_CTL3 PHY Control 3 Register DMC_PHY_CTL4 PHY Control 4 Register Protocol Controller...
Page 412 Efficiency Controller transactions while scheduling. When the page-based scheduling of the buffered transactions is complete, same mas- ter transaction scheduling is triggered. If multiple transactions from a master are received, the efficiency controller schedules the transactions back-to-back. DMC Read Data Buffer The DMC read data buffer contains a data buffer and an address buffer.
Page 413 Efficiency Controller • If the DMC_PRIOMSK field is set to 0xFFFFFFFC, the SCB IDs 7234, 7235, 7236 and 7237 are given priori- • If two transactions with priority, one read and the other a write, are outstanding, the priority transaction that does not change the direction of the DMC access gets priority.
Page 414 System Crossbar Slave Interface auto-refresh. A delay can occur. The delay is a maximum of 64 clock cycles from the moment the write response is sent on the SCB to the write operation of the data into SDRAM. The system crossbar interface performs the following operations: •...
Page 415 Architectural Concepts Controller On Die Termination (ODT) The controller ODT is enabled with the granularity of a byte lane. The description of this feature can be obtained in the description of the corresponding PHY registers. Controller ODT involves extra overhead in terms of power con- sumption during reads.
Page 416 Architectural Concepts Table 10-3: DDR3 Bank Interleaving (Continued) SDRAM size Bank address bits Row address bits Column address bits 1 Gb 26:24 23:11 10:1 2 Gb 27:25 24:11 10:1 4 Gb 28:26 25:11 10:1 8 Gb 29:27 26:11 10:1 Page Interleaving The DDR3 Page Interleaving table shows DDR3 page interleaving.
Page 417 Architectural Concepts Table 10-6: DDR2 Page Interleaving SDRAM size Row address bits Bank address bits Column address bits 256 Mb 24:12 11:10 512 Mb 25:13 12:11 10:1 1 Gb 26:14 13:11 10:1 2 Gb 27:14 13:11 10:1 4 Gb 28:14 13:11 10.1 LPDDR SDRAM Organization...
Page 418 Architectural Concepts Table 10-8: LPDDR Page Interleaving (Continued) SDRAM size Row address bits Bank address bits Column address bits 2 Gb 27:14 13:11 10.1 DMC Clocking The DMC uses a divided-down version of the PLLCLK (PLL clock) to generate an internal clock for clocking the DMC block and interface.
Page 419 DMC Operating Modes DDR2 Mode This mode is the default mode of the DMC module and supports JESD79-2E compatible DDR2 SDRAM. In this mode, the DMC_CTL.DDR3EN bit =0, the DMC_CTL.LPDDR bit =0, and the DMC_PHY_CTL4.DDRMODE bit field is 0b'01. DDR3 Mode The DMC module supports JESD79-3E compatible double data rate DDR3 SDRAM.
Page 420 DMC Event Control The DMC can be brought out of self-refresh mode by clearing the DMC_CTL.SRREQ bit again. The controller clears the DMC_STAT.SRACK bit after the self-refresh operation completes. DMC Event Control The DMC has no related interrupt or trigger event information. DMC Programming Model The dynamic memory controller contains five groups of memory-mapped registers.
Page 421 DMC Programming Model Table 10-9: DDR2, DDR3, and LPDDR Programming (Continued) PHY/Control- Description Registers and Bit DDR3 DDR2 LPDDR Fields Involved DMC_CAL_ ODT and drive impe- The DMC supports The DMC supports The DMC does not PADCTL0, dance calibration ODT and drive impe- OCD calibration.
Page 422 DMC Programming Model Table 10-9: DDR2, DDR3, and LPDDR Programming (Continued) PHY/Control- Description Registers and Bit DDR3 DDR2 LPDDR Fields Involved Controller Configuring burst DMC_MR.BLEN (for The DMC only sup- The DMC supports The DMC supports length DDR2 and LPDDR), ports burst length of both burst length of 4 both burst length of 4...
Page 423 DMC Programming Model Table 10-9: DDR2, DDR3, and LPDDR Programming (Continued) PHY/Control- Description Registers and Bit DDR3 DDR2 LPDDR Fields Involved DDR3 memory device data sheets. DMC_DLLCTL Controller Configuring the Always configure the DMC_DLLCTL.DLLCALRDCNT field to 0x48 regis- DMC_DLLCTL and DMC_DLLCTL.DATACYC field to 0x9. PHY DLL Calibration The PHY DLL calibration is performed as part of the SDRAM power-up initialization.
Page 424 DMC Programming Model driver impedance Rtt and ODT values to match the trace impedance. The connection reduces impedance disconti- nuity and minimizes signal reflections. The command has two variants named as ZQ calibration long (ZQCL) and ZQ calibration short (ZQCS). The ZQCL command is issued during initialization and after self-refresh exit command.
Page 425 DMC Programming Model Initializing the DMC (ADSP-SC58x) To initialize the DMC, use the following steps. If it is not the first time that the DMC initializes, check to first ensure that the DMC is idle and not in the midst of any activity. If DMC initialization occurs for the first time after power-up, PHY and PAD initialization is a requirement.
Page 426 DMC Programming Model 1. Perform first-time DMC initialization, as needed. ADDITIONAL INFORMATION: Perform this step only for the first time DMC initialization after power-up or reset. Skip this step if reinitializing the DMC. a. Set the DMC_PHY_CTL0.RESETDLL bit of the DMC_PHY_CTL0 register.
Page 427 DMC Programming Model DMC CONTROLLER INITIALIZATION CGU (DCLK) INITIALIZATION START PLACE DMC IN PROGRAM THE DMCx_CFG, SELF REFERSH MODE DMCx_TR2-0, DMCx_MR (DDR2/LPDDR), DMCx_MR0 (DDR3), DMCx_EMR1 (DDR2), DMCx_MR1 (DDR3), DMCx_EMR2 (DDR2), DMCx_EMR (LPDDR), DMCx_MR2 (DDR3) FIRST TIME DMCx_PHY_CTL0.RESETDLL INIT. AFTER POWER-UP RESET? ENSURE THE DMC_DT_CALIB_ADDR REGISTER IS PROGRAMMED TO AN UNUSED...
Page 428 ADSP-SC58x DMC Register Descriptions address programmed is not 16-byte aligned. For example, it updates all the locations 0x80000000 to 0x8000000F regardless of whether the address is programmed as 0x80000000 or 0x80000004. The program performs second-time initialization for cases where the DMC has already been initialized. The initiali- zation can be through a preload during a debug session, or through code executed during the booting process.
Page 429 ADSP-SC58x DMC Register Descriptions Table 10-10: ADSP-SC58x DMC Register List (Continued) Name Description DMC_TR1 Timing 1 Register DMC_TR2 Timing 2 Register ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference 10–23...
Page 430 ADSP-SC58x DMC Register Descriptions Configuration Register register selects SDRAM device specific parameters and selects the SDRAM interface width. DMC_CFG EXTBANK (R/W) IFWID (R/W) External Banks Interface Width SDRSIZE (R/W) SDRWID (R/W) SDRAM Size SDRAM Width Figure 10-2: DMC_CFG Register Diagram Table 10-11: DMC_CFG Register Fields Bit No.
Page 431 ADSP-SC58x DMC Register Descriptions Table 10-11: DMC_CFG Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) SDRWID SDRAM Width. (R/W) The DMC_CFG.SDRWID bits select the width of the individual SDRAM connected to the DMC. Note that all values other than those shown are reserved. 0-1 Reserved 2 16-Bit Wide SDRAM 3-15 Reserved...
Page 432 ADSP-SC58x DMC Register Descriptions Controller to PHY Interface Register CPHY_CTL[15:0] (W) Register given from Controller to PHY CPHY_CTL[31:16] (W) Register given from Controller to PHY Figure 10-3: DMC_CPHY_CTL Register Diagram Table 10-12: DMC_CPHY_CTL Register Fields Bit No. Bit Name Description/Enumeration (Access) 31:0 CPHY_CTL...
Page 433 ADSP-SC58x DMC Register Descriptions Control Register register controls DMC modes, DLL calibration, and DRAM initialization. DMC_CTL DLLCAL (R0/W) DDR3EN (R/W) DLL Calibration Start DDR3 Mode PPREF (R/W) LPDDR (R/W) Postpone Refresh Low Power DDR Mode RDTOWR (R/W) INIT (R0/W) Read-to-Write Cycle Initialize DRAM Start ADDRMODE (R/W) SRREQ (R/W)
Page 434 ADSP-SC58x DMC Register Descriptions Table 10-13: DMC_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) DLLCAL DLL Calibration Start. (R0/W) The DMC_CTL.DLLCAL bit starts the PHY DLL calibration sequence. Note that this bit always reads as 0. 0 No effect 1 Start PHY DLL calibration PPREF Postpone Refresh.
Page 435 ADSP-SC58x DMC Register Descriptions Table 10-13: DMC_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ADDRMODE Addressing (Page/Bank) Mode. (R/W) The DMC_CTL.ADDRMODE bit selects whether the DMC uses page or bank inter- leaving for addressing. When using page interleaving, the bank address bits follow the most significant column address bits.
Page 436 ADSP-SC58x DMC Register Descriptions Table 10-13: DMC_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) SRREQ Self-Refresh Request. (R/W) The DMC_CTL.SRREQ bit enables self-refresh mode. When the DMC is in self-re- fresh mode, any data accesses cause the DMC to generate a bus error. The DRAM re- mains in self-refresh mode as along as this bit is 1.
Page 437 ADSP-SC58x DMC Register Descriptions DLL Control Register register holds the programmable parameters associated with the DLLs within the DMC PHY. DMC_DLLCTL DATACYC (R/W) DLLCALRDCNT (R/W) Data Cycles DLL Calibration RD Count Figure 10-5: DMC_DLLCTL Register Diagram Table 10-14: DMC_DLLCTL Register Fields Bit No.
Page 438 ADSP-SC58x DMC Register Descriptions Data Calibration Address Register register provides the address used for the data calibration for read and write. During DMC_DT_CALIB_ADDR the DMC PHY DLL calibration, a particular set of locations in the DRAM is written and a series of reads are per- formed back to back to calibrate the PHY.
Page 439 ADSP-SC58x DMC Register Descriptions Data Calibration Data 0 Register register contains the first 32-bit data used for the write during the data cali- DMC_DT_DATA_CALIB_DATA0 bration. DMC_DT_DATA_CALIB_DATA0[15:0] (R/W) Data Calibration Data 0 DMC_DT_DATA_CALIB_DATA0[31:16] (R/W) Data Calibration Data 0 Figure 10-7: DMC_DT_DATA_CALIB_DATA0 Register Diagram Table 10-16: DMC_DT_DATA_CALIB_DATA0 Register Fields Bit No.
Page 440 ADSP-SC58x DMC Register Descriptions Data Calibration Data 1 Register register contains the second 32-bit data used for the write during the data DMC_DT_DATA_CALIB_DATA1 calibration. DMC_DT_DATA_CALIB_DATA1[15:0] (R/W) Data Calibration Data 1 DMC_DT_DATA_CALIB_DATA1[31:16] (R/W) Data Calibration Data 1 Figure 10-8: DMC_DT_DATA_CALIB_DATA1 Register Diagram Table 10-17: DMC_DT_DATA_CALIB_DATA1 Register Fields Bit No.
Page 441 ADSP-SC58x DMC Register Descriptions Efficiency Control Register register control DMC features that improve throughput efficiency. These include features such DMC_EFFCTL as auto-refresh management, precharge options, and write data options. PRECBANK7 (R/W) PRECBANK0 (R/W) Precharge Bank 7 Precharge Bank 0 PRECBANK6 (R/W) PRECBANK1 (R/W) Precharge Bank 6 Precharge Bank 1...
Page 442 ADSP-SC58x DMC Register Descriptions Table 10-18: DMC_EFFCTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 19:16 NUMREF Number of Refresh Commands. (R/W) The DMC_EFFCTL.NUMREF bits select the number of auto-refresh commands that the DMC can accumulate if postpone refresh is enabled (DMC_CTL.PPREF =1). The number of auto-refresh commands that can accumulate depends on whether the DMC is in DDR2 or LPDDR mode as selected by the DMC_CTL.LPDDR bit.
Page 443 ADSP-SC58x DMC Register Descriptions Table 10-18: DMC_EFFCTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PRECBANK5 Precharge Bank 5. (R/W) The DMC_EFFCTL.PRECBANK5 bit enables precharge (closes the page) of bank 5 after each transfer if the DMC precharge feature is enabled (DMC_CTL.PREC =1). Note: The (DMC_CTL.PREC) takes precedence over value in this register.
Page 444 ADSP-SC58x DMC Register Descriptions Table 10-18: DMC_EFFCTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PRECBANK0 Precharge Bank 0. (R/W) The DMC_EFFCTL.PRECBANK0 bit enables precharge (closes the page) of bank 0 after each transfer if the DMC precharge feature is enabled (DMC_CTL.PREC =1). Note: The (DMC_CTL.PREC) takes precedence over value in this register.
Page 445 ADSP-SC58x DMC Register Descriptions Shadow EMR1 DDR2 Register register in the DMC shadows the EMR1 register in the SDRAM when the DMC is in DDR2 DMC_EMR1 mode (DMC_CTL.LPDDR =0). This register is used only when the DMC is operating in DDR2 mode. If unmasked by the corresponding bit in the shadow mask register (DMC_MSK.EMR1 =1), a write to DMC_EMR1 triggers an extended “mode register set”...
Page 446 ADSP-SC58x DMC Register Descriptions Table 10-19: DMC_EMR1 Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Additive Latency. (R/W) The DMC_EMR1.AL bits select a number of added latency time for CAS operations in terms of clock cycles (t ). For more information about this operation, see the data sheet for the SDRAM being used in your system.
Page 447 ADSP-SC58x DMC Register Descriptions Shadow EMR2 Register (DDR2)/Shadow EMR Register (LPDDR) register in the DMC shadows the EMR2 register in the SDRAM when the DMC is in DDR2 DMC_EMR2 mode (DMC_CTL.LPDDR =0) and shadows the EMR register in the SDRAM when the DMC is in LPDDR mode (DMC_CTL.LPDDR =1).
Page 448 ADSP-SC58x DMC Register Descriptions Table 10-20: DMC_EMR2 Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) TCSR Temperature Compensated Self-Refresh. (R/W) The DMC_EMR2.TCSR bits select the temperature for applying temperature compen- sated self-refresh when the DMC is in LPDDR mode. (These bits are reserved when the DMC is in DDR2 mode.) For more information about this operation, see the data sheet for the SDRAM being used in your system.
Page 449 ADSP-SC58x DMC Register Descriptions Shadow MR Register (DDR2/LPDDR), Shadow MR0 Register (DDR3) register in the DMC shadows the MR register in the SDRAM when the DMC is in DDR2 mode or DMC_MR LPDDR mode (DMC_CTL.LPDDR =0 or =1 and DMC_CTL.DDR3EN =0) or DDR3 mode (DMC_CTL.DDR3EN =0 or =1 and DMC_CTL.LPDDR =0).
Page 450 ADSP-SC58x DMC Register Descriptions Table 10-21: DMC_MR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 5 6 Clock Cycles for DDR2 and 10 clock cycles for DDR3 6 7 Clock Cycles for DDR2 and 12 clock cycles for DDR3 7 8 Clock Cycles for DDR2 and 14 clock cycles for DDR3 DLLRST...
Page 451 ADSP-SC58x DMC Register Descriptions Table 10-21: DMC_MR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) CAS Latency. (R/W) The DMC_MR.CL bit field selects latency from the assertion of a read/write signal to the SDRAM until the first valid data on the output from the SDRAM in terms of clock cycles.
Page 452 ADSP-SC58x DMC Register Descriptions Shadow MR1 Register (DDR3) register is a mirror of the DDR3 SDRAM Mode register 1. This register is used only when the DMC_MR1 DMC is operating in DDR3 mode. A write to this register triggers an extended "mode register 1 set" command on the memory interface provided the corresponding mask bit is set in the mask register.
Page 453 ADSP-SC58x DMC Register Descriptions Table 10-22: DMC_MR1 Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) RTT2 Rtt_nom. (R/W) The DMC_MR1.RTT2 bit is used in conjunction with the DMC_MR1.RTT0 and DMC_MR1.RTT1 bits. (9 6 2) 0 0 0 Rtt_Nom disabled 0 0 1 RZQ/4 0 1 0 RZQ/2 0 1 1 RZQ/6...
Page 454 ADSP-SC58x DMC Register Descriptions Table 10-22: DMC_MR1 Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) DIC0 Output Driver Impedance control. (R/W) The DMC_MR1.DIC0 bit is used with the DMC_MR1.DIC1 bit. DLLEN DLL Enable. (R/W) The DMC_MR1.DLLEN bit enables the DLL in the SDRAM. For more information about this operation, see the data sheet for the SDRAM being used in your system.
Page 455 ADSP-SC58x DMC Register Descriptions Shadow MR2 Register (DDR3) register mirrors DDR3 SDRAM device Mode register 2 when the controller is operating in DDR3 DMC_MR2 mode. A write to this register triggers an extended "mode register set" command on the memory interface provided the corresponding mask bit is set in the mask register.
Page 456 ADSP-SC58x DMC Register Descriptions Table 10-23: DMC_MR2 Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PASR Partial Array Self refresh. (R/W) The DMC_MR2.PASR bits select the amount of memory to be refreshed during self refresh. For more information about this operation, see the data sheet for the SDRAM being used in your system.
Page 457 ADSP-SC58x DMC Register Descriptions Mask (Mode Register Shadow) Register register permits masking (disabling) writes to the MR and EMRn registers in the SDRAM. When DMC_MSK masked, writes to these registers go instead to shadow copies of these registers (DMC_MR, DMC_EMR1, DMC_EMR2), which are maintained within the DMC.
Page 458 ADSP-SC58x DMC Register Descriptions Table 10-24: DMC_MSK Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) EMR1 Shadow EMR1 Unmask. (R/W) The DMC_MSK.EMR1 bit masks or unmasks writes to the EMR1 register in the SDRAM. When masked, writes to this register instead go to the DMC_EMR1 register.
Page 459 ADSP-SC58x DMC Register Descriptions Priority ID Register 1 register allows transactions from selected masters that generate specific SCB IDs to obtain higher DMC_PRIO priority than the transactions proceeding in the usual fashion. The contents of the register are masked with the con- tents of the DMC_PRIOMSK register to obtain a single SCB ID or a range of IDs that get elevated priority.
Page 460 ADSP-SC58x DMC Register Descriptions Priority ID Register 2 register is another register which allows transactions from selected masters that generate specific DMC_PRIO2 SCB IDs to obtain higher priority than the transactions proceeding in the usual fashion. The contents of the register are masked with the contents of the DMC_PRIOMSK2 register to obtain a single SCB ID or a range of IDs that get...
Page 461 ADSP-SC58x DMC Register Descriptions Priority ID Mask Register 1 register masks the respective ID bits in the register. This masking provides DMC_PRIOMSK DMC_PRIOMSK for elevating the access priority of either a single ID or a range of IDs. ID1MSK[15:0] (R/W) Mask for SCB ID1 ID1MSK[31:16] (R/W) Mask for SCB ID1...
Page 462 ADSP-SC58x DMC Register Descriptions Priority ID Mask Register 2 register bits mask the respective ID bits in the register. This masking provides DMC_PRIOMSK2 DMC_PRIO2 for elevating the access priority of either a single ID or a range of IDs. ID2MSK[15:0] (R/W) Mask for SCB ID2 ID2MSK[31:16] (R/W) Mask for SCB ID2...
Page 463 ADSP-SC58x DMC Register Descriptions DMC Read Data Buffer ID Register 1 register allows read transactions from selected masters to make use of DMC read data DMC_RDDATABUFID1 buffer. The contents of the register are masked with the contents of the DMC_RDDATABUFMSK1 register to obtain a single SCB ID or a range of IDs that get elevated priority.
Page 464 ADSP-SC58x DMC Register Descriptions DMC Read Data Buffer ID Register 2 register allows read transactions from selected masters to make use of DMC read data DMC_RDDATABUFID2 buffer. The contents of the register are masked with the contents of the DMC_RDDATABUFMSK2 register to obtain a single SCB ID or a range of IDs that get elevated priority.
Page 465 ADSP-SC58x DMC Register Descriptions DMC Read Data Buffer Mask Register 1 register bits mask the respective ID bits in the DMC Priority Mask ID register. DMC_RDDATABUFMSK1 VALUE[15:0] (R/W) Mask for Read Data Buffer ID1 VALUE[31:16] (R/W) Mask for Read Data Buffer ID1 Figure 10-22: DMC_RDDATABUFMSK1 Register Diagram Table 10-31: DMC_RDDATABUFMSK1 Register Fields Bit No.
Page 466 ADSP-SC58x DMC Register Descriptions DMC Read Data Buffer Mask Register 2 register bits mask the respective ID bits in the DMC Priority Mask ID register. DMC_RDDATABUFMSK2 VALUE[15:0] (R/W) Mask for Read Data Buffer ID2 VALUE[31:16] (R/W) Mask for Read Data Buffer ID2 Figure 10-23: DMC_RDDATABUFMSK2 Register Diagram Table 10-32: DMC_RDDATABUFMSK2 Register Fields Bit No.
Page 467 ADSP-SC58x DMC Register Descriptions Status Register register indicates status for modes selected with the register and indicates status DMC DMC_STAT DMC_CTL operations. DLLCALDONE (R) IDLE (R) DLL Calibration Done Idle State RESETDONE (R) INITDONE (R) Reset Done Initialization Done DPDACK (R) SRACK (R) Deep Power-Down Acknowledge Self-Refresh Acknowledge...
Page 468 ADSP-SC58x DMC Register Descriptions Table 10-33: DMC_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 2 2 Clock Cycles Latency 3 3 Clock Cycles Latency 4 4 Clock Cycles Latency 5 5 Clock Cycles Latency 6 6 Clock Cycles Latency 7 7Clock Cycles Latency 19:16 PENDREF...
Page 469 ADSP-SC58x DMC Register Descriptions Table 10-33: DMC_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) INITDONE Initialization Done. (R/NW) The DMC_STAT.INITDONE bit indicates that the initialization sequence is com- plete. 0 No Status 1 Initialize Done IDLE Idle State. (R/NW) The DMC_STAT.IDLE bit indicates whether the DMC is idle or busy.
Page 470 ADSP-SC58x DMC Register Descriptions Timing 0 Register register selects timing parameters for DMC operation to corresponding with parameters of the DMC_TR0 SDRAM device that is used in the system. The timing registers must be programmed to match the device for correct operation of the SDRAM and must be programmed before initializing the SDRAM.
Page 471 ADSP-SC58x DMC Register Descriptions Table 10-34: DMC_TR0 Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) TWTR Timing Write to Read. (R/W) The DMC_TR0.TWTR field selects the write-to-read delay time (t ), which is the number of clock cycles that occur from the last write data to the next read command. TRCD Timing RAS to CAS Delay.
Page 472 ADSP-SC58x DMC Register Descriptions Timing 1 Register register selects timing parameters for DMC operation to corresponding with parameters of the DMC_TR1 SDRAM device that is used in the system. The timing registers must be programmed to match the device for correct operation of the SDRAM and must be programmed before initializing the SDRAM.
Page 473 ADSP-SC58x DMC Register Descriptions Timing 2 Register register selects timing parameters for DMC operation to corresponding with parameters of the DMC_TR2 SDRAM device that is used in the system. The timing registers must be programmed to match the device for correct operation of the SDRAM and before initializing the SDRAM.
Page 474 ADSP-SC58x DMC Register Descriptions ADSP-SC58x DMC Register Descriptions DMCPHY (DMC) contains the following registers. Table 10-37: ADSP-SC58x DMC Register List Name Description DMC_CAL_PADCTL0 Calibration PAD Control 0 Register DMC_CAL_PADCTL2 Calibration PAD Control 2 Register DMC_PHY_CTL0 PHY Control 0 Register DMC_PHY_CTL1 PHY Control 1 Register DMC_PHY_CTL2 PHY Control 2 Register...
Page 475 ADSP-SC58x DMC Register Descriptions Calibration PAD Control 0 Register register sets the pad calibration controls. DMC_CAL_PADCTL0 RTTCALEN (R/W) CALSTRT (R/W) RTT Calibration Enable Start New Calibration ( Hardware Cleared) PDCALEN (R/W) PUCALEN (R/W) PULLDOWN Calibration Enable PULLUP Calibration Enable Figure 10-28: DMC_CAL_PADCTL0 Register Diagram Table 10-38: DMC_CAL_PADCTL0 Register Fields Bit No.
Page 476 ADSP-SC58x DMC Register Descriptions Calibration PAD Control 2 Register register sets the pad calibration controls. The DMC pads can be auto-calibrated to the DMC_CAL_PADCTL2 required driver impedance and the On Die Termination (ODT) value using the corresponding bits in this register. These values are translated by the auto calibration logic into a corresponding drive strength control inside the PHY and then routed to the PADS.
Page 477 ADSP-SC58x DMC Register Descriptions PHY Control 0 Register register controls programmable PHY features. DMC_PHY_CTL0 RESETDAT (R/W) RESETDLL (R/W) Reset Data Capture Logic Reset DLL Figure 10-30: DMC_PHY_CTL0 Register Diagram Table 10-40: DMC_PHY_CTL0 Register Fields Bit No. Bit Name Description/Enumeration (Access) RESETDAT Reset Data Capture Logic.
Page 478 ADSP-SC58x DMC Register Descriptions PHY Control 1 Register register controls programmable PHY features. DMC_PHY_CTL1 BYPODTEN (R/W) Bypass ODTEN for DQ and DQS Figure 10-31: DMC_PHY_CTL1 Register Diagram Table 10-41: DMC_PHY_CTL1 Register Fields Bit No. Bit Name Description/Enumeration (Access) BYPODTEN Bypass ODTEN for DQ and DQS. (R/W) 0 Reserved 1 Reserved...
Page 479 ADSP-SC58x DMC Register Descriptions PHY Control 2 Register register controls programmable PHY features. Program this register as per the programming DMC_PHY_CTL2 guidelines for proper operation of the DMC. VALUE[15:0] (R/W) 32 Bit Value VALUE[31:16] (R/W) 32 Bit Value Figure 10-32: DMC_PHY_CTL2 Register Diagram Table 10-42: DMC_PHY_CTL2 Register Fields Bit No.
Page 480 ADSP-SC58x DMC Register Descriptions PHY Control 3 Register register controls programmable PHY features. Program this register as per the programming DMC_PHY_CTL3 guidelines for proper operation of DMC. VALUE[15:0] (R/W) 32 Bit Value VALUE[31:16] (R/W) 32 Bit Value Figure 10-33: DMC_PHY_CTL3 Register Diagram Table 10-43: DMC_PHY_CTL3 Register Fields Bit No.
Page 481 ADSP-SC58x DMC Register Descriptions PHY Control 4 Register register controls programmable PHY features. DMC_PHY_CTL4 CLKDIS (R/W) DDRMODE (R/W) Clock Disable DDR Mode Select Figure 10-34: DMC_PHY_CTL4 Register Diagram Table 10-44: DMC_PHY_CTL4 Register Fields Bit No. Bit Name Description/Enumeration (Access) CLKDIS Clock Disable.
Page 482 Static Memory Controller (SMC) 11 Static Memory Controller (SMC) The static memory controller is a protocol converter and data transfer interface between the internal processor bus and the external L3 memory. It provides a glueless interface to various external memories and peripheral devices, including: •...
Page 483 SMC Definitions Read setup time The time between the beginning of a memory cycle (SMC_AMS0 signal low) and the read-enable assertion (SMC_ARE signal low). Read hold time The time between read-enable deassertion (SMC_ARE signal high) and the end of the memory cycle (SMC_AMS0 signal high).
Page 484 SMC Functional Description Memory transition time The number of bus idle cycles extending the idle time cycles. These idle cycles occur in the case where a subsequent access has a different data direction or the access is to a different bank. Bus contention State of the bus in which more than one device on the bus attempts to place values on the bus at the same time.
Page 485 SMC Functional Description ADSP-SC58x SMC Register List The Static Memory Controller SMC is a protocol converter and data transfer interface between the internal process- or bus and the external L3 memory. The SMC acts as a bus slave, and accesses to SMC are arbitrated by the mod- ule's system crossbar.
Page 486 SMC Architectural Concepts The byte enable pins are both three-stated during all asynchronous reads and are driven low during 16-bit asynchro- nous writes. When an asynchronous write is made to the upper byte of a 16-bit memory, SMC_ABE1 =0 and SMC_ABE0 =1.
Page 487 SMC Architectural Concepts The reset value of turnaround transition time is two cycles. Program the SMC_B0ETIM.TT bit to a value either greater than or equal to two cycles, depending on memory AC-timing specifications. It is important to be aware that the SMC_B0ETIM.TT bit is programmed to 0 only when: •...
Page 488 SMC Operating Modes Asynchronous Flash Mode When the access selected mode is asynchronous flash (SMC_B0CTL.MODE =01), external bank accesses operate the same as in standard asynchronous mode, except for the pin configuration. Use this mode when accessing burst devices in non-read array modes. Asynchronous Page Mode When asynchronous page mode access is selected (SMC_B0CTL.MODE =10), asynchronous page reads are enabled.
Page 489 SMC Programmable Timing Characteristics Write Write Write Trams Read Read Read Setup Access Hold TURN Setup Access Hold 2 Cycles 4 Cycles 2 Cycles 2 Cycles 3 Cycles 5 Cycles 1 Cycle CLKOUT SMC_An SMC_AMSn SMC_AOE SMC_AWE SMC_ARE BE1-0 SMC_D15-0 Figure 11-2: Basic Asynchronous SRAM Write Followed by Read For the current bank, the programmed time cycles are: •...
Page 490 SMC Programmable Timing Characteristics 6. At the start of the read access period, the read enable signal, SMC_ARE is asserted. 7. At the end of the read access period, the SMC_ARE signal is deasserted and the read hold period starts. Read data is latched along with SMC_ARE deasserting.
Page 491 SMC Programmable Timing Characteristics Setup Read Access Trans. TURN 1 Cycle 2 Cycles 2 Cycles CLKOUT ADDRn A0 + 1 A0 + 2 A0 + 3 AMSn DATA15-0 Read Data Latching Edges Figure 11-4: Fast Asynchronous SRAM Reads, Burst of Four Word In this case, the target SMC bank has been programmed with: •...
Page 492 SMC Programmable Timing Characteristics Setup Write Access Trans. TURN 1 Cycle 2 Cycles 2 Cycles CLKOUT SMC_An A0 + 1 A0 + 2 A0 + 3 SMC_AMSn SMC_AOE SMC_ABE1-0 SMC_AWE SMC_D15-0 Figure 11-5: Fast Asynchronous SRAM Writes Asynchronous SRAM Reads with ARDY The Asynchronous SRAM Read with ARDY figure shows an extended asynchronous SRAM read bus cycle with SMC_ARDY enabled.
Page 493 SMC Programmable Timing Characteristics • Pre-setup time = 1 cycle • Read setup time = 3 cycles • Read access time = 6 cycles • Read hold time = 2 cycles • SMC_B0CTL.RDYPOL =1 (memory is ready when SMC_ARDY =1) The bus cycles proceed as follows: •...
Page 494 SMC Programmable Timing Characteristics Pre-Setup Pre-Access Read Data 1 Cycle 1 Cycle Latched Here Setup Read Access Hold 2 Cycles 5 Cycles 2 Cycles CLKOUT NOR_An NOR_CE NOR_ADV NOR_OE NOR_DQ15-0 Figure 11-7: Asynchronous Flash Read with Pre-Setup and Pre-Access Cycles In this case, the target SMC bank has been programmed with: •...
Page 495 SMC Programmable Timing Characteristics CLKOUT NOR_An A0 + 1 NOR_CE NOR_ADV NOR_OE NOR_DQ15-0 Setup Read Access Hold 2 Cycles 5 Cycles 2 Cycles Read Data Read Data Latched Here Latched Here Figure 11-8: 32-bit Asynchronous Flash Read Asynchronous Flash Writes The Asynchronous Flash Write Operation figure shows a single asynchronous flash write bus cycle.
Page 496 SMC Programmable Timing Characteristics SMC_AOE signal as the address valid signal (SMC_NORDV). The SMC_AOE signal asserts during the setup period, unlike in asynchronous SRAM writes where the SMC_AOE signal never asserts. Asynchronous Flash Page Mode Reads The Asynchronous Page Mode Read Bus Cycle figure shows an asynchronous page mode bus read cycle for a burst of five reads.
Page 497 SMC Programmable Timing Characteristics Read Read Data Latched Data Latched CLKOUT AMS(n)/RE DATA/DQ15 Read Read Read Trans. Setup Access Hold TURN 1 Cycle 3 Cycles 1 Cycle 2 Cycles Figure 11-11: Asynchronous FIFO Read Bus Cycles Other settings are: • Read setup time = 1 cycle •...
Page 498 SMC Programming Model CLKOUT AMS(n)/WE DATA/DIN Write Write Write Trans. Setup Access Hold TURN 1 Cycle 3 Cycles 1 Cycle 2 Cycles Figure 11-12: Asynchronous FIFO Write Bus Cycles SMC Programming Model The following general guidelines are used for configuring and enabling the SMC interface. Failure to follow these guidelines can lead to erroneous behavior.
Page 499 ADSP-SC58x SMC Register Descriptions Table 11-2: ADSP-SC58x SMC Register List Name Description SMC_B0CTL Bank 0 Control Register SMC_B0ETIM Bank 0 Extended Timing Register SMC_B0TIM Bank 0 Timing Register SMC_B1CTL Bank 1 Control Register SMC_B1ETIM Bank 1 Extended Timing Register SMC_B1TIM Bank 1 Timing Register SMC_B2CTL Bank 2 Control Register...
Page 500 ADSP-SC58x SMC Register Descriptions Bank 0 Control Register register enables bank 0 accesses and configures the memory access features for this bank. SMC_B0CTL RDYABTEN (R/W) EN (R/W) ARDY Abort Enable Bank 0 Enable RDYPOL (R/W) MODE (R/W) ARDY Polarity Memory Access Mode RDYEN (R/W) SELCTRL (R/W) ARDY Enable...
Page 501 ADSP-SC58x SMC Register Descriptions Table 11-3: SMC_B0CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) RDYABTEN ARDY Abort Enable. (R/W) The SMC_B0CTL.RDYABTEN bit enables the abort counter for the SMC_ARDY pin, if enabled (SMC_B0CTL.RDYEN =1). After SMC_B0TIM.RAT or SMC_B0TIM.WAT cycles, the SMC starts sampling the SMC_ARDY pin and starts the abort down counter (if enabled).
Page 502 ADSP-SC58x SMC Register Descriptions Table 11-3: SMC_B0CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) MODE Memory Access Mode. (R/W) The SMC_B0CTL.MODE bits select the protocol the SMC uses for static memory read/write access. Note that the write protocol for async flash, async flash page, and sync burst flash are all similar;...
Page 503 ADSP-SC58x SMC Register Descriptions Bank 0 Extended Timing Register register configures extensions to access times and idle times, augmenting the setup, hold, and SMC_B0ETIM access times configured with the SMC_B0TIM register. IT (R/W) PREST (R/W) Idle Time Pre Setup Time TT (R/W) PREAT (R/W) Transition Time...
Page 504 ADSP-SC58x SMC Register Descriptions Table 11-4: SMC_B0ETIM Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 10:8 Transition Time. (R/W) The SMC_B0ETIM.TT bits select a bus idle time (in SCLK0_0 cycles) that the SMC extends the SMC_B0ETIM.IT to allow for the subsequent access either using a dif- ferent transfer direction or accessing a different bank.
Page 505 ADSP-SC58x SMC Register Descriptions Bank 0 Timing Register register configures bank 0 read and write access, setup, and hold timing for this bank. Note that SMC_B0TIM read and write timing configurations are independent and may differ. WAT (R/W) WST (R/W) Write Access Time Write Setup Time WHT (R/W)
Page 506 ADSP-SC58x SMC Register Descriptions Table 11-5: SMC_B0TIM Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 18:16 Read Setup Time. (R/W) The SMC_B0TIM.RST bits select the setup time (in SCLK0_0 cycles) that the SMC asserts the SMC_AOE pin before asserting the SMC_ARE pin for an access. The setup time is from 1 to 8 SCLK0_0 cycles.
Page 507 ADSP-SC58x SMC Register Descriptions Bank 1 Control Register register enables bank 1 accesses and configures the memory access features for this bank. SMC_B1CTL RDYABTEN (R/W) EN (R/W) ARDY Abort Enable Bank 1 Enable RDYPOL (R/W) MODE (R/W) ARDY Polarity Memory Access Mode RDYEN (R/W) SELCTRL (R/W) ARDY Enable...
Page 508 ADSP-SC58x SMC Register Descriptions Table 11-6: SMC_B1CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) RDYABTEN ARDY Abort Enable. (R/W) The SMC_B1CTL.RDYABTEN bit enables the abort counter for the SMC_ARDY pin, if enabled (SMC_B1CTL.RDYEN =1). After SMC_B1TIM.RAT or SMC_B1TIM.WAT cycles, the SMC starts sampling the SMC_ARDY pin and starts the abort down counter (if enabled).
Page 509 ADSP-SC58x SMC Register Descriptions Table 11-6: SMC_B1CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) MODE Memory Access Mode. (R/W) The SMC_B1CTL.MODE bits select the protocol the SMC uses for static memory read/write access. Note that the write protocol for async flash, async flash page, and sync burst flash are all similar;...
Page 510 ADSP-SC58x SMC Register Descriptions Bank 1 Extended Timing Register register configures extensions to access times and idle times, augmenting the setup, hold, and SMC_B1ETIM access times configured with the SMC_B1TIM register. IT (R/W) PREST (R/W) Idle Time Pre Setup Time TT (R/W) PREAT (R/W) Transition Time...
Page 511 ADSP-SC58x SMC Register Descriptions Table 11-7: SMC_B1ETIM Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 10:8 Transition Time. (R/W) The SMC_B1ETIM.TT bits select a bus idle time (in SCLK0_0 cycles) that the SMC extends the SMC_B1ETIM.IT to allow for the subsequent access either using a dif- ferent transfer direction or accessing a different bank.
Page 512 ADSP-SC58x SMC Register Descriptions Bank 1 Timing Register register configures bank 1 read and write access, setup, and hold timing for this bank. Note that SMC_B1TIM read and write timing configurations are independent and may differ. WAT (R/W) WST (R/W) Write Access Time Write Setup Time WHT (R/W)
Page 513 ADSP-SC58x SMC Register Descriptions Table 11-8: SMC_B1TIM Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 18:16 Read Setup Time. (R/W) The SMC_B1TIM.RST bits select the setup time (in SCLK0_0 cycles) that the SMC asserts the SMC_AOE pin before asserting the SMC_ARE pin for an access. The setup time is from 1 to 8 SCLK0_0 cycles.
Page 514 ADSP-SC58x SMC Register Descriptions Bank 2 Control Register register enables bank 2 accesses and configures the memory access features for this bank. SMC_B2CTL RDYABTEN (R/W) EN (R/W) ARDY Abort Enable Bank 2 Enable RDYPOL (R/W) MODE (R/W) ARDY Polarity Memory Access Mode RDYEN (R/W) SELCTRL (R/W) ARDY Enable...
Page 515 ADSP-SC58x SMC Register Descriptions Table 11-9: SMC_B2CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) RDYABTEN ARDY Abort Enable. (R/W) The SMC_B2CTL.RDYABTEN bit enables the abort counter for the SMC_ARDY pin, if enabled (SMC_B2CTL.RDYEN =1). After SMC_B2TIM.RAT or SMC_B2TIM.WAT cycles, the SMC starts sampling the SMC_ARDY pin and starts the abort down counter (if enabled).
Page 516 ADSP-SC58x SMC Register Descriptions Table 11-9: SMC_B2CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) MODE Memory Access Mode. (R/W) The SMC_B2CTL.MODE bits select the protocol the SMC uses for static memory read/write access. Note that the write protocol for async flash, async flash page, and sync burst flash are all similar;...
Page 517 ADSP-SC58x SMC Register Descriptions Bank 2 Extended Timing Register register configures extensions to access times and idle times, augmenting the setup, hold, and SMC_B2ETIM access times configured with the SMC_B2TIM register. IT (R/W) PREST (R/W) Idle Time Pre Setup Time TT (R/W) PREAT (R/W) Transition Time...
Page 518 ADSP-SC58x SMC Register Descriptions Table 11-10: SMC_B2ETIM Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 10:8 Transition Time. (R/W) The SMC_B2ETIM.TT bits select a bus idle time (in SCLK0_0 cycles) that the SMC extends the SMC_B2ETIM.IT to allow for the subsequent access either using a dif- ferent transfer direction or accessing a different bank.
Page 519 ADSP-SC58x SMC Register Descriptions Bank 2 Timing Register register configures bank 2 read and write access, setup, and hold timing for this bank. Note that SMC_B2TIM read and write timing configurations are independent and may differ. WAT (R/W) WST (R/W) Write Access Time Write Setup Time WHT (R/W)
Page 520 ADSP-SC58x SMC Register Descriptions Table 11-11: SMC_B2TIM Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 18:16 Read Setup Time. (R/W) The SMC_B2TIM.RST bits select the setup time (in SCLK0_0 cycles) that the SMC asserts the SMC_AOE pin before asserting the SMC_ARE pin for an access. The setup time is from 1 to 8 SCLK0_0 cycles.
Page 521 ADSP-SC58x SMC Register Descriptions Bank 3 Control Register register enables bank 3 accesses and configures the memory access features for this bank. SMC_B3CTL RDYABTEN (R/W) EN (R/W) ARDY Abort Enable Bank 3 Enable RDYPOL (R/W) MODE (R/W) ARDY Polarity Memory Access Mode RDYEN (R/W) SELCTRL (R/W) ARDY Enable...
Page 522 ADSP-SC58x SMC Register Descriptions Table 11-12: SMC_B3CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) RDYABTEN ARDY Abort Enable. (R/W) The SMC_B3CTL.RDYABTEN bit enables the abort counter for the SMC_ARDY pin, if enabled (SMC_B3CTL.RDYEN =1). After SMC_B3TIM.RAT or SMC_B3TIM.WAT cycles, the SMC starts sampling the SMC_ARDY pin and starts the abort down counter (if enabled).
Page 523 ADSP-SC58x SMC Register Descriptions Table 11-12: SMC_B3CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) MODE Memory Access Mode. (R/W) The SMC_B3CTL.MODE bits select the protocol the SMC uses for static memory read/write access. Note that the write protocol for async flash, async flash page, and sync burst flash are all similar;...
Page 524 ADSP-SC58x SMC Register Descriptions Bank 3 Extended Timing Register register configures extensions to access times and idle times, augmenting the setup, hold, and SMC_B3ETIM access times configured with the SMC_B3TIM register. IT (R/W) PREST (R/W) Idle Time Pre Setup Time TT (R/W) PREAT (R/W) Transition Time...
Page 525 ADSP-SC58x SMC Register Descriptions Table 11-13: SMC_B3ETIM Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 10:8 Transition Time. (R/W) The SMC_B3ETIM.TT bits select a bus idle time (in SCLK0_0 cycles) that the SMC extends the SMC_B3ETIM.IT to allow for the subsequent access either using a dif- ferent transfer direction or accessing a different bank.
Page 526 ADSP-SC58x SMC Register Descriptions Bank 3 Timing Register register configures bank 3 read and write access, setup, and hold timing for this bank. Note that SMC_B3TIM read and write timing configurations are independent and may differ. WAT (R/W) WST (R/W) Write Access Time Write Setup Time WHT (R/W)
Page 527 ADSP-SC58x SMC Register Descriptions Table 11-14: SMC_B3TIM Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 18:16 Read Setup Time. (R/W) The SMC_B3TIM.RST bits select the setup time (in SCLK0_0 cycles) that the SMC asserts the SMC_AOE pin before asserting the SMC_ARE pin for an access. The setup time is from 1 to 8 SCLK0_0 cycles.
Page 528 One-Time Programmable Memory Controller (OTPC) 12 One-Time Programmable Memory Con- troller (OTPC) This chapter describes the operation of the OTP controller. The OTP module is a complete system integrating an OTP memory core with a programming controller, charge pump, and voltage regulator. A built-in Hamming Code Error Correction (ECC), and a fully implemented double-redundant program or read scheme protect the OTP data.
Page 529 OTPC Event Control OTP Layout Table 12-1: ADSP-SCxx OTP Layout Name Byte Address Size (bits) Description Customer OTP Area - 896 bytes 0x0 + 0 - 0x1c Hardware unique key pvt_128key0 0x168 + 0 - 0x174 Customer private key 0 128bits pvt_128key1 0x178 + 0 - 0x184 Customer private key 1 128bits...
Page 530 OTPC Event Control OTPC Interrupt Signals When making 32-bit accesses to OTP memory, a double-bit error in any 16-bit segment triggers the OTPC_INT interrupt. The OTPC also has the OTPC dual bit error (OTPC0_ERR) with the SEC ID of 5 and the GIC ID of 37.
Page 531 OTP API Overview typedef struct { uint32_t (*huk)[8]; uint32_t (*pvt_128key1)[4]; uint32_t (*pvt_128key2)[4]; uint32_t (*pvt_128key3)[4]; uint32_t (*pvt_128key4)[4]; uint32_t (*pvt_192key1)[6]; uint32_t (*pvt_192key2)[6]; uint32_t (*public_key0)[16]; uint32_t (*public_key1)[16]; uint32_t (*ek)[8]; uint32_t (*secure_emu_key)[4]; uint8_t bootModeDisable; uint32_t (*boot_info)[16]; uint32_t (*gp0)[16]; uint32_t antiroll_nv_cntr; uint8_t stageID; uint32_t (*preboot_ddr_cfg)[11]; } otp_data;...
Page 532 OTP Reading The data specified by the OTPCMD enum parameter is fetched from OTP memory and placed in the location speci- fied by data. The OTPCMD enum contains entries for each field defined in OTP memory, for the most current list please refer to the OTP header file.
Page 533 OTP API Overview OTP Counters The OTPC module implements a counter API to allow easy reading or writing of the counter without dealing with the complexities of rewriting OTP memory sections that are ECC protected. The OTPC module provides two functional APIs for counters. These APIs are not extra; the module uses the same get and pgm APIs.
Page 534 ADSP-SC58x OTPC Interrupt List ADSP-SC58x OTPC Interrupt List Table 12-2: ADSP-SC58x OTPC Interrupt List Interrupt Name Description Sensitivity Channel OTPC0_ERR OTPC0 Dual-bit error Level ADSP-SC58x OTPC Register Descriptions OTP Memory Controller (OTPC) contains the following registers. Table 12-3: ADSP-SC58x OTPC Register List Name Description OTPC_SECU_STATE...
Page 535 ADSP-SC58x OTPC Register Descriptions OTP Security State Register register provides lock status information. OTPC_SECU_STATE PARTLOCK (R) Part Locked Figure 12-1: OTPC_SECU_STATE Register Diagram Table 12-4: OTPC_SECU_STATE Register Fields Bit No. Bit Name Description/Enumeration (Access) PARTLOCK Part Locked. (R/NW) The OTPC_SECU_STATE.PARTLOCK bit indicates a locked part. 0 OPEN part 1 Locked part 2 Unlocked part...
Page 536 ADSP-SC58x OTPC Register Descriptions OTP Status Register register bits indicate errors and flag status and control the protection bits. OTPC_STAT ADDRERR (R) OTP Address Error Figure 12-2: OTPC_STAT Register Diagram Table 12-5: OTPC_STAT Register Fields Bit No. Bit Name Description/Enumeration (Access) 14:13 ADDRERR...
Page 537 System Memory Protection Unit (SMPU) 13 System Memory Protection Unit (SMPU) The SMPU provides a flexible way of protecting memory regions against read or write access from any or all masters in the system. In addition, it can guard against memory access depending on security privileges of the system master. SMPU Features The system memory protection unit has the following features.
Page 538 SMPU Functional Description Table 13-1: SMPU Instances (Continued) Module SMPU Instance DMC0 DMC1 All the SMPU instances can be configured up to eight regions. • Up to eight outstanding read or write transactions supported on SMPU instances for Core_L2_RAM_Boot_ROM0, DMC0 and DMC1. •...
Page 539 SMPU Functional Description NOTE: The debugger typically replaces an instruction with a breakpoint instruction for software breakpoints. If a memory region is protected against write accesses, software breakpoints are not possible unless the SMPU is configured with the appropriate system master ID of the debugger. The configuration allows it to per- form a write-access.
Page 540 SMPU Functional Description Table 13-2: ADSP-SC58x SMPU Register List (Continued) Name Description SMPU_IDTLS Interrupt Details Register SMPU_RADDR[n] Region n Address Register SMPU_RCTL[n] Region n Control Register SMPU_REVID SMPU Revision ID Register SMPU_RIDA[n] Region n ID A Register SMPU_RIDB[n] Region n ID B Register SMPU_RIDMSKA[n] Region n ID Mask A Register SMPU_RIDMSKB[n]...
Page 541 SMPU Functional Description ID Comparison ID comparison automatically occurs during region-based memory protection. ID matches allow the transaction to bypass the configured memory protection for that region. The following sections describe the calculation of a write ID match and read ID match. Write Transaction The state of the following values determines the ID value that is compared with the ID of an incoming write trans- action:...
Page 542 SMPU Functional Description Depending on the setting of the SMPU_RCTL[n].RIDCINV or the SMPU_RCTL[n].WIDCINV bits, the ID match comparison is inverted or not. The final result after applying the inversion, SMPU_RCTL[n].RIDCINV, or SMPU_RCTL[n].WIDCINV, determines whether the transaction bypasses the protection. Usage The masks, SMPU_RIDMSKA[n] and SMPU_RIDMSKB[n], are AND'ed with both the incoming transaction...
Page 543 SMPU Functional Description Table 13-3: System Master IDs (Continued) Master Name SCB Input Switch Master ID SCB Input CRC0_CH1 13'b00000000x1001 CRC1_CH0 13'b00010000x1000 CRC1_CH1 13'b00010000x1001 EMAC0 13'b00100xxxx0000 13'b0011000000000 UART0_TX 13'b00100000x0001 UART0_RX 13'b00100000x0010 SDIO 13'b0010000000011 SINC 13'b00100000x0100 SPI0TX 13'b01000000x0000 SPI0RX 13'b01000000x0001 SPI1TX 13'b01000000x0010 SPI1RX 13'b01000000x0011...
Page 544 SMPU Functional Description Table 13-3: System Master IDs (Continued) Master Name SCB Input Switch Master ID SCB Input FIR_CH1 13'b0101000000111 IIR_CH0 13'b0110000000110 IIR_CH1 13'b0110000000111 EMDMA0_CH0 13'b0111000000000 EMDMA0_CH1 13'b0111000000001 EMDMA1_CH0 13'b0111000000010 EMDMA1_CH1 13'b0111000000011 STD_BW_MDMA_SRC_CH 13'b10000000x0000 STD_BW_MDMA_DST_CH 13'b10000000x0001 PCIE_M 13'b1000xxxxx0010 ENH_BW_MDMA_SRC_CH 13'b10010000x0000 ENH_BW_MDMA_DST_CH 13'b10010000x0001 FFT_CH0...
Page 545 SMPU Functional Description Table 13-4: Supported Memory Region Size and Alignment (Continued) Size SMPU_RCTLn.SIZE Address Possible Values for N 0b00001 0xXXXXN000 0x0, 0x2, 0x4, 0x8, 0xA, 0xC, 0xE 16KB 0b00010 0xXXXXN000 0x0, 0x4, 0x8, 0xC 32KB 0b00011 0xXXXXN000 0x0, 0x8 64KB 0b00100 0xXXXX0000...
Page 546 SMPU Functional Description Global Protection Guarding of the entire memory space for the particular SMPU instantiation. Region-Based Protection Guarding individual segments of memory inside the memory space for the particular SMPU instantiation. ID Match A successful comparison of the ID associated with the incoming transaction and the ID and MASK configured in the SMPU.
Page 547 SMPU Operating Modes Latency The SMPU adds latency to all the transactions to the memory except reads when read speculation is enabled (SMPU_CTL.RSDIS =0). In this case, read accesses are always forwarded to the memory and read responses are generated according to the SMPU settings. If read speculation is disabled (SMPU_CTL.RSDIS =1), reads are blocked if they cause a security or protection violation.
Page 548 SMPU Status and Error Signals If a second memory access violation occurs while the SMPU_STAT.IRQ bit is set, the SMPU_STAT.IOVR (inter- rupt overrun) bit is set. The and the registers are not updated until the SMPU_IADDR SMPU_IDTLS SMPU_STAT.IRQ bit is cleared. Any information on the subsequent interrupt is lost. Once the SMPU_STAT.IRQ bit and the SMPU_STAT.IOVR bit are cleared, any new memory access violations can trigger an interrupt and its details can be captured.
Page 549 ADSP-SC58x SMPU Register Descriptions *pREG_SMPU_RADDR0 = 0x20000000; 3. Program the SMPU_RIDA[n] SMPU_RIDB[n] registers with the ID which is to be an exception to the rule. *pREG_SMPU_RIDA0 = 0x0081; //corresponds to MDMA_WR *pREG_SMPU_RIDB0 = 0x0081; 4. Program the SMPU_RIDMSKA[n] andSMPU_RIDMSKB[n] registers with the mask to be applied to the ID values programmed in the SMPU_RIDA[n] SMPU_RIDB[n]...
Page 550 ADSP-SC58x SMPU Register Descriptions Table 13-5: ADSP-SC58x SMPU Register List (Continued) Name Description SMPU_RCTL[n] Region n Control Register SMPU_REVID SMPU Revision ID Register SMPU_RIDA[n] Region n ID A Register SMPU_RIDB[n] Region n ID B Register SMPU_RIDMSKA[n] Region n ID Mask A Register SMPU_RIDMSKB[n] Region n ID Mask B Register SMPU_SECURECTL...
Page 551 ADSP-SC58x SMPU Register Descriptions Bus Error Address Register Programs read the and the registers to determine the cause of a bus error. Write er- SMPU_BADDR SMPU_BDTLS rors are prioritized over read errors. VALUE[15:0] (R) Bus Error Address VALUE[31:16] (R) Bus Error Address Figure 13-2: SMPU_BADDR Register Diagram Table 13-6: SMPU_BADDR Register Fields Bit No.
Page 552 ADSP-SC58x SMPU Register Descriptions Bus Error Details Register register indicates the ID of the bus error transaction, whether the transaction that caused the SMPU_BDTLS last bus error was a read, a write, secure or non-secure. ID[7:0] (R) SECURE (R) ID of Transaction Secure Status Register RNW (R) Read/Write Status...
Page 553 ADSP-SC58x SMPU Register Descriptions SMPU Control Register register provides access to the locking control, error interrupts and SMPU violations. SMPU_CTL RLOCK (R/W) RSDIS (R/W) RCTLn, RADDRn, RIDxn and RIDMxn Read Speculation Disable Registers Lock Bit PBEDIS (R/W) PINTEN (R/W) Protection Violation Bus Error Disable Protection Violation Interrupt Enable PBETYPE (R/W) Protection Violation Bus Error Type...
Page 554 ADSP-SC58x SMPU Register Descriptions Table 13-8: SMPU_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PINTEN Protection Violation Interrupt Enable. (R/W) The SMPU_CTL.PINTEN bit controls whether or not an interrupt is generated when a protection violation occurs. 0 Protection Violation IRQ Disable. The protection viola- tion interrupt is disabled.
Page 555 ADSP-SC58x SMPU Register Descriptions Exclusive Access IDn Address register provides the address ID of an exclusive access. SMPU_EXACADD[n] VALUE[15:0] (R) Exclusive Access IDn Address VALUE[31:16] (R) Exclusive Access IDn Address Figure 13-5: SMPU_EXACADD[n] Register Diagram Table 13-9: SMPU_EXACADD[n] Register Fields Bit No.
Page 556 ADSP-SC58x SMPU Register Descriptions Exclusive Access Status register provides the exclusive access ID, read size and read length as well as the indi- SMPU_EXACSTAT[n] cation that the access was valid. ARID[7:0] (R) VALID (R) Exclusive Access ID Valid Exclusive Access Read ARSIZE (R) ARLEN (R) Exclusive Access Read Size...
Page 557 ADSP-SC58x SMPU Register Descriptions Interrupt Address Register register indicates an attempt to make a read or write access to unimplemented addresses or ac- SMPU_IADDR cesses are non-aligned. The SMPU issues a bus error for this condition. VALUE[15:0] (R) Interrupt Address VALUE[31:16] (R) Interrupt Address Figure 13-7: SMPU_IADDR Register Diagram...
Page 558 ADSP-SC58x SMPU Register Descriptions Interrupt Details Register register provides the ID of the last signaled interrupt, whether the interrupt was caused by a SMPU_IDTLS read or write, and whether the transaction that caused the last signaled interrupt was secure. ID[7:0] (R) SECURE (R) ID of Transaction Secure Status...
Page 559 ADSP-SC58x SMPU Register Descriptions Region n Address Register register is used to define the base address for a memory region to be protected. SMPU_RADDR[n] BADDR[3:0] (R/W) Region n Base Address 20 Most Significant Bits BADDR[19:4] (R/W) Region n Base Address 20 Most Significant Bits Figure 13-9: SMPU_RADDR[n] Register Diagram Table 13-13: SMPU_RADDR[n] Register Fields...
Page 560 ADSP-SC58x SMPU Register Descriptions Region n Control Register register is used to define the level of protection for a region of memory. The protection of a SMPU_RCTL[n] region is controlled and defined by this register and the SMPU_RADDR[n], SMPU_RIDA[n], SMPU_RIDB[n], SMPU_RIDMSKA[n], and SMPU_RIDMSKB[n] registers.
Page 561 ADSP-SC58x SMPU Register Descriptions Table 13-14: SMPU_RCTL[n] Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) RPROTEN Read Transaction Protection Enable. (R/W) The SMPU_RCTL[n].RPROTEN bit enable bit to turn on protection against ID- based read transactions for the memory region. 0 Read transaction ID-based protection disabled 1 Read transaction ID-based protection enabled SIZE...
Page 562 ADSP-SC58x SMPU Register Descriptions Table 13-14: SMPU_RCTL[n] Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Region Enable. (R/W) The SMPU_RCTL[n].EN bit enables the protection of a region. 0 Disabled 1 Enabled 13–26 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference...
Page 563 ADSP-SC58x SMPU Register Descriptions SMPU Revision ID Register register provides the major and minor revision numbers of this module. SMPU_REVID MAJOR (R) REV (R) Major Version ID Incremental Version ID Figure 13-11: SMPU_REVID Register Diagram Table 13-15: SMPU_REVID Register Fields Bit No.
Page 564 ADSP-SC58x SMPU Register Descriptions Region n ID A Register register is used for ID comparison 'A'. This comparison is performed after a mask is applied SMPU_RIDA[n] to both the transaction ID (from either the read or write IDs) and the register value. An ID match means that the ID is the exception to the rule and the read or write is allowed even if the region is read or write-protected.
Page 565 ADSP-SC58x SMPU Register Descriptions Region n ID B Register register is used for ID comparison 'B'. This comparison is performed after a mask is applied SMPU_RIDB[n] to both the transaction ID (from either the read or write IDs) and the register value. An ID match means that the ID is the exception to the rule and the read or write is allowed even if the region is read or write-protected.
Page 566 ADSP-SC58x SMPU Register Descriptions Region n ID Mask A Register register is used for ID comparison 'A'. The mask allows or disallows certain IDs from SMPU_RIDMSKA[n] affecting the final result of the ID match. For more details, refer to the ID Comparison section. MSK (R/W) Region n ID Mask Register A Figure 13-14: SMPU_RIDMSKA[n] Register Diagram...
Page 567 ADSP-SC58x SMPU Register Descriptions Region n ID Mask B Register register is used for ID comparison 'B'. The mask allows or disallows certain IDs from SMPU_RIDMSKB[n] affecting the final result of the ID match. For more details, refer to the ID Comparison section. MSK (R/W) Region n ID Mask Register B Figure 13-15: SMPU_RIDMSKB[n] Register Diagram...
Page 568 ADSP-SC58x SMPU Register Descriptions SMPU Control Secure Accesses Register register provides the bits required to set up the security settings for the processor. These SMPU_SECURECTL settings includes error generation and read/write security. WSECDIS (R/W) SBEDIS (R/W) Secure Write Transaction Disable Security Violation Bus Error Disable WNSEN (R/W) SBETYPE (R/W)
Page 569 ADSP-SC58x SMPU Register Descriptions Table 13-20: SMPU_SECURECTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) RSECDIS Secure Read Transaction Disable. (R/W) The SMPU_SECURECTL.RSECDIS bit disables secure read transactions. 0 Enable secure read transactions 1 Disable secure read transactions RNSEN Non-secure Read Transaction Enable.
Page 570 ADSP-SC58x SMPU Register Descriptions Region n Control Secure Accesses Register register contains bits that configure read/write security for a specific region. SMPU_SECURERCTL[n] WSECDIS (R/W) RNSEN (R/W) Secure Write Transaction Disable Non-secure Read Transaction Enable WNSEN (R/W) RSECDIS (R/W) Non-secure Write Transaction Enable Secure Read Transaction Disable Figure 13-17: SMPU_SECURERCTL[n] Register Diagram Table 13-21: SMPU_SECURERCTL[n] Register Fields...
Page 571 ADSP-SC58x SMPU Register Descriptions SMPU Status Register register provides the state of the SMPU and indicates various errors. All bits in this register are SMPU_STAT write 1 to clear. BEOVR (R/W1C) IRQ (R/W1C) Bus Error Overrun Interrupt Request BERR (R/W1C) IOVR (R/W1C) Bus Error Interrupt Overrun...
Page 572 ADSP-SC58x SMPU Register Descriptions Table 13-22: SMPU_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) BERR Bus Error. (R/W1C) This SMPU_STAT.BERR bit indicates if a bus error was generated. 0 No Bus Error since this bit has been cleared 1 Bus Error has been generated IOVR Interrupt Overrun.
Page 573 General-Purpose Ports (PORT) 14 General-Purpose Ports (PORT) This section describes general-purpose ports, pin multiplexing, general-purpose input/output (GPIO) functionality, and pin interrupts. The general-purpose ports provide the following three functions: • Pin multiplexing scheme • GPIO functionality • Pin interrupt requests In this chapter, the naming convention for registers and bits omits the alphabetic group enumeration NOTE: to refer to any and all of the ports.
Page 574 PORT Features PORT Features The PORTs include the following features: • Input mode, output mode, and open-drain mode of GPIO operation • Port multiplexing controlled on a pin-by-pin basis • No external glue hardware required for unused pins • All port pins provide interrupt request functionality •...
Page 575 PORT Functional Description ADSP-SC58x PORT Register List The PORT module (PORT) regulates the use of the multiplexable processor pins. Every port pin can operate in general-purpose I/O (GPIO) mode or as an alternate function. This GPIO operation is the default after processor reset and is controlled by a set of registers that control GPIO functionality.
Page 576 PORT Functional Description Table 14-2: ADSP-SC58x PINT Register List Name Description PINT_ASSIGN PINT Assign Register PINT_EDGE_CLR PINT Edge Clear Register PINT_EDGE_SET PINT Edge Set Register PINT_INV_CLR PINT Invert Clear Register PINT_INV_SET PINT Invert Set Register PINT_LATCH PINT Latch Register PINT_MSK_CLR PINT Mask Clear Register PINT_MSK_SET PINT Mask Set Register...
Page 577 PORT Functional Description Table 14-5: ADSP-SC58x PINT Trigger List Slaves Trigger ID Name Description Sensitivity None ADSP-SC58x PADS Register List The PADS controls signal hysteresis and other system interface signal features for a number of module interfaces. Table 14-6: ADSP-SC58x PADS Register List Name Description PADS_DAI0_IE...
Page 578 GPIO Functionality However, the input signal does not overwrite the state of the internal flip-flop used for providing output to the same pin. Only software can alter the state. If the input driver is enabled, a write to the PORT_DATA register can alter the state of the flip-flop, but the change cannot be read back.
Page 579 PORT Event Control Pairs of bits in the PORT_MUX register control the multiplexing between the peripheral functions available to an individual pin, as some PORT pins provide up to four possible peripheral functions. Refer to the Signal Muxing table in the datasheet for the specific PORT_MUX settings.
Page 580 PORT Event Control IRQ18 IRQ21 PINT2 PINT5 BYTE3 BYTE2 BYTE1 BYTE0 BYTE3 BYTE2 BYTE1 BYTE0 IRQ17 IRQ20 PINT1 PINT4 BYTE3 BYTE3 BYTE2 BYTE1 BYTE0 BYTE2 BYTE1 BYTE0 IRQ16 IRQ19 PINT0 PINT3 BYTE3 BYTE2 BYTE1 BYTE0 BYTE3 BYTE2 BYTE1 BYTE0 Figure 14-3: ADSP-SC57x/SC58x PINTx Block Diagram As shown in the PINTx Block Diagram, each port is subdivided into two 8-pin half ports, upper (PxH) and lower (PxL).
Page 581 PORT Programming Model the half ports needs to have the inversion enabled in the PINT_INV_SET register. The servicing software routine can then detect from the register whether a falling, rising, or both edges have occurred. PINT_LATCH Regardless of whether level-sensitive or edge-sensitive mode is used, the hardware always latches an interrupt request. Latched signals can be read from the registers.
Page 582 PORT Programming Model START PERIPHERAL GPIO OR WRITE PORT_FER PERIPHERAL TO ENABLE FEATURE GPIO WRITE PORT_FER TO CLEAR REQUIRED BITS (OPTIONAL IF WRITE PORT_MUX PORT_FER HAS NOT BEEN MODIFIED AFTER RESET TO SELECT PERIPHERAL INPUT/ SEE PERIPHERAL OUTPUT OPEN-DRAIN GPIO OUTPUT OR FOR MORE DETAILS INPUT/OPEN-DRAIN CLEAR...
Page 583 PORT Programming Model INPUT OR OPEN DRAIN INPUT OPEN DRAIN** WRITE PORT_DATA_CLR FOR REQUIRED PINS PIN POLARITY INVERTED* WRITE PORT_INEN_SET TO SET APPROPRIATE BITS TO ENABLE THE INPUT DRIVERS WRITE PINT_INV_CLR WRITE PINT_INV_SET TO INVERT THE POLARITY OF TO DISABLE THE INVERTERS ON THE APPROPRIATE PINS THE APPROPRIATE PINS NOT ACTIVE...
Page 584 ADSP-SC58x PORT Register Descriptions REGISTER ISR TO REQUIRED EVTX ASSIGN PINTx TO REQUIRED IVGX UNMASK PINTx INTERRUPT UNMASK EVT_IVGX ASSIGN PORT PINS TO APPROPRIATE PINTx BLOCK WRITE PINT_EDGE_CLEAR LEVEL EDGE OR EDGE WRITE PINT_EDGE_SET TO SET APPROPRIATE BITS FOR LEVEL SENSITIVE TO SET APPROPRIATE BITS FOR LEVEL SENSITIVITY EDGE SENSITIVITY...
Page 585 ADSP-SC58x PORT Register Descriptions Table 14-7: ADSP-SC58x PORT Register List (Continued) Name Description PORT_INEN Port x GPIO Input Enable Register PORT_INEN_CLR Port x GPIO Input Enable Clear Register PORT_INEN_SET Port x GPIO Input Enable Set Register PORT_LOCK Port x GPIO Lock Register PORT_MUX Port x Multiplexer Control Register PORT_POL...
Page 586 ADSP-SC58x PORT Register Descriptions Port x GPIO Data Register The operation of the register depends on whether the bit/pin is in output mode or input mode. In PORT_DATA both modes, a set bit in the PORT_DATA register corresponds to a signal high on a GPIO pin. A cleared bit in the PORT_DATA register corresponds to a signal low on a GPIO pin.
Page 587 ADSP-SC58x PORT Register Descriptions Table 14-8: PORT_DATA Register Fields Bit No. Bit Name Description/Enumeration (Access) PX15 Port x Bit 15 Data. (R/W) The PORT_DATA.PX15 bit indicates a signal on a GPIO pin. 0 Signal Low 1 Signal High PX14 Port x Bit 14 Data. (R/W) The PORT_DATA.PX14 bit indicates a signal on a GPIO pin.
Page 588 ADSP-SC58x PORT Register Descriptions Table 14-8: PORT_DATA Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 8 Data. (R/W) The PORT_DATA.PX8 bit indicates a signal on a GPIO pin. 0 Signal Low 1 Signal High Port x Bit 7 Data. (R/W) The PORT_DATA.PX7 bit indicates a signal on a GPIO pin.
Page 589 ADSP-SC58x PORT Register Descriptions Table 14-8: PORT_DATA Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 1 Data. (R/W) The PORT_DATA.PX1 bit indicates a signal on a GPIO pin. 0 Signal Low 1 Signal High Port x Bit 0 Data. (R/W) The PORT_DATA.PX0 bit indicates a signal on a GPIO pin.
Page 590 ADSP-SC58x PORT Register Descriptions Port x GPIO Data Clear Register register operates differently for port bits/pins, depending on whether the bit/pin is output PORT_DATA_CLR mode or input mode. For more information, see the PORT_DATA register description. PX15 (R/W1C) PX0 (R/W1C) Port x Bit 15 Data Clear Port x Bit 0 Data Clear PX14 (R/W1C)
Page 591 ADSP-SC58x PORT Register Descriptions Table 14-9: PORT_DATA_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PX13 Port x Bit 13 Data Clear. (R/W1C) The PORT_DATA_CLR.PX13 bit clears the pin without impacting other pins of the port. 0 No Effect. Write 0 has no effect in output mode. 1 Clear Bit.
Page 592 ADSP-SC58x PORT Register Descriptions Table 14-9: PORT_DATA_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 7 Data Clear. (R/W1C) The PORT_DATA_CLR.PX7 bit clears the pin without impacting other pins of the port. 0 No Effect. Write 0 has no effect in output mode. 1 Clear Bit.
Page 593 ADSP-SC58x PORT Register Descriptions Table 14-9: PORT_DATA_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 1 Data Clear. (R/W1C) The PORT_DATA_CLR.PX1 bit clears the pin without impacting other pins of the port. 0 No Effect. Write 0 has no effect in output mode. 1 Clear Bit.
Page 594 ADSP-SC58x PORT Register Descriptions Port x GPIO Data Set Register register operates differently for port bits/pins, depending on whether the bit/pin is output PORT_DATA_SET mode or input mode. For more information, see the PORT_DATA register description. PX15 (R/W1S) PX0 (R/W1S) Port x Bit 15 Data Set Port x Bit 0 Data Set PX14 (R/W1S)
Page 595 ADSP-SC58x PORT Register Descriptions Table 14-10: PORT_DATA_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PX12 Port x Bit 12 Data Set. (R/W1S) 0 No Effect. Write 0 has no effect in output mode. 1 Set Bit. Write 1 for signal high in output mode. PX11 Port x Bit 11 Data Set.
Page 596 ADSP-SC58x PORT Register Descriptions Table 14-10: PORT_DATA_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 2 Data Set. (R/W1S) 0 No Effect. Write 0 has no effect in output mode. 1 Set Bit. Write 1 for signal high in output mode. Port x Bit 1 Data Set.
Page 597 ADSP-SC58x PORT Register Descriptions Port x GPIO Output Toggle Register register permits toggling the state of output GPIO pins. Setting bits in the PORT_DATA_TGL PORT_DATA_TGL register affects the state of specific pins without impacting other pins of the port. Reading the PORT_DATA_TGL returns the state of the PORT_DATA...
Page 598 ADSP-SC58x PORT Register Descriptions Table 14-11: PORT_DATA_TGL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PX13 Port x Bit 13 Toggle. (R/W) The PORT_DATA_TGL.PX13 bit toggles the output GPIO bit/pin state. 0 No Effect 1 Toggle Bit PX12 Port x Bit 12 Toggle. (R/W) The PORT_DATA_TGL.PX12 bit toggles the output GPIO bit/pin state.
Page 599 ADSP-SC58x PORT Register Descriptions Table 14-11: PORT_DATA_TGL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 6 Toggle. (R/W) The PORT_DATA_TGL.PX6 bit toggles the output GPIO bit/pin state. 0 No Effect 1 Toggle Bit Port x Bit 5 Toggle. (R/W) The PORT_DATA_TGL.PX5 bit toggles the output GPIO bit/pin state.
Page 600 ADSP-SC58x PORT Register Descriptions Port x GPIO Direction Register The PORT_DIR, PORT_DIR_SET, and registers select output or input mode for GPIO pins PORT_DIR_CLR and enable output drivers. Use the PORT_INEN, PORT_INEN_SET, and PORT_INEN_CLR registers to enable or disable input drivers. Writes to the PORT_DIR register affect the state of all pins of the port.
Page 601 ADSP-SC58x PORT Register Descriptions PX15 (R/W) PX0 (R/W) Port x Bit 15 Direction Port x Bit 0 Direction PX14 (R/W) PX1 (R/W) Port x Bit 14 Direction Port x Bit 1 Direction PX13 (R/W) PX2 (R/W) Port x Bit 13 Direction Port x Bit 2 Direction PX12 (R/W) PX3 (R/W)
Page 602 ADSP-SC58x PORT Register Descriptions Table 14-12: PORT_DIR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PX11 Port x Bit 11 Direction. (R/W) 0 Input mode. The output driver is disabled. 1 Output mode. The output driver is enabled. PX10 Port x Bit 10 Direction.
Page 603 ADSP-SC58x PORT Register Descriptions Table 14-12: PORT_DIR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 1 Direction. (R/W) 0 Input mode. The output driver is disabled. 1 Output mode. The output driver is enabled. Port x Bit 0 Direction. (R/W) 0 Input mode.
Page 604 ADSP-SC58x PORT Register Descriptions Port x GPIO Direction Clear Register register disables output mode and disables the output drivers for GPIO pins. For more in- PORT_DIR_CLR formation, see the PORT_DIR register description. PX15 (R/W1C) PX0 (R/W1C) Port x Bit 15 Direction Clear Port x Bit 0 Direction Clear PX14 (R/W1C) PX1 (R/W1C)
Page 605 ADSP-SC58x PORT Register Descriptions Table 14-13: PORT_DIR_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PX13 Port x Bit 13 Direction Clear. (R/W1C) The PORT_DIR_CLR.PX13 bit disables output mode and the output drivers for port x. 0 No Effect 1 Disable output mode/driver PX12 Port x Bit 12 Direction Clear.
Page 606 ADSP-SC58x PORT Register Descriptions Table 14-13: PORT_DIR_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 7 Direction Clear. (R/W1C) The PORT_DIR_CLR.PX7 bit disables output mode and the output drivers for port 0 No Effect 1 Disable output mode/driver Port x Bit 6 Direction Clear.
Page 607 ADSP-SC58x PORT Register Descriptions Table 14-13: PORT_DIR_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 1 Direction Clear. (R/W1C) The PORT_DIR_CLR.PX1 bit disables output mode and the output drivers for port 0 No Effect 1 Disable output mode/driver Port x Bit 0 Direction Clear.
Page 608 ADSP-SC58x PORT Register Descriptions Port x GPIO Direction Set Register register enables output mode and output drivers for GPIO pins. For more information, see PORT_DIR_SET PORT_DIR register description. PX15 (R/W1S) PX0 (R/W1S) Port x Bit 15 Direction Set Port x Bit 0 Direction Set PX14 (R/W1S) PX1 (R/W1S) Port x Bit 14 Direction Set...
Page 609 ADSP-SC58x PORT Register Descriptions Table 14-14: PORT_DIR_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PX13 Port x Bit 13 Direction Set. (R/W1S) The PORT_DIR_SET.PX13 bit enables the output mode/driver for port x. 0 No Effect 1 Enable output mode/driver PX12 Port x Bit 12 Direction Set.
Page 610 ADSP-SC58x PORT Register Descriptions Table 14-14: PORT_DIR_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 6 Direction Set. (R/W1S) The PORT_DIR_SET.PX6 bit enables the output mode/driver for port x. 0 No Effect 1 Enable output mode/driver Port x Bit 5 Direction Set.
Page 611 ADSP-SC58x PORT Register Descriptions Port x Function Enable Register register bits indicate each port bit's operating mode: general purpose I/O mode or peripheral PORT_FER mode. After reset, all pins default to GPIO mode. Setting a bit in the PORT_FER registers enables a peripheral module to take ownership of the pin.
Page 612 ADSP-SC58x PORT Register Descriptions Table 14-15: PORT_FER Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PX13 Port x Bit 13 Mode. (R/W) The PORT_FER.PX13 bit indicates the operating mode for port x. 0 GPIO Mode 1 Peripheral Mode PX12 Port x Bit 12 Mode.
Page 613 ADSP-SC58x PORT Register Descriptions Table 14-15: PORT_FER Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 6 Mode. (R/W) The PORT_FER.PX6 bit indicates the operating mode for port x. 0 GPIO Mode 1 Peripheral Mode Port x Bit 5 Mode. (R/W) The PORT_FER.PX5 bit indicates the operating mode for port x.
Page 614 ADSP-SC58x PORT Register Descriptions Port x Function Enable Clear Register register permits enabling GPIO mode for each bit and corresponding GPIO pin. Writing 1 PORT_FER_CLR to a bit in PORT_FER_CLR enables GPIO mode for the corresponding pin. PX15 (R/W1C) PX0 (R/W1C) Port x Bit 15 Mode Clear Port x Bit 0 Mode Clear PX14 (R/W1C)
Page 615 ADSP-SC58x PORT Register Descriptions Table 14-16: PORT_FER_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PX13 Port x Bit 13 Mode Clear. (R/W1C) The PORT_FER_CLR.PX13 bit enables GPIO mode. 0 No Effect 1 Set Bit for GPIO Mode PX12 Port x Bit 12 Mode Clear.
Page 616 ADSP-SC58x PORT Register Descriptions Table 14-16: PORT_FER_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 6 Mode Clear. (R/W1C) The PORT_FER_CLR.PX6 bit enables GPIO mode. 0 No Effect 1 Set Bit for GPIO Mode Port x Bit 5 Mode Clear. (R/W1C) The PORT_FER_CLR.PX5 bit enables GPIO mode.
Page 617 ADSP-SC58x PORT Register Descriptions Port x Function Enable Set Register register permits enabling peripheral mode for each bit and corresponding GPIO pin. Writ- PORT_FER_SET ing 1 to a bit in PORT_FER_SET enables peripheral mode for the corresponding pin. PX15 (R/W1S) PX0 (R/W1S) Port x Bit 15 Mode Set Port x Bit 0 Mode Set...
Page 618 ADSP-SC58x PORT Register Descriptions Table 14-17: PORT_FER_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PX13 Port x Bit 13 Mode Set. (R/W1S) The PORT_FER_SET.PX13 bit enables peripheral mode. 0 No Effect 1 Set Bit for Peripheral Mode PX12 Port x Bit 12 Mode Set.
Page 619 ADSP-SC58x PORT Register Descriptions Table 14-17: PORT_FER_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 6 Mode Set. (R/W1S) The PORT_FER_SET.PX6 bit enables peripheral mode. 0 No Effect 1 Set Bit for Peripheral Mode Port x Bit 5 Mode Set. (R/W1S) The PORT_FER_SET.PX5 bit enables peripheral mode.
Page 620 ADSP-SC58x PORT Register Descriptions Port x GPIO Input Enable Register The PORT_INEN, PORT_INEN_SET, and registers enable or disable input drivers, which are PORT_INEN_CLR required for using a GPIO pin in input mode. Writes to the register affect the input drivers for all pins of the port. To set or clear specific pin drivers PORT_INEN without impacting other pin drivers of the port, use the PORT_INEN_SET...
Page 621 ADSP-SC58x PORT Register Descriptions Table 14-18: PORT_INEN Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PX14 Port x Bit 14 Input Enable. (R/W) 0 Disable Input Driver 1 Enable Input Driver PX13 Port x Bit 13 Input Enable. (R/W) 0 Disable Input Driver 1 Enable Input Driver PX12...
Page 622 ADSP-SC58x PORT Register Descriptions Table 14-18: PORT_INEN Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 4 Input Enable. (R/W) 0 Disable Input Driver 1 Enable Input Driver Port x Bit 3 Input Enable. (R/W) 0 Disable Input Driver 1 Enable Input Driver Port x Bit 2 Input Enable.
Page 623 ADSP-SC58x PORT Register Descriptions Port x GPIO Input Enable Clear Register register disables the input drivers for GPIO pins. For more information, see the PORT_INEN_CLR PORT_INEN register description. PX15 (R/W1C) PX0 (R/W1C) Port x Bit 15 Input Enable Clear Port x Bit 0 Input Enable Clear PX14 (R/W1C) PX1 (R/W1C) Port x Bit 14 Input Enable Clear...
Page 624 ADSP-SC58x PORT Register Descriptions Table 14-19: PORT_INEN_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PX12 Port x Bit 12 Input Enable Clear. (R/W1C) 0 No Effect 1 Clear Bit. Set to disable the input driver. PX11 Port x Bit 11 Input Enable Clear. (R/W1C) 0 No Effect 1 Clear Bit.
Page 625 ADSP-SC58x PORT Register Descriptions Table 14-19: PORT_INEN_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 2 Input Enable Clear. (R/W1C) 0 No Effect 1 Clear Bit. Set to disable the input driver. Port x Bit 1 Input Enable Clear. (R/W1C) 0 No Effect 1 Clear Bit.
Page 626 ADSP-SC58x PORT Register Descriptions Port x GPIO Input Enable Set Register register enables input drivers for GPIO pins. For more information, see the PORT_INEN_SET PORT_INEN register description. PX15 (R/W1S) PX0 (R/W1S) Port x Bit 15 Input Enable Set Port x Bit 0 Input Enable Set PX14 (R/W1S) PX1 (R/W1S) Port x Bit 14 Input Enable Set...
Page 627 ADSP-SC58x PORT Register Descriptions Table 14-20: PORT_INEN_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PX12 Port x Bit 12 Input Enable Set. (R/W1S) 0 No Effect 1 Set Bit. Set to enable the input driver. PX11 Port x Bit 11 Input Enable Set. (R/W1S) 0 No Effect 1 Set Bit.
Page 628 ADSP-SC58x PORT Register Descriptions Table 14-20: PORT_INEN_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 2 Input Enable Set. (R/W1S) 0 No Effect 1 Set Bit. Set to enable the input driver. Port x Bit 1 Input Enable Set. (R/W1S) 0 No Effect 1 Set Bit.
Page 629 ADSP-SC58x PORT Register Descriptions Port x GPIO Lock Register register enables (unlocks) or disables (locks) write access selectively for the PORT control regis- PORT_LOCK ters. POLAR (R/W) FER (R/W) Polarity Lock Function Enable Lock INEN (R/W) MUX (R/W) Input Enable Lock Function Multiplexer Lock DIR (R/W) DATA (R/W)
Page 630 ADSP-SC58x PORT Register Descriptions Table 14-21: PORT_LOCK Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Direction Lock. (R/W) The PORT_LOCK.DIR disables write access to the PORT_DIR, PORT_DIR_SET, PORT_DIR_CLR registers. 0 Unlock DIR 1 Lock DIR DATA Data, TGL Lock. (R/W) The PORT_LOCK.DATA disables write access to the PORT_DATA, PORT_DATA_SET, PORT_DATA_CLR, and...
Page 631 ADSP-SC58x PORT Register Descriptions Port x Multiplexer Control Register When a pin is in peripheral mode (not GPIO mode), the register controls which peripheral takes own- PORT_MUX ership of a pin. Ports may have multiple, different peripheral functions. Two bits are required to describe every mul- tiplexer on an individual pin-by-pin scheme.
Page 632 ADSP-SC58x PORT Register Descriptions Table 14-22: PORT_MUX Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 29:28 MUX14 Mux for Port x Bit 14. (R/W) The PORT_MUX.MUX14 bit provides multiplexer control for port x bit 14. 27:26 MUX13 Mux for Port x Bit 13. (R/W) The PORT_MUX.MUX13 bit provides multiplexer control for port x bit 13.
Page 633 ADSP-SC58x PORT Register Descriptions Port x GPIO Polarity Invert Register The PORT_POL, PORT_POL_SET, and registers enable or disable inverting polarity of GPIO PORT_POL_CLR signals. To invert polarity of peripheral signals, use the inversion selection programming in the signal's correspond- ing module. Writes to the register affect the polarity inversion selection of all pins of the port.
Page 634 ADSP-SC58x PORT Register Descriptions Table 14-23: PORT_POL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PX14 Port x Bit 14 Polarity Invert. (R/W) The PORT_POL.PX14 bit enables polarity inversion. 0 No Invert. GPIO is active high or rising edge sensitive. 1 Invert.
Page 635 ADSP-SC58x PORT Register Descriptions Table 14-23: PORT_POL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 7 Polarity Invert. (R/W) The PORT_POL.PX7 bit enables polarity inversion. 0 No Invert. GPIO is active high or rising edge sensitive. 1 Invert.
Page 636 ADSP-SC58x PORT Register Descriptions Table 14-23: PORT_POL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 0 Polarity Invert. (R/W) The PORT_POL.PX0 bit enables polarity inversion. 0 No Invert. GPIO is active high or rising edge sensitive. 1 Invert.
Page 637 ADSP-SC58x PORT Register Descriptions Port x GPIO Polarity Invert Clear Register register disables polarity inversion for GPIO pins. For more information, see the PORT_POL_CLR PORT_POL register description. PX15 (R/W1C) PX0 (R/W1C) Port x Bit 15 Polarity Invert Clear Port x Bit 0 Polarity Invert Clear PX14 (R/W1C) PX1 (R/W1C) Port x Bit 14 Polarity Invert Clear...
Page 638 ADSP-SC58x PORT Register Descriptions Table 14-24: PORT_POL_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PX12 Port x Bit 12 Polarity Invert Clear. (R/W1C) 0 No Effect 1 Clear Bit. Set to disable GPIO pin polarity invert. PX11 Port x Bit 11 Polarity Invert Clear. (R/W1C) 0 No Effect 1 Clear Bit.
Page 639 ADSP-SC58x PORT Register Descriptions Table 14-24: PORT_POL_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 2 Polarity Invert Clear. (R/W1C) 0 No Effect 1 Clear Bit. Set to disable GPIO pin polarity invert. Port x Bit 1 Polarity Invert Clear. (R/W1C) 0 No Effect 1 Clear Bit.
Page 640 ADSP-SC58x PORT Register Descriptions Port x GPIO Polarity Invert Set Register register enables polarity inversion for GPIO pins. For more information, see the PORT_POL_SET PORT_POL register description. PX15 (R/W1S) PX0 (R/W1S) Port x Bit 15 Polarity Invert Set Port x Bit 0 Polarity Invert Set PX14 (R/W1S) PX1 (R/W1S) Port x Bit 14 Polarity Invert Set...
Page 641 ADSP-SC58x PORT Register Descriptions Table 14-25: PORT_POL_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PX13 Port x Bit 13 Polarity Invert Set. (R/W1S) The PORT_POL_SET.PX13 bit enables pin polarity inversion. 0 No Effect 1 Set Bit. Set to enable GPIO pin polarity invert. PX12 Port x Bit 12 Polarity Invert Set.
Page 642 ADSP-SC58x PINT Register Descriptions Table 14-25: PORT_POL_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Port x Bit 6 Polarity Invert Set. (R/W1S) The PORT_POL_SET.PX6 bit enables pin polarity inversion. 0 No Effect 1 Set Bit. Set to enable GPIO pin polarity invert. Port x Bit 5 Polarity Invert Set.
Page 643 ADSP-SC58x PINT Register Descriptions Table 14-26: ADSP-SC58x PINT Register List Name Description PINT_ASSIGN PINT Assign Register PINT_EDGE_CLR PINT Edge Clear Register PINT_EDGE_SET PINT Edge Set Register PINT_INV_CLR PINT Invert Clear Register PINT_INV_SET PINT Invert Set Register PINT_LATCH PINT Latch Register PINT_MSK_CLR PINT Mask Clear Register PINT_MSK_SET...
Page 644 ADSP-SC58x PINT Register Descriptions PINT Assign Register register controls the pin-to-interrupt request assignment in a byte-wide manner. This register PINT_ASSIGN consists of four control bytes that each function as a multiplexer control. The PINT ports are subdivided into 8-bit half ports, resulting in lower and upper half 8-bit units. Using the multi- plexers controlled by the register, the lower half units of eight pins can be forwarded to either byte PINT_ASSIGN...
Page 645 ADSP-SC58x PINT Register Descriptions PINT Edge Clear Register register permits selecting level-sensitive interrupts. Writing 1 to a bit in PINT_EDGE_CLR PINT_EDGE_CLR enables level sensitivity for the corresponding pin interrupt. PIQ15 (R/W1C) PIQ0 (R/W1C) Pin Interrupt 15 Level Pin Interrupt 0 Level PIQ14 (R/W1C) PIQ1 (R/W1C) Pin Interrupt 14 Level...
Page 646 ADSP-SC58x PINT Register Descriptions Table 14-28: PINT_EDGE_CLR Register Fields Bit No. Bit Name Description/Enumeration (Access) PIQ31 Pin Interrupt 31 Level. (R/W1C) Set the PINT_EDGE_CLR.PIQ31 bit to enable level sensitivity. PIQ30 Pin Interrupt 30 Level. (R/W1C) Set the PINT_EDGE_CLR.PIQ30 bit to enable level sensitivity. PIQ29 Pin Interrupt 29 Level.
Page 647 ADSP-SC58x PINT Register Descriptions Table 14-28: PINT_EDGE_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PIQ15 Pin Interrupt 15 Level. (R/W1C) Set the PINT_EDGE_CLR.PIQ15 bit to enable level sensitivity. PIQ14 Pin Interrupt 14 Level. (R/W1C) Set the PINT_EDGE_CLR.PIQ14 bit to enable level sensitivity. PIQ13 Pin Interrupt 13 Level.
Page 648 ADSP-SC58x PINT Register Descriptions PINT Edge Set Register register permits selecting edge-sensitive interrupts. Writing 1 to a bit in PINT_EDGE_SET PINT_EDGE_SET enables edge sensitivity for the corresponding pin interrupt. PIQ15 (R/W1S) PIQ0 (R/W1S) Pin Interrupt 15 Edge Pin Interrupt 0 Edge PIQ14 (R/W1S) PIQ1 (R/W1S) Pin Interrupt 14 Edge...
Page 649 ADSP-SC58x PINT Register Descriptions Table 14-29: PINT_EDGE_SET Register Fields Bit No. Bit Name Description/Enumeration (Access) PIQ31 Pin Interrupt 31 Edge. (R/W1S) Set the PINT_EDGE_SET.PIQ31 bit to enable edge sensitivity. PIQ30 Pin Interrupt 30 Edge. (R/W1S) Set the PINT_EDGE_SET.PIQ30 bit to enable edge sensitivity. PIQ29 Pin Interrupt 29 Edge.
Page 650 ADSP-SC58x PINT Register Descriptions Table 14-29: PINT_EDGE_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PIQ15 Pin Interrupt 15 Edge. (R/W1S) Set the PINT_EDGE_SET.PIQ15 bit to enable edge sensitivity. PIQ14 Pin Interrupt 14 Edge. (R/W1S) Set the PINT_EDGE_SET.PIQ14 bit to enable edge sensitivity. PIQ13 Pin Interrupt 13 Edge.
Page 651 ADSP-SC58x PINT Register Descriptions PINT Invert Clear Register register disables inverting input polarity. Writing 1 to a bit in disables an PINT_INV_CLR PINT_INV_CLR inverter for input on the corresponding pin. PIQ15 (R/W1C) PIQ0 (R/W1C) Pin Interrupt 15 No Invert Pin Interrupt 0 No Invert PIQ14 (R/W1C) PIQ1 (R/W1C) Pin Interrupt 14 No Invert...
Page 652 ADSP-SC58x PINT Register Descriptions Table 14-30: PINT_INV_CLR Register Fields Bit No. Bit Name Description/Enumeration (Access) PIQ31 Pin Interrupt 31 No Invert. (R/W1C) Set the PINT_INV_CLR.PIQ31 bit to disable inverted input. PIQ30 Pin Interrupt 30 No Invert. (R/W1C) Set the PINT_INV_CLR.PIQ30 bit to disable inverted input. PIQ29 Pin Interrupt 29 No Invert.
Page 653 ADSP-SC58x PINT Register Descriptions Table 14-30: PINT_INV_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PIQ15 Pin Interrupt 15 No Invert. (R/W1C) Set the PINT_INV_CLR.PIQ15 bit to disable inverted input. PIQ14 Pin Interrupt 14 No Invert. (R/W1C) Set the PINT_INV_CLR.PIQ14 bit to disable inverted input. PIQ13 Pin Interrupt 13 No Invert.
Page 654 ADSP-SC58x PINT Register Descriptions PINT Invert Set Register register enables inverting input polarity. Writing 1 to a bit in enables an PINT_INV_SET PINT_INV_SET inverter for input on the corresponding pin. PIQ15 (R/W1S) PIQ0 (R/W1S) Pin Interrupt 15 Invert Pin Interrupt 0 Invert PIQ14 (R/W1S) PIQ1 (R/W1S) Pin Interrupt 14 Invert...
Page 655 ADSP-SC58x PINT Register Descriptions Table 14-31: PINT_INV_SET Register Fields Bit No. Bit Name Description/Enumeration (Access) PIQ31 Pin Interrupt 31 Invert. (R/W1S) Set the PINT_INV_SET.PIQ31 bit to enable inverted input. PIQ30 Pin Interrupt 30 Invert. (R/W1S) Set the PINT_INV_SET.PIQ30 bit to enable inverted input. PIQ29 Pin Interrupt 29 Invert.
Page 656 ADSP-SC58x PINT Register Descriptions Table 14-31: PINT_INV_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PIQ15 Pin Interrupt 15 Invert. (R/W1S) Set the PINT_INV_SET.PIQ15 bit to enable inverted input. PIQ14 Pin Interrupt 14 Invert. (R/W1S) Set the PINT_INV_SET.PIQ14 bit to enable inverted input. PIQ13 Pin Interrupt 13 Invert.
Page 657 ADSP-SC58x PINT Register Descriptions PINT Latch Register register indicates the interrupt latch status for pin interrupts. When set, an interrupt request is PINT_LATCH latched. When cleared, there is no interrupt request latched. Both the registers indicate whether an interrupt request is latched on the respective PINT_REQ PINT_LATCH pin.
Page 658 ADSP-SC58x PINT Register Descriptions PIQ15 (R/W1C) PIQ0 (R/W1C) Pin Interrupt 15 Latch Pin Interrupt 0 Latch PIQ14 (R/W1C) PIQ1 (R/W1C) Pin Interrupt 14 Latch Pin Interrupt 1 Latch PIQ13 (R/W1C) PIQ2 (R/W1C) Pin Interrupt 13 Latch Pin Interrupt 2 Latch PIQ12 (R/W1C) PIQ3 (R/W1C) Pin Interrupt 12 Latch...
Page 659 ADSP-SC58x PINT Register Descriptions Table 14-32: PINT_LATCH Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PIQ30 Pin Interrupt 30 Latch. (R/W1C) If the PINT_LATCH.PIQ30 bit is set, the request is latched. PIQ29 Pin Interrupt 29 Latch. (R/W1C) If the PINT_LATCH.PIQ29 bit is set, the request is latched. PIQ28 Pin Interrupt 28 Latch.
Page 660 ADSP-SC58x PINT Register Descriptions Table 14-32: PINT_LATCH Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PIQ14 Pin Interrupt 14 Latch. (R/W1C) If the PINT_LATCH.PIQ14 bit is set, the request is latched. PIQ13 Pin Interrupt 13 Latch. (R/W1C) If the PINT_LATCH.PIQ13 bit is set, the request is latched. PIQ12 Pin Interrupt 12 Latch.
Page 661 ADSP-SC58x PINT Register Descriptions PINT Mask Clear Register register permits masking (disabling) of interrupt requests. Writing 1 to a bit in PINT_MSK_CLR PINT_MSK_CLR masks the corresponding pin interrupt. PIQ15 (R/W1C) PIQ0 (R/W1C) Pin Interrupt 15 Mask Pin Interrupt 0 Mask PIQ14 (R/W1C) PIQ1 (R/W1C) Pin Interrupt 14 Mask...
Page 662 ADSP-SC58x PINT Register Descriptions Table 14-33: PINT_MSK_CLR Register Fields Bit No. Bit Name Description/Enumeration (Access) PIQ31 Pin Interrupt 31 Mask. (R/W1C) Set the PINT_MSK_CLR.PIQ31 bit to disable the interrupt. PIQ30 Pin Interrupt 30 Mask. (R/W1C) Set the PINT_MSK_CLR.PIQ30 bit to disable the interrupt. PIQ29 Pin Interrupt 29 Mask.
Page 663 ADSP-SC58x PINT Register Descriptions Table 14-33: PINT_MSK_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PIQ15 Pin Interrupt 15 Mask. (R/W1C) Set the PINT_MSK_CLR.PIQ15 bit to disable the interrupt. PIQ14 Pin Interrupt 14 Mask. (R/W1C) Set the PINT_MSK_CLR.PIQ14 bit to disable the interrupt. PIQ13 Pin Interrupt 13 Mask.
Page 664 ADSP-SC58x PINT Register Descriptions PINT Mask Set Register register permits unmasking (enabling) of interrupt requests. Writing 1 to a bit in PINT_MSK_SET PINT_MSK_SET unmasks the corresponding pin interrupt. PIQ15 (R/W1S) PIQ0 (R/W1S) Pin Interrupt 15 Unmask Pin Interrupt 0 Unmask PIQ14 (R/W1S) PIQ1 (R/W1S) Pin Interrupt 14 Unmask...
Page 665 ADSP-SC58x PINT Register Descriptions Table 14-34: PINT_MSK_SET Register Fields Bit No. Bit Name Description/Enumeration (Access) PIQ31 Pin Interrupt 31 Unmask. (R/W1S) Set the PINT_MSK_SET.PIQ31 bit to enable the interrupt. PIQ30 Pin Interrupt 30 Unmask. (R/W1S) Set the PINT_MSK_SET.PIQ30 bit to enable the interrupt. PIQ29 Pin Interrupt 29 Unmask.
Page 666 ADSP-SC58x PINT Register Descriptions Table 14-34: PINT_MSK_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PIQ15 Pin Interrupt 15 Unmask. (R/W1S) Set the PINT_MSK_SET.PIQ15 bit to enable the interrupt. PIQ14 Pin Interrupt 14 Unmask. (R/W1S) Set the PINT_MSK_SET.PIQ14 bit to enable the interrupt. PIQ13 Pin Interrupt 13 Unmask.
Page 667 ADSP-SC58x PINT Register Descriptions PINT Pin State Register When a half port is assigned to a byte in any PINT block, the state of the eight pins (regardless of GPIO or func- tion, input or output) can be seen in the register.
Page 668 ADSP-SC58x PINT Register Descriptions PIQ15 (R) PIQ0 (R) Pin Interrupt 15 State Pin Interrupt 0 State PIQ14 (R) PIQ1 (R) Pin Interrupt 14 State Pin Interrupt 1 State PIQ13 (R) PIQ2 (R) Pin Interrupt 13 State Pin Interrupt 2 State PIQ12 (R) PIQ3 (R) Pin Interrupt 12 State...
Page 669 ADSP-SC58x PINT Register Descriptions Table 14-35: PINT_PINSTATE Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PIQ30 Pin Interrupt 30 State. (R/NW) A read of the PINT_PINSTATE.PIQ30 bit returns the pin state. PIQ29 Pin Interrupt 29 State. (R/NW) A read of the PINT_PINSTATE.PIQ29 bit returns the pin state. PIQ28 Pin Interrupt 28 State.
Page 670 ADSP-SC58x PINT Register Descriptions Table 14-35: PINT_PINSTATE Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PIQ14 Pin Interrupt 14 State. (R/NW) A read of the PINT_PINSTATE.PIQ14 bit returns the pin state. PIQ13 Pin Interrupt 13 State. (R/NW) A read of the PINT_PINSTATE.PIQ13 bit returns the pin state. PIQ12 Pin Interrupt 12 State.
Page 671 ADSP-SC58x PINT Register Descriptions PINT Request Register register indicates the interrupt request status for pin interrupts. When set, an interrupt request is PINT_REQ pending. When cleared, there is no interrupt request pending. Both the registers indicate whether an interrupt request is latched on the respective PINT_REQ PINT_LATCH pin.
Page 672 ADSP-SC58x PINT Register Descriptions PIQ15 (R/W1C) PIQ0 (R/W1C) Pin Interrupt 15 Request Pin Interrupt 0 Request PIQ14 (R/W1C) PIQ1 (R/W1C) Pin Interrupt 14 Request Pin Interrupt 1 Request PIQ13 (R/W1C) PIQ2 (R/W1C) Pin Interrupt 13 Request Pin Interrupt 2 Request PIQ12 (R/W1C) PIQ3 (R/W1C) Pin Interrupt 12 Request...
Page 673 ADSP-SC58x PINT Register Descriptions Table 14-36: PINT_REQ Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PIQ30 Pin Interrupt 30 Request. (R/W1C) If the PINT_REQ.PIQ30 bit is set, a request is pending. PIQ29 Pin Interrupt 29 Request. (R/W1C) If the PINT_REQ.PIQ29 bit is set, a request is pending. PIQ28 Pin Interrupt 28 Request.
Page 674 ADSP-SC58x PINT Register Descriptions Table 14-36: PINT_REQ Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PIQ14 Pin Interrupt 14 Request. (R/W1C) If the PINT_REQ.PIQ14 bit is set, a request is pending. PIQ13 Pin Interrupt 13 Request. (R/W1C) If the PINT_REQ.PIQ13 bit is set, a request is pending. PIQ12 Pin Interrupt 12 Request.
Page 675 ADSP-SC58x PADS Register Descriptions ADSP-SC58x PADS Register Descriptions Pads Controller (PADS) contains the following registers. Table 14-37: ADSP-SC58x PADS Register List Name Description PADS_DAI0_IE DAI0 Port Input Enable Control Register PADS_DAI1_IE DAI1 Port Input Enable Control Register PADS_PCFG0 Peripheral PAD Configuration0 Register ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference 14–103...
Page 676 ADSP-SC58x PADS Register Descriptions DAI0 Port Input Enable Control Register register configures input enable control of the DAI0 (20 pins) pads. If =0 implies input buf- PADS_DAI0_IE fer disable and if =1 implies enable. VALUE[14:0] (R/W) DAI0 Input Enable Control VALUE[19:15] (R/W) DAI0 Input Enable Control Figure 14-35: PADS_DAI0_IE Register Diagram...
Page 677 ADSP-SC58x PADS Register Descriptions DAI1 Port Input Enable Control Register register configures input enable control of the DAI1 (20 pins) pads. If =0 implies input buf- PADS_DAI1_IE fer disable and if =1 implies enable. VALUE[14:0] (R/W) DAI1 Input Enable Control VALUE[19:15] (R/W) DAI1 Input Enable Control Figure 14-36: PADS_DAI1_IE Register Diagram...
Page 678 ADSP-SC58x PADS Register Descriptions Peripheral PAD Configuration0 Register register provides several configuration options for the pads and multiplexing for peripherals. PADS_PCFG0 PUMSIHL (R/W) EMAC0 (R/W) Pull-Up Enable for MSI DATA[7:4] bits PTP Clock Source 0 PUMSIDLC (R/W) EMACRESET (R/W) Pull-Up Enable for MSI DATA[3:0] bits Reset Enable for RGMII and CMD Pin EMACPHYISEL (R/W)
Page 679 ADSP-SC58x PADS Register Descriptions Table 14-40: PADS_PCFG0 Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) TWI0VSEL TWI0 Voltage Select. (R/W) The PADS_PCFG0.TWI0VSEL bit selects the drive/tolerate voltage for the TWI_SCL and TWI_SDA pins for TWI0. By default this bit is cleared (=0, 3.3V). 0 TWI0 voltage is 3.3V 1 TWI0 voltage is 5.0V TWI1VSEL...
Page 680 ADSP-SC58x PADS Register Descriptions Table 14-40: PADS_PCFG0 Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) EMAC0 PTP Clock Source 0. (R/W) The PADS_PCFG0.EMAC0 selects the clock source for the PTP Block in EMAC0. 0 EMAC0_RMII CLK 1 SCLK 2 External Clock 3 SCLK 14–108 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference...
Page 681 Link Port (LP) 15 Link Port (LP) Link ports allow the processor to connect to other processors or peripheral link ports using a simple communication protocol for high-speed parallel data transfer. This peripheral allows various I/O peripheral interconnection schemes to I/O peripheral devices as well as co-processing and multiprocessing schemes. The link ports of the processor support 8-bit wide data transfers.
Page 682 LP Functional Description multiprocessing schemes. A set of registers governs LP operations. For more information on LP functionality, see the LP register descriptions. Table 15-1: ADSP-SC58x LP Register List Name Description LP_CTL Control Register LP_DIV Clock Divider Value Register LP_RX Receive Buffer Register LP_STAT Status Register...
Page 683 LP Functional Description ADSP-SC58x LP DMA Channel List Table 15-5: ADSP-SC58x LP DMA Channel List DMA ID DMA Channel Name Description DMA30 LP0_DMA LP0 DMA Channel DMA36 LP1_DMA LP1 DMA Channel Block Diagram The Link Port Block Diagram shows the block diagram of a link port. LDATx7-0 LACKx LCLKx...
Page 684 Block Diagram TRANSMITTER RECEIVER LPx_D7:0 LPx_D7:0 LPx_CLK LPx_CLK LPx_ACK LPx_ACK X DENOTES THE LINK PORT NUMBER, 0-1 Figure 15-2: Link Port Pin Connections Use external pull-downs for the LP_CLK and LP_ACK pins so that the link port can enable the transmitter and receiver, irrespective of the state of the other.
Page 685 Architectural Concepts 5. When this assertion occurs, the transmitter drives LP_CLK low. The transmission of the next word starts. If the transmit buffer is empty, LP_CLK remains low until the buffer refills, regardless of the state of LP_ACK. The LP_ACK signal can deassert when it anticipates that the buffer could fill. The receiver reasserts the LP_ACK signal as soon as the internal DMA grant signal has occurred or the core reads the receive buffer.
Page 686 Architectural Concepts 5. The receiver accepts the remaining word even if LP_ACK is deasserted. The transmitter does not send the fol- lowing word. 6. Transmission of data for next word is held until LP_ACK is asserted. The transmitter samples the LP_ACK signal. If the signal is high, the transmitter gives out the falling edges of LP_CLK for data sampling.
Page 687 Architectural Concepts SCLK LP_ACK driven by receiver LP_ACK synchronized at rising edge SCLK (2-stage) LP_CLK driven low if LP_ACK is sampled by the previous SCLK rise edge Figure 15-5: LP_ACK Synchronization for SCLK: LP_CLK=1:2, 1:4 and Up The link port uses the value programmed in the register at the transmitter to determine the frequency of LP_DIV the link port clock (LP_CLK).
Page 688 Architectural Concepts port is driving data from the shift register to the pins. The LP_STAT.LPBS bit is also set when receiver has held off transmission by driving LP_ACK low. When the 2-deep FIFO and the output shift-register overflow, any further write to the link port buffer NOTE: overwrites the input stage of the FIFO.
Page 689 Architectural Concepts shows how FIFO slots influence the acknowledge signal generation. The grayed sections show received data. The white sections show empty locations where the decision to pull LP_ACK high is taken. 32-BIT 32-BIT 8-BIT 24-BIT 32-BIT Figure 15-8: LACK Generation Based on Receive FIFO Status The link port uses a 4-deep receive FIFO only under a worst case situation, as mentioned.
Page 690 Architectural Concepts LPx_CLK driven by transmitter LPx_CLK held high until LPx_ACK goes high LPx_ACK driven by receiver LPx_ACK may deassert after BYTE 0 LPx_Dn BYTE 0 BYTE 1 BYTE 2 driven by transmitter Transmit data held until LPx_ACK is asserted Figure 15-9: Enable the Transmitter Before the Receiver NOTE: Service request interrupts or status are asserted only when the link port (receiver or transmitter) is disabled.
Page 691 Architectural Concepts PROCESSOR 1 PROCESSOR 2 CENTRAL PROCESSOR PROCESSOR 3 PROCESSOR 4 Figure 15-10: Central Processor-Based Model PROCESSOR 1 PROCESSOR 2 Figure 15-11: Link Port Full-Duplex Transfer Model PROCESSOR 1 PROCESSOR 4 PROCESSOR 2 PROCESSOR 3 Figure 15-12: Link Port Ring Model The link port protocol does not include built-in support for multiple masters.
Page 692 LP Operating Modes data transmission. If the master wishes to give up the token, it can send back a user-defined token release word and thereafter clear its token flag. Simultaneously, the slave examines the data sent back and if it is the token release word, the slave sets its token, and can thereafter transmit.
Page 693 LP Event Control the link port. The FIFO detects that there is room in the buffer and asserts another DMA request, continuing the process. LP Event Control This section describes how the link port uses interrupts and status signals. Interrupt Signals Each link port has two dedicated interrupt lines registered with the system event controller—a data request interrupt and a status interrupt.
Page 694 LP Event Control can read the LP_STAT register bits to determine the type of interrupt. These bits are write-one-to-clear (W1C); writing one to the bit resets the bit and disables the corresponding interrupt. Status and Error Signals This section explains the various status signals in the register.
Page 695 LP Programming Model 2. Install interrupt handlers for DMA and for transfer status (service request interrupt). 3. Configure the link port to transmit by setting the LP_CTL bit and enable the transmit request interrupt mask by setting the LP_CTL.TRQMSK bit. 4.
Page 696 LP Programming Model 6. Wait for the link port transmitter (connected externally) to be enabled with subsequent data transmission. The application can wait for the receive service request interrupt to assert. 7. Clear the receive service request interrupt status by writing 1 to the LP_STAT.LRRQ bit. 8.
Page 697 ADSP-SC58x LP Register Descriptions 5. Clear the receive service request interrupt status by writing 1 to the LP_STAT.LRRQ bit. 6. Enable the link port by setting the LP_CTL.EN bit. 7. The data request interrupt is asserted whenever there is free space in the FIFO. The application can read from register based on the FIFO conditions (1 or 2 or 3 data available) which is reflected in the LP_RX LP_STAT.FFST bit field.
Page 698 ADSP-SC58x LP Register Descriptions Control Register register provides LP interrupt masking, selection of transfer direction, and link port enable. LP_CTL ROVFMSK (R/W) EN (R/W) Receive FIFO Overflow Interrupt Mask Enable RRQMSK (R/W) TRAN (R/W) Receive Request Interrupt Mask Transfer Direction TRQMSK (R/W) Transmit Request Interrupt Mask Figure 15-13: LP_CTL Register Diagram...
Page 699 ADSP-SC58x LP Register Descriptions Table 15-7: LP_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Enable. (R/W) The LP_CTL.EN enables or disables the link port. When the processor disables the port (LP_CTL.EN transitions from high to low), the processor clears the correspond- LP_STAT bits.
Page 700 ADSP-SC58x LP Register Descriptions Clock Divider Value Register register selects the divisor for ratio between the internal LP clock (LCLK) and system clock LP_DIV (CDU0_CLKO8). This programming is applicable only for the transmitter. The receiver can operate at any asyn- chronous frequency up to the maximum frequency independent of the ratio programmed.
Page 701 ADSP-SC58x LP Register Descriptions Receive Buffer Register register buffers the receive data flow through the LP. The receive buffer is a four-location deep FIFO. LP_RX In the receive buffer, data is transferred to the core or DMA from the receive FIFO where an internal register does the packing.
Page 702 ADSP-SC58x LP Register Descriptions Status Register register provides status information on link port interrupts, FIFO, buses, and receive/transmit re- LP_STAT quests. LPBS (R) LTRQ (R/W1C) Bus Status Transmit Request LPACK (R) LRRQ (R/W1C) Buffer Pack Status Receive Request FFST (R) ROVF (R/W1C) FIFO Status Receive FIFO Overflow Interrupt...
Page 703 ADSP-SC58x LP Register Descriptions Table 15-10: LP_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 1 TX - Reserved ; RX - Has 1 data word RX has 1 word of data. TX reserved 2 TX - Reserved; RX - Has 2 data words RX has 2 word of data.
Page 704 ADSP-SC58x LP Register Descriptions Transmit Buffer Register register buffers the transmit data flow through the LP. The transmit buffer is two words deep. In the LP_TX transmit buffer, the input stage of the FIFO is used to accept core data or DMA data from internal memory, and the data is transferred to the link port interface from the output stage of the FIFO.
Page 705 ADSP-SC58x LP Register Descriptions Shadow Input Transmit Buffer Register register contains the same data as the input stage of the transmit buffer. Read of this shadow LP_TXIN_SHDW transmit buffer does not update the LP_STAT register. DATA[15:0] (R) Transmit Data Buffer Shadow Input Stage DATA[31:16] (R) Transmit Data Buffer Shadow Input...
Page 706 ADSP-SC58x LP Register Descriptions Shadow Output Transmit Buffer Register register contains the same data as the output stage of the transmit buffer. Read of this LP_TXOUT_SHDW shadow transmit buffer does not update the LP_STAT register. DATA[15:0] (R) Transmit Data Output Shadow Register DATA[31:16] (R) Transmit Data Output Shadow Register Figure 15-19: LP_TXOUT_SHDW Register Diagram...
Page 707 Serial Peripheral Interface (SPI) 16 Serial Peripheral Interface (SPI) The serial peripheral interface is an industry-standard synchronous serial link that supports communication with multiple SPI-compatible devices. The baseline SPI peripheral is a synchronous, four-wire interface consisting of two data pins, one device select pin, and a gated clock pin. The two data pins allow full-duplex operation to other SPI- compatible devices.
Page 708 SPI Functional Description • Burst transfer mode for non-DMA write accesses SPI Functional Description This section provides information on the function of the SPI module. Shift register functionality The SPI is essentially a shift register that serially transmits and receives data bits to or from other SPI devices. During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serial- ly).
Page 709 SPI Functional Description Table 16-1: ADSP-SC58x SPI Register List Name Description SPI_CLK Clock Rate Register SPI_CTL Control Register SPI_DLY Delay Register SPI_ILAT Masked Interrupt Condition Register SPI_ILAT_CLR Masked Interrupt Clear Register SPI_IMSK Interrupt Mask Register SPI_IMSK_CLR Interrupt Mask Clear Register SPI_IMSK_SET Interrupt Mask Set Register SPI_MMRDH...
Page 710 SPI Functional Description Table 16-2: ADSP-SC58x SPI Interrupt List (Continued) Interrupt Name Description Sensitivity Channel SPI0_STAT SPI0 Status Level SPI0_ERR SPI0 Error Level SPI1_TXDMA SPI1 TX DMA Channel Level SPI1_RXDMA SPI1 RX DMA Channel Level SPI1_STAT SPI1 Status Level SPI1_ERR SPI1 Error Level SPI2_TXDMA_ERR...
Page 711 SPI Functional Description Table 16-4: ADSP-SC58x SPI Trigger List Slaves (Continued) Trigger ID Name Description Sensitivity SPI2 RX DMA Channel Pulse SPI2_RXDMA ADSP-SC58x SPI DMA Channel List Table 16-5: ADSP-SC58x SPI DMA Channel List DMA ID DMA Channel Name Description DMA22 SPI0_TXDMA SPI0 TX DMA Channel...
Page 712 SPI Functional Description SPI_CLK SPI_RDY RFIFO TFIFO CONTROL AND STATUS REGISTERS DMA BUS PERIPHERAL BUS Figure 16-1: SPI Controller Block Diagram, Quad Mode Transfer Protocol The SPI module implements two channels that are independent of each other. The SPI module uses the SPI_RXCTL SPI_TXCTL dedicated control registers to control these channels.
Page 713 SPI Functional Description The clock polarity and the clock phase could be identical for the master device and the slave device involved in the communication link. The transfer format from the master can be changed between transfers to adjust for various requirements of a slave device.
Page 714 SPI Functional Description the number. The clock rate can be as high as the SCLK1_0 rate, and both even and odd dividers from SCLK1_0 are supported. For master devices, the SPI uses the SPI_CLK register value to determine the clock rate, whereas this value is ignored for slave devices.
Page 715 SPI Functional Description The SPI Timing with SPI_DLY.STOP Programming (Independent of SPI_CTL.CPHA Setting) figure illustrates SPI timing with STOP programming. The SPI module uses this timing to insert multiples of SPI_CLK period delays between transfers. The SPI_SS line is deasserted for the duration specified in the SPI_DLY.STOP bit field, assuming the SPI_CTL.SELST bit is configured for deassertion between transfers.
Page 716 SPI Functional Description pin is deasserted. The SPI uses the SPI_CTL.FCWM bits to control the FIFO status at which SPI_RDY deasser- tion takes place. Flow control in slave mode is purely based on the FIFO status and does not depend on the word counters.
Page 717 SPI Functional Description For example, assume that the SPI of the processor is the master. The SPI_SLVSEL.SSEL1 – SPI_SLVSEL.SSEL7 bits on the processor can be connected to the slave select pin of each slave device. In this configuration, the slave select bits can be used in three ways. In cases 1 and 2, the processor is the master and the seven microcontrollers or peripherals with SPI interfaces are slaves.
Page 718 SPI Functional Description The SPI_STAT.RFE bit defines when the receive buffer can be read, indicating that SPI_RFIFO is not empty. The SPI_STAT.TFF bit defines when the transmit buffer can be written, indicating that the is not SPI_TFIFO full. The end of a single word transfer occurs when the SPI_STAT.RFE bit is cleared. The status indicates that a new word has been received and written into the receive FIFO.
Page 719 SPI Functional Description SPI_CTL.SOSI bit is cleared, the order is reversed. Since dual I/O mode uses both pins to transmit or receive data, only one channel can be enabled, either transmit or receive. Flow control through the SPI_RDY pin is sup- ported.
Page 720 SPI Functional Description Changing to quad SPI mode must be done when the SPI is in a quiescent state. While using dual or quad I/O mode for communicating with flash devices, program the SPI_CTL.CPHA and the SPI_CTL.CPOL bits =1. This programming avoids bus contention during read operations, because the flash de- vice starts driving out the bits immediately after dummy cycles in read header.
Page 721 SPI Functional Description CPOL=0 CPOL=1 MOSI MISO Note : Last Master sample edge is internally generated to latch incoming data Figure 16-12: SPI Transfer Protocol in Fast Mode for SPI_CTL.CPHA = 1 Memory-Mapped Mode (SPI2 only) The SPI supports direct memory-mapped read accesses from a SPI memory device, enabled by setting the SPI_CTL.MMSE bit.
Page 722 Memory-Mapped Mode (SPI2 only) Table 16-6: Types of Operations (Continued) SPI Operation Non-Memory-Mapped Mode Memory-Mapped Mode MDMA write Memory-Mapped Description of Operation Memory-mapped mode is enabled by setting the SPI_CTL.MMSE bit. When enabled, the SPI (if ready) accepts the read requests through a dedicated on-chip slave interface. The memory subsystem master drives this dedicated interface through the SCB fabric.
Page 723 Memory-Mapped Mode (SPI2 only) SPI MEMORY MAPPED READ TRANSFER INITIATED MMRDH. MMRDH. CTL. CMDSKIP CMDPINS MIOM COMMAND PHASE SEND MMRDH.OPCODE SEND MMRDH.OPCODE SEND MMRDH.OPCODE ON MOSI, MISO D2, ON MOSI PIN ON MOSI AND MISO PINS AND D3 PINS MMRDH. CTL.
Page 724 Memory-Mapped Mode (SPI2 only) SPI CONTROLLER MEMORY-MAPPED RECEIVED DATA CS GAP MODE SETTINGS (CACHE LINE) LEAD STOP COMMAND ADDRESS DUMMY INTERNAL FLASH MEMORY APPLICATION ADDRESS Figure 16-14: Memory-Mapped Protocol As shown in the figure, the COMMAND field (SPI_MMRDH.OPCODE) is transmitted upon assertion of the SPI_SEL[n] signal.
Page 725 Memory-Mapped Mode (SPI2 only) of which is a function of the number of pins used to transmit the address (SPI_MMRDH.ADRPINS), as shown in the Pins Used to Transmit the Address (ADRPINS) table. Table 16-7: Pins Used to Transmit the Address (ADRPINS) Dummy clock cycles SPI_MMRDH.
Page 726 Memory-Mapped Mode (SPI2 only) Table 16-8: SPI Read Operations (Continued) Operation Read Command CMDPIN ADRPIN DMYSIZE Three-state Multiple Data Pins (Opcode) I/O Mode Quad I/O Read 0xEB 1, 4 Non-Zero Yes (IO0-3) 4 Some memory devices also support word quad I/O read (0xE7) and octal quad I/O read (0xE3) operations. These operations require fewer dummy cycles than normal quad I/O read operations.
Page 727 Memory-Mapped Mode (SPI2 only) SSEL CONTINUOUS CLOCKING N x 4 CLOCKS MOSI HI-Z READ CMD ADDRESS MODE READ DATA (Q0) 1 BYTE M BYTES BITS N BYTES (*) HI-Z ADDRESS MODE READ DATA M BYTES BITS N BYTES (*) MISO (Q1) M = 1, 2, 3, 4 ADDRESS BYTES N = 4, 8, 16, 32 READ DATA BYTES...
Page 728 Memory-Mapped Mode (SPI2 only) SSEL CONTINUOUS CLOCKING N x 2 CLOCKS HI-Z MOSI READ CMD ADDRESS MODE READ DATA 1 BYTE M BYTES BITS N BYTES (*) (Q0) HI-Z MISO ADDRESS MODE READ DATA M BYTES BITS N BYTES (*) (Q1) HI-Z ADDRESS...
Page 729 Memory-Mapped Mode (SPI2 only) To minimize this delay, the wrap feature can be used where the memory subsystem provides the address of the criti- cal word. • For MDMA reads, the number of read data bytes (N) is always equal to 4 bytes. The MDMA read does not depend on the cache setting.
Page 730 Memory-Mapped High-Performance Features Data access is limited to 8-byte, 16-byte, or 32-byte sections of flash page in wrap mode. The ARM core uses the Wrap 4 access (64-bit data) for L1 cache. The ARM core uses Wrap 4 and Wrap 8 accesses (64-bit data) for L2 cache.
Page 731 Memory-Mapped Mode (SPI2 only) memory-mapped access may be needed before setting the SPI_MMRDH.CMDSKIP bit in order to set the SPI memory device in Command Skip mode. For more details about how to configure SPI memories into XIP mode, refer to the device data sheet. NOTE: When configuring the flash to XIP mode from the SHARC+ core, ensure that the routine that configures flash to XIP is not routed through the L2CC.
Page 732 Memory-Mapped Mode (SPI2 only) Table 16-11: SPI Control (SPI_CTL) Register Bits Typical values to set Description Comments SPI_CTL.MSTR Master mode enable SPI_CTL.PSSE Protected slave select ena- SPI_CTL.ODM Open-drain mode enable SPI_CTL.CPHASPI_ 0–0 or 1–1 SPI mode of communica- Flash dependent, usually SPI flash supports CTL.CPOL tion mode-0 (CPHA=CPOL=0) and mode-3...
Page 733 Memory-Mapped Mode (SPI2 only) Table 16-13: SPI Transmit Control Register Bits Typical values to set Description SPI_TXCTL.TEN Transmit channel enable SPI_TXCTL.TTI Transmit transfer initiation disable SPI_TXCTL.TWCEN Transmit word counter disable SPI_TXCTL.TDR Transmit data request disable SPI_TXCTL.TDU Send last word when TFIFO is empty SPI_TXCTL.TRWM Transmit FIFO regular watermark SPI_TXCTL.TUWM...
Page 734 SPI Interrupt Signals • To use some of the features offered by SPI memory devices, programs can first configure the SPI memory de- vice by setting its control word or sending some commands. Since SPI memory-mapped hardware does not allow any type of SPI write operations, configure the SPI in non-memory-mapped mode prior to enabling memory-mapped mode.
Page 735 SPI Interrupt Signals Status Interrupts The SPI controller supports several status interrupt requests to indicate different conditions of the receiver and transmitter. All status interrupt requests can be masked. Status interrupt requests are signaled directly through a sin- gle SPI status IRQ line. The line cannot be combined with the SPI error IRQ line for some processors. The SPI Status Interrupts table describes the status interrupt requests that are available for the SPI controller.
Page 736 SPI Programming Concepts Table 16-16: SPI Error Interrupts (Continued) Description SPI_STAT.ROR Reception error. Signaled when an overflow condition occurs on the receive channel. This event occurs when a new data word is received, but the SPI_RFIFO is full. This error condition does not occur in master receive initiating mode since Not Full is one of the conditions for transfer initiation.
Page 737 SPI Programming Concepts 1. Write to the SPI_SLVSEL register, setting one or more of the SPI select enable bits. This operation ensures that the desired slaves are properly deselected while the master is configured. 2. The SPI_RXCTL.RTI and SPI_TXCTL.TTI bits determine the SPI initiating mode. The initiating mode defines the primary transfer channel, and also the initiating condition for the transfer.
Page 738 SPI Programming Concepts Configuring DMA Master Mode The SPI interface supports a write DMA channel and a read DMA channel. It can use these functions individually or in a lock-step manner in duplex mode (SPI_TXCTL.TTI= SPI_RXCTL.RTI=1). 1. Write to the appropriate DMA registers to enable the SPI DMA channel and to configure the necessary work units, access direction, word count, and so on.
Page 739 SPI Programming Concepts 9. If the receive pipe fills up due to unavailability of DMA grants, the transmit pipe stalls until the pipe is drained. If the transmit pipe fills up, the SPI stops requesting for DMA writes. If the value in SPI_RWC expires, further write-requests to DMA stop.
Page 740 ADSP-SC58x SPI Register Descriptions b. Upon a DMA grant, the DMA engine reads a word from memory and writes to the transmit FIFO. c. The SPI then reads DMA data from the transmit FIFO and writes to the transmit shift register, awaiting the start of the next transfer.
Page 741 ADSP-SC58x SPI Register Descriptions Table 16-17: ADSP-SC58x SPI Register List (Continued) Name Description SPI_IMSK Interrupt Mask Register SPI_IMSK_CLR Interrupt Mask Clear Register SPI_IMSK_SET Interrupt Mask Set Register SPI_MMRDH Memory Mapped Read Header (Only on SPI2) SPI_MMTOP SPI Memory Top Address (Only on SPI2) SPI_RFIFO Receive FIFO Data Register SPI_RWC...
Page 742 ADSP-SC58x SPI Register Descriptions Clock Rate Register register selects the baud rate for SPI data transfers, relating this rate to the SPI serial clock (SPI SPI_CLK clock) and the system clock (SCLK1_0). BAUD (R/W) Baud Rate Figure 16-20: SPI_CLK Register Diagram Table 16-18: SPI_CLK Register Fields Bit No.
Page 743 ADSP-SC58x SPI Register Descriptions Control Register register enables the SPI and configures settings for operating modes, communication protocols, and SPI_CTL buffer operations. FCPL (R/W) EN (R/W) Flow Control Polarity Enable FCCH (R/W) MSTR (R/W) Flow Control Channel Selection Master/Slave FCEN (R/W) PSSE (R/W) Flow Control Enable Protected Slave Select Enable...
Page 744 ADSP-SC58x SPI Register Descriptions Table 16-19: SPI_CTL Register Fields Bit No. Bit Name Description/Enumeration (Access) MMSE Memory-Mapped SPI Enable (Only on SPI2). (R/W) When the SPI_CTL.MMSE bit is asserted, communication to an SPI memory device is automated such that the memory it contains is accessible directly through the read of processor address space assigned to it.
Page 745 ADSP-SC58x SPI Register Descriptions Table 16-19: SPI_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 21:20 MIOM Multiple I/O Mode (Only on SPI2). (R/W) The SPI_CTL.MIOM bits enable SPI operation in dual I/O mode (DIOM) or quad I/O mode (QIOM). These bits can only be changed when the SPI is disabled (SPI_CTL.EN =0).
Page 746 ADSP-SC58x SPI Register Descriptions Table 16-19: SPI_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) FCCH Flow Control Channel Selection. (R/W) The SPI_CTL.FCCH bit selects whether the SPI applies flow control to the transmit channel (SPI_TFIFO buffer) or receive channel (SPI_RFIFO buffer).
Page 747 ADSP-SC58x SPI Register Descriptions Table 16-19: SPI_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) SELST Slave Select Polarity Between Transfers. (R/W) The SPI_CTL.SELST bit selects the state (polarity) for the SPI_SEL[n] pin be- tween SPI transfers when the SPI is a master and hardware slave select assertion is ena- bled (SPI_CTL.ASSEL =1).
Page 748 ADSP-SC58x SPI Register Descriptions Table 16-19: SPI_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Open Drain Mode. (R/W) The SPI_CTL.ODM bit configures the data output pins (SPI_MOSI and SPI_MISO) to behave as open drain outputs, which prevents contention and possible damage to pin drivers in multi-master or multi-slave SPI systems.
Page 749 ADSP-SC58x SPI Register Descriptions Delay Register register selects a transfer delay and the lead/lag timing between slave select signals and SPI clock SPI_DLY edge assertion/deassertion. LAGX (R/W) STOP (R/W) Extended SPI Clock Lag Control Transfer Delay Time in Multiples of SPI Clock Period LEADX (R/W) Extended SPI Clock Lead Control...
Page 750 ADSP-SC58x SPI Register Descriptions Masked Interrupt Condition Register register latches interrupts, queuing the interrupt requests for service. When a condition is indicat- SPI_ILAT ed by a bit in the SPI_STAT register and the corresponding interrupt request is unmasked in SPI_IMSK, the SPI latches the interrupt request bit in SPI_ILAT.
Page 751 ADSP-SC58x SPI Register Descriptions Table 16-21: SPI_ILAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Mode Fault Interrupt Latch. (R/NW) 0 No interrupt request 1 Latched interrupt request Transmit Collision Interrupt Latch. (R/NW) 0 No interrupt request 1 Latched interrupt request Transmit Underrun Interrupt Latch.
Page 752 ADSP-SC58x SPI Register Descriptions Masked Interrupt Clear Register register permits clearing individual mask bits in the register without affecting SPI_ILAT_CLR SPI_ILAT other bits in the register. Use write-1-to-clear on a bit in the SPI_ILAT_CLR register to clear the corresponding bit in the SPI_ILAT register.
Page 753 ADSP-SC58x SPI Register Descriptions Table 16-22: SPI_ILAT_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Clear Receive Start. (R/W1C) The SPI_ILAT_CLR.RS bit clears the corresponding mask bit in the SPI_ILAT register. 0 No effect 1 Clear mask bit Clear Mode Fault. (R/W1C) The SPI_ILAT_CLR.MF bit clears the corresponding mask bit in the SPI_ILAT...
Page 754 ADSP-SC58x SPI Register Descriptions Table 16-22: SPI_ILAT_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) RUWM Clear Receive Urgent Watermark. (R/NW) The SPI_ILAT_CLR.RUWM bit clears the corresponding mask bit in the SPI_ILAT register. 0 No effect 1 Clear mask bit 16–48 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference...
Page 755 ADSP-SC58x SPI Register Descriptions Interrupt Mask Register register unmasks (enables) or masks (disables) SPI interrupt requests. When a condition is indicat- SPI_IMSK ed by a bit in the SPI_STAT register and the corresponding interrupt request is unmasked in SPI_IMSK, the SPI latches the interrupt request bit in the SPI_ILAT register, queuing the interrupt request for service.
Page 756 ADSP-SC58x SPI Register Descriptions Table 16-23: SPI_IMSK Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Receive Start. (R/NW) The SPI_IMSK.RS bit unmasks (enables) or masks (disables) the RS interrupt. 0 Disable (mask) interrupt request 1 Enable (unmask) interrupt request Mode Fault.
Page 757 ADSP-SC58x SPI Register Descriptions Interrupt Mask Clear Register register permits clearing individual mask bits in the register without affecting SPI_IMSK_CLR SPI_IMSK other bits in the register. Use write-1-to-clear on a bit in the SPI_IMSK_CLR register to clear the corresponding bit in the SPI_IMSK register.
Page 758 ADSP-SC58x SPI Register Descriptions Table 16-24: SPI_IMSK_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Clear Receive Start. (R/W1C) The SPI_IMSK_CLR.RS bit clears the corresponding mask bit in the SPI_IMSK register. 0 No effect 1 Clear mask bit Clear Mode Fault. (R/W1C) The SPI_IMSK_CLR.MF bit clears the corresponding mask bit in the SPI_IMSK...
Page 759 ADSP-SC58x SPI Register Descriptions Table 16-24: SPI_IMSK_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) RUWM Clear Receive Urgent Watermark. (R/W1C) The SPI_IMSK_CLR.RUWM bit clears the corresponding mask bit in the SPI_IMSK register. 0 No effect 1 Clear mask bit ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference 16–53...
Page 760 ADSP-SC58x SPI Register Descriptions Interrupt Mask Set Register register permits setting individual mask bits in the register without affecting SPI_IMSK_SET SPI_IMSK other bits in the register. Use write-1-to-set on a bit in the SPI_IMSK_SET register to set the corresponding bit in SPI_IMSK register.
Page 761 ADSP-SC58x SPI Register Descriptions Table 16-25: SPI_IMSK_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Set Receive Start. (R/W1S) The SPI_IMSK_SET.RS bit sets the corresponding mask bit in the SPI_IMSK register. 0 No effect 1 Set mask bit Set Mode Fault. (R/W1S) The SPI_IMSK_SET.MF bit sets the corresponding mask bit in the SPI_IMSK...
Page 762 ADSP-SC58x SPI Register Descriptions Table 16-25: SPI_IMSK_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) RUWM Set Receive Urgent Watermark. (R/W1S) The SPI_IMSK_SET.RUWM bit sets the corresponding mask bit in the SPI_IMSK register. 0 No effect 1 Set mask bit 16–56 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference...
Page 763 ADSP-SC58x SPI Register Descriptions Memory Mapped Read Header (Only on SPI2) register enables the use of memory-mapped mode. This mode allows direct memory-mapped SPI_MMRDH read accesses of an SPI memory device and is primarily used to directly execute instructions from an SPI FLASH memory without using a low-level software driver.
Page 764 ADSP-SC58x SPI Register Descriptions Table 16-26: SPI_MMRDH Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) CMDSKIP Command Skip Enable. (R/W) The SPI_MMRDH.CMDSKIP bit enables command skip mode where the address is sent first and the OPCODE field is not sent (SPI_MMRDH.CMDSKIP bit =1). This mode is useful for supporting XIP (Execute-In-Place) operation where only the address is sent and the same read command is assumed.
Page 765 ADSP-SC58x SPI Register Descriptions Table 16-26: SPI_MMRDH Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 25:24 TRIDMY Tristate Dummy Timing. (R/W) The SPI_MMRDH.TRIDMY bits specify whether and when output pins are three- stated during the interval of time specified by the SPI_MMRDH.DMYSIZE bits. Out- put pins potentially three-stated include all pins which were used to transmit the ad- dress 0 Tristate outputs immediately...
Page 766 ADSP-SC58x SPI Register Descriptions Table 16-26: SPI_MMRDH Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ADRPINS Pins Used for Address. (R/W) The SPI_MMRDH.ADRPINS bit specifies the number of pins to be used for address transmission. This bit must be set consistent with expectations established by read op- code.
Page 767 ADSP-SC58x SPI Register Descriptions SPI Memory Top Address (Only on SPI2) register specifies the top populated address of a connected SPI memory device. SPI_MMTOP TOPADR[15:0] (R/W) SPI Memory Top Address TOPADR[31:16] (R/W) SPI Memory Top Address Figure 16-29: SPI_MMTOP Register Diagram Table 16-27: SPI_MMTOP Register Fields Bit No.
Page 768 ADSP-SC58x SPI Register Descriptions Receive FIFO Data Register register has an interface to the receive shift register in the SPI and has an interface to the process- SPI_RFIFO or’s data buses. The top level of the buffer is visible to programs as the 32-bit SPI_RFIFO register, but the size (number of word locations) of the receive FIFO is actually flexible with transfer word size.
Page 769 ADSP-SC58x SPI Register Descriptions Received Word Count Register register holds a count of the number of words remaining to be received by the SPI. To start the SPI_RWC decrement of the word count in SPI_RWC, enable the receive word counter (SPI_RXCTL.RWCEN =1). The SPI uses the word count to control the duration of transfers and to signal the completion of a burst of transfers with the receive finish interrupt (SPI_ILAT.RF).
Page 770 ADSP-SC58x SPI Register Descriptions Received Word Count Reload Register register holds the receive word count value that the SPI loads into the register when the SPI_RWCR SPI_RWC transfer count decrements to zero. To prevent the SPI from reloading the counter, use zero for the reload count val- ue.
Page 771 ADSP-SC58x SPI Register Descriptions Receive Control Register register enables the SPI receive channel, initiates receive transfers, and configures SPI_RXCTL SPI_RFIFO buffer watermark settings. RRWM (R/W) REN (R/W) Receive FIFO Regular Watermark Receive Enable RDO (R/W) RTI (R/W) Receive Data Overrun Receive Transfer Initiate RDR (R/W) RWCEN (R/W)
Page 772 ADSP-SC58x SPI Register Descriptions Table 16-31: SPI_RXCTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 13:12 RRWM Receive FIFO Regular Watermark. (R/W) The SPI_RXCTL.RRWM bits select the receive FIFO (SPI_RFIFO) watermark level for regular data bus requests. When an urgent SPI_RFIFO watermark is enabled with SPI_RXCTL.RUWM, the SPI_RXCTL.RRWM selection is used as the deasser-...
Page 773 ADSP-SC58x SPI Register Descriptions Table 16-31: SPI_RXCTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Receive Transfer Initiate. (R/W) The SPI_RXCTL.RTI bit enables initiation of receive transfers if the receive FIFO (SPI_RFIFO) is not full. The bit also enables this initiation if SPI_RWC is not zero when SPI_RXCTL.RWCEN is enabled.
Page 774 ADSP-SC58x SPI Register Descriptions Slave Select Register register enables the SPI_SEL[n] pins for output and indicates the state (high or low) of SPI_SLVSEL these pins when enabled. SSEL7 (R/W) SSE1 (R/W) Slave Select 7 Output Slave Select 1 Enable SSEL6 (R/W) SSE2 (R/W) Slave Select 6 Output Slave Select 2 Enable...
Page 775 ADSP-SC58x SPI Register Descriptions Table 16-32: SPI_SLVSEL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) SSEL5 Slave Select 5 Output. (R/W) The SPI_SLVSEL.SSEL5 bit state indicates the value driven on the related SPI_SEL[n] pin. 0 Low 1 High SSEL4 Slave Select 4 Output.
Page 776 ADSP-SC58x SPI Register Descriptions Table 16-32: SPI_SLVSEL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) SSE6 Slave Select 6 Enable. (R/W) The SPI_SLVSEL.SSE6 bit enables the related SPI_SEL[n] pin for output. See the SPI_SLVSEL.SSE7 bit description for more information. 0 Disable 1 Enable SSE5...
Page 777 ADSP-SC58x SPI Register Descriptions Status Register register indicates SPI status including FIFO status, error conditions, and interrupt conditions. SPI_STAT When an interrupt condition from this register is unmasked (enabled) by the corresponding bit in the SPI_IMSK register, the interrupt request is latched into the corresponding bit in the SPI_ILAT register.
Page 778 ADSP-SC58x SPI Register Descriptions Table 16-33: SPI_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) MMRE Memory Mapped Read Error. (R/W1C) The SPI_STAT.MMRE bit =1 if an attempt is made to read address space reserved for memory-mapped SPI memory while memory mapping is disabled (see the SPI_CTL.MMSE bit).
Page 779 ADSP-SC58x SPI Register Descriptions Table 16-33: SPI_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 14:12 SPI_RFIFO Status. (R/NW) The SPI_STAT.RFS bits indicate the status of the SPI_RFIFO. The SPI uses this status when evaluating receive watermark conditions. 0 Empty RFIFO 1 25% full RFIFO 2 50% full RFIFO 3 75% full RFIFO...
Page 780 ADSP-SC58x SPI Register Descriptions Table 16-33: SPI_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Mode Fault Indication. (R/W1C) The SPI_STAT.MF bit, when SPI is a master and SPI_CTL.PSSE is enabled, in- dicates that multiple masters have asserted slave select inputs. 0 No status 1 Mode fault occurred Transmit Collision Indication.
Page 781 ADSP-SC58x SPI Register Descriptions Table 16-33: SPI_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) SPIF SPI Finished. (R/NW) The SPI_STAT.SPIF bit indicates that a single word transfer is complete. 0 No status 1 Completed single word transfer ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference 16–75...
Page 782 ADSP-SC58x SPI Register Descriptions Transmit FIFO Data Register register has an interface to the transmit shift register in the SPI and has an interface to the pro- SPI_TFIFO cessor’s data buses. The top level of the buffer is visible to programs as the 32-bit SPI_TFIFO register, but the size (number of word locations) of the transmit FIFO is actually flexible with transfer word size.
Page 783 ADSP-SC58x SPI Register Descriptions Transmitted Word Count Register register holds a count of the number of words remaining to be transmitted by the SPI. To start the SPI_TWC decrement of the word count in SPI_TWC, enable the transmit word counter (SPI_TXCTL.TWCEN =1). The SPI uses the word count to control the duration of transfers and to signal the completion of a burst of transfers with the transmit finish interrupt request.
Page 784 ADSP-SC58x SPI Register Descriptions Transmitted Word Count Reload Register register holds the transmit word count value that the SPI loads into the register when SPI_TWCR SPI_TWC the transfer count decrements to zero. To prevent the SPI from reloading the counter, use zero for the reload count value.
Page 785 ADSP-SC58x SPI Register Descriptions Transmit Control Register register enables the SPI transmit channel, initiates transmit transfers, and configures SPI_TXCTL SPI_TFIFO buffer watermark settings. TRWM (R/W) TEN (R/W) FIFO Regular Watermark Transmit Enable TDU (R/W) TTI (R/W) Transmit Data Underrun Transmit Transfer Initiate TDR (R/W) TWCEN (R/W) Transmit Data Request...
Page 786 ADSP-SC58x SPI Register Descriptions Table 16-37: SPI_TXCTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 13:12 TRWM FIFO Regular Watermark. (R/W) The SPI_TXCTL.TRWM bits select the transmit FIFO (SPI_TFIFO) watermark level for regular data bus requests. When an urgent SPI_TFIFO watermark is ena- bled with SPI_TXCTL.TUWM, the SPI_TXCTL.TRWM selection is used as the...
Page 787 ADSP-SC58x SPI Register Descriptions Table 16-37: SPI_TXCTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Transmit Transfer Initiate. (R/W) The SPI_TXCTL.TTI bit enables initiation of transmit transfers if the transmit FIFO (SPI_TFIFO) is not empty. The bit also enables this initiation if SPI_TWC not zero when SPI_TXCTL.TWCEN is enabled.
Page 788 Universal Asynchronous Receiver/Transmitter (UART) 17 Universal Asynchronous Receiver/Trans- mitter (UART) The UART module is a full-duplex peripheral compatible with PC-style industry-standard UARTs. The UART con- verts data between serial and parallel formats. The serial communication follows an asynchronous protocol that sup- ports various word lengths, stop bits, bit rates, and parity-generation options.
Page 789 UART Functional Description • Independent DMA operation for receive and transmit • Programmable automatic request to send (RTS)/clear to send (CTS) hardware flow control • False start bit detection • SIR IrDA operation mode • MDB/ICP v2.0 operation mode • Internal loopback •...
Page 790 UART Functional Description options. A set of registers governs UART operations. For more information on UART functionality, see the UART register descriptions. Table 17-2: ADSP-SC58x UART Register List Name Description UART_CLK Clock Rate Register UART_CTL Control Register UART_IMSK Interrupt Mask Register UART_IMSK_CLR Interrupt Mask Clear Register UART_IMSK_SET...
Page 791 UART Functional Description Table 17-3: ADSP-SC58x UART Interrupt List (Continued) Interrupt Name Description Sensitivity Channel UART0_RXDMA_ERR UART0 Receive DMA Error Level UART1_TXDMA_ERR UART1 Transmit DMA Error Level UART1_RXDMA_ERR UART1 Receive DMA Error Level UART2_TXDMA_ERR UART2 Transmit DMA Error Level UART2_RXDMA_ERR UART2 Receive DMA Error Level ADSP-SC58x UART Trigger List...
Page 792 UART Functional Description Table 17-6: ADSP-SC58x UART DMA Channel List (Continued) DMA ID DMA Channel Name Description DMA34 UART1_TXDMA UART1 Transmit DMA DMA35 UART1_RXDMA UART1 Receive DMA DMA37 UART2_TXDMA UART2 Transmit DMA DMA38 UART2_RXDMA UART2 Receive DMA UART Block Diagram The UART Block Diagram figure shows a simplified block diagram of one UART module and how it interconnects to the processor system.
Page 793 UART Architectural Concepts • The transmit and receive request outputs can function as DMA requests and connect to the DMA controller. Therefore, if the DMA is not enabled, the DMA controller simply forwards the request to the system event controller (SEC). •...
Page 794 UART Architectural Concepts The bit clock is 1/16th of the sample clock. If not in IrDA mode, the bit clock can equal the sample clock if the UART_CLK.EDBO bit is set, so that the following equation applies: (1-EDBO) Bit Rate = SCLK0_0/16 ×...
Page 795 UART Architectural Concepts bit rate applied to the UART_RX pin automatically by an external device. It often uses the capture capabilities of the timer to supervise the bit rate at run time. If the UART communicates with any device supplied by a weak clock oscillator that drifts over time, the processor can then readjust its UART bit rate dynamically, as required.
Page 796 UART Architectural Concepts • Divisor = TIMER_TMR[n]_PER>> 3, if UART_CLK.EDBO=1 The Autobaud Detection Character 0x40 figure shows the ASCII “@” (0x40) detection character. STOP PERIOD Figure 17-4: Autobaud Detection Character 0x40 UART Debug Features The UART can automatically calculate and transmit a parity bit. The UART Parity table summarizes parity behav- ior assuming 8-bit data words (UART_CTL.WLS=b#11).
Page 797 UART Operating Modes • Multi-Drop Bus Mode UART Mode The UART mode follows an asynchronous serial communication protocol with these options: • 1 start bit • 5–8 data bits • Address bit (available in MDB mode only) • None, even, odd or sticky parity •...
Page 798 UART Operating Modes In a multidrop bus (MDB) network, for example, an address bit enhances the UART frame. The address bit is inser- ted between the data bits and the optional parity bit. To configure the UART for MDB mode, set the mode of operation bits (UART_CTL.MOD [5:4]) to 01.
Page 799 UART Operating Modes NOTE: If the address bit and parity bit are both enabled, the parity check and generation includes the address bit in its parity calculation. UART Data Transfer Modes The UART can transfer data using both the core and DMA. Receive and transmit paths operate independently ex- cept that the bit rate and the frame format are identical for both transfer directions.
Page 800 UART Data Transfer Modes NOTE: If another transmission is pending (in the UART_TSR register), the UART_TAIP initiated pulse is queued until after all pending operations have finished and all stop bits are transmitted. The transmission of break command/inter-frame gap precedes transmission of the number of stop bits as set in the UART_CTL.STB and UART_CTL.STBH bit fields.
Page 801 UART Data Transfer Modes Reception starts when the UART receiver detects a falling edge on the UART_RX input pin. The receiver attempts to see a start bit. The data is shifted into the register. After the ninth sample of the first, the receiver UART_RSR processes the stop bit and copies the received data to the 8-stage receive FIFO.
Page 802 UART Data Transfer Modes Glitch filtering is accomplished by counting 16 system clocks from the time the receiver detects an initial pulse. If the pulse is absent when the counter expires, the receiver interprets it as a glitch. Otherwise, the receiver interprets it as a zero.
Page 803 UART Data Transfer Modes If DMA is enabled, the DMA engine always writes the data into the UART_THR register, and the written word is transmitted with the appending address bit set low. The polarity of transmit data is selectable, using the UART_CTL.TPOLC bit. MDB Receive Operation Receive operations use the same data format as the transmit configuration, except that the number of stop bits is always assumed to be 1.
Page 804 UART Data Transfer Modes Regardless of the DMA_CFG.SYNC setting, the DMA stream has not left the UART transmitter completely at the time the interrupt request is generated. Transmission can abort in the middle of the stream, causing data loss, when the UART clock was disabled without extra synchronization with the UART_STAT.TEMT bit.
Page 805 UART Event Control UART Event Control Status flags in the register are available to signal data reception, parity, and error conditions, if neces- UART_STAT sary. DMA and Interrupt Multiplexing See the Direct Memory Access (DMA) chapter on for information on DMA multiplexing. Several interrupts and DMA channels in thr UART can be multiplexed.
Page 806 UART Event Control interrupt as an alternative to the regular UART_IMSK.ERBFI receive interrupt. Hardware must ensure that at least two (if UART_CTL.RFIT=0) or four (if UART_CTL.RFIT=1) words are available in the receive buffer by the time the interrupt is requested. Transmit Interrupts The UART module uses the UART_IMSK_SET.ETBEI bit to enable transmit interrupt requests.
Page 807 UART Event Control When enabled by the UART_IMSK.ETBEI bit, the UART_STAT.THRE flag requests data along the peripheral command lines to the DMA controller (referred to as TXREQ). This signal is routed through the DMA controller. If the associated DMA channel is enabled, the TXREQ signal functions as a DMA request, otherwise the DMA controller simply forwards it to the SEC.
Page 808 UART Event Control • UART_STAT.FE bits • UART_STAT.BI bits • register UART_RBR The UART_STAT.OE bit is updated as soon as an overflow condition occurs (for example when a stop bit for a frame is received and the receive FIFO is full). When software does not read the UART_RBR register in time, the received data is protected from being overwritten by new data until software clears the UART_STAT.OE bit.
Page 809 UART Event Control indicates a receive buffer threshold level. If the UART_CTL.RFIT bit is cleared, software can safely read two words out of the register by the time the UART_STAT.RFCS interrupt occurs. UART_RBR If the UART_CTL.RFIT bit is set, software can safely read four words. The interrupt request and the UART_STAT.RFCS bit are cleared when the UART_RBR is read enough of times, so that the receive buffer drains...
Page 810 UART Programming Model 2. Configure the following bits: UART_CTL.MOD =00, UART_CTL.LOOP_EN =1, UART_CTL.WLS =11 (8- bit data), and UART_CTL.EN =1 3. Configure the following bits: TIMER_TMR[n]_CFG.TMODE =1101, TIMER_TMR[n]_CFG.OUTDIS =1, TIMER_TMR[n]_CFG.IRQMODE =10 and enable the timer. 4. Send test data through the host device and wait for the timer interrupt and disable the timer. The bit rate can be derived from the timer period register value according to the formula provided in the Auto- baud Detection...
Page 811 ADSP-SC58x UART Register Descriptions ADSP-SC58x UART Register Descriptions UART (UART) contains the following registers. Table 17-9: ADSP-SC58x UART Register List Name Description UART_CLK Clock Rate Register UART_CTL Control Register UART_IMSK Interrupt Mask Register UART_IMSK_CLR Interrupt Mask Clear Register UART_IMSK_SET Interrupt Mask Set Register UART_RBR Receive Buffer Register UART_RSR...
Page 812 ADSP-SC58x UART Register Descriptions Clock Rate Register register divides the system clock ( SCLK0_0) down to the bit clock. UART_CLK DIV (R/W) Divisor EDBO (R/W) Enable Divide By One Figure 17-11: UART_CLK Register Diagram Table 17-10: UART_CLK Register Fields Bit No. Bit Name Description/Enumeration (Access)
Page 813 ADSP-SC58x UART Register Descriptions Control Register register provides enable and disable control for internal UART and for the IrDA mode of opera- UART_CTL tion. This register also provides UART line control, permitting selection of the format of received and transmitted character frames.
Page 814 ADSP-SC58x UART Register Descriptions Table 17-11: UART_CTL Register Fields Bit No. Bit Name Description/Enumeration (Access) RFRT Receive FIFO RTS Threshold. (R/W) The UART_CTL.RFRT bit controls UART_RTS pin assertion and deassertion tim- ing. This bit is ignored if UART_CTL.ARTS is cleared. If set, the UART_RTS pin is deasserted when the receive buffer already holds seven words and an eighth start bit is detected.
Page 815 ADSP-SC58x UART Register Descriptions Table 17-11: UART_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) XOFF Transmitter off. (R/W) The UART_CTL.XOFF bit (if set) turns off transmission (XOFF) by preventing the content of THR from being continued to TSR. When set, this bit turns on transmis- sion (XON).
Page 816 ADSP-SC58x UART Register Descriptions Table 17-11: UART_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) FCPOL Flow Control Pin Polarity. (R/W) The UART_CTL.FCPOL bit selects the polarities of the UART_CTS and UART_RTS pins. When the UART_CTL.FCPOL bit is cleared, the UART_RTS and UART_CTS pins are active low, and the UART is halted when the UART_RTS and UART_CTS pin state is high.
Page 817 ADSP-SC58x UART Register Descriptions Table 17-11: UART_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Sticky Parity. (R/W) The UART_CTL.STP bit controls whether the parity is generated by hardware based on the data bits or whether it is set to a fixed value. If this bit is cleared, the hardware calculates the parity bit value based on the data bits.
Page 818 ADSP-SC58x UART Register Descriptions Table 17-11: UART_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Word Length Select. (R/W) The UART_CTL.WLS field determines whether the transmitted and received UART word consists of 5, 6, 7, or 8 data bits. 0 5-bit word 1 6-bit word 2 7-bit word...
Page 819 ADSP-SC58x UART Register Descriptions Interrupt Mask Register register indicates the interrupt mask status (unmasked, if set, or masked, if cleared) of the UART UART_IMSK status interrupt requests. This register is not a data register. Instead, it is controlled by the UART_IMSK_SET UART_IMSK_CLR register pair.
Page 820 ADSP-SC58x UART Register Descriptions ETXS (R/W) ERBFI (R/W) Enable TX to Status Interrupt Mask Enable Receive Buffer Full Interrupt Status Mask Status ERXS (R/W) ETBEI (R/W) Enable RX to Status Interrupt Mask Enable Transmit Buffer Empty Interrupt Status Mask Status EAWI (R/W) ELSI (R/W) Enable Address Word Interrupt Mask...
Page 821 ADSP-SC58x UART Register Descriptions Table 17-12: UART_IMSK Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) EAWI Enable Address Word Interrupt Mask Status. (R/W) If set (interrupt unmasked), the UART_IMSK.EAWI bit indicates generation of a sta- tus interrupt request when an Address word in MDB-mode is present in the UART_RBR.
Page 822 ADSP-SC58x UART Register Descriptions Table 17-12: UART_IMSK Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) EDSSI Enable Modem Status Interrupt Mask Status. (R/W) If set (interrupt unmasked), the UART_IMSK.EDSSI bit indicates enabling of a mo- dem status interrupt request on the same status interrupt channel when the UART_STAT.SCTS bit is set.
Page 823 ADSP-SC58x UART Register Descriptions Interrupt Mask Clear Register indicates interrupt mask status (unmasked if set, masked if cleared) of UART status interrupts. UART_IMSK This register is not a data register. Instead it is controlled by the UART_IMSK_SET UART_IMSK_CLR regis- ter pair. Writing ones to UART_IMSK_SET enables (unmasks) interrupt requests, and writing ones to disables (masks) them.
Page 824 ADSP-SC58x UART Register Descriptions Table 17-13: UART_IMSK_CLR Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ERFCI Enable Receive FIFO Count Interrupt Mask Clear. (R/W1C) 0 No action 1 Mask interrupt ETFI Enable Transmission Finished Interrupt Mask Clear. (R/W1C) 0 No action 1 Mask interrupt EDTPTI Enable DMA TX Peripheral Triggered Interrupt Mask Clear.
Page 825 ADSP-SC58x UART Register Descriptions Interrupt Mask Set Register indicates interrupt request mask status (unmasked if set, masked if cleared) of UART status inter- UART_IMSK rupts. This register is not a data register. Instead it is controlled by the UART_IMSK_SET UART_IMSK_CLR register pair.
Page 826 ADSP-SC58x UART Register Descriptions Table 17-14: UART_IMSK_SET Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ERFCI Enable Receive FIFO Count Interrupt Mask Set. (R/W1S) 0 No action 1 Unmask interrupt ETFI Enable Transmission Finished Interrupt Mask Set. (R/W1S) 0 No action 1 Unmask interrupt EDTPTI Enable DMA TX Peripheral Triggered Interrupt Mask Set.
Page 827 ADSP-SC58x UART Register Descriptions Receive Buffer Register The read-only register is the UART’s receive buffer. It is updated when there is pending data in the UART_RBR receive FIFO. Newly available data is signaled by the UART_STAT.DR bit. VALUE (R) 8-bit data Figure 17-16: UART_RBR Register Diagram Table 17-15: UART_RBR Register Fields Bit No.
Page 828 ADSP-SC58x UART Register Descriptions Receive Shift Register The read only register which returns the content of the UART’s receive shift register. UART_RSR The frame data is moved into this shift register after polarity inversion, if any (including the native polarity inversion in the IrDA case).
Page 829 ADSP-SC58x UART Register Descriptions Receive Counter Register register returns the content of 16-bit counter in the UART receiver. This count is used for baud UART_RXCNT rate clock generation (the lower [15:0] is the count data). VALUE (R) 16-bit Counter Value Figure 17-18: UART_RXCNT Register Diagram Table 17-17: UART_RXCNT Register Fields Bit No.
Page 830 ADSP-SC58x UART Register Descriptions Scratch Register registers contain 8-bit scratch pad data. These registers are used for general purpose data storage UART_SCR and do not control the UART hardware in any way. VALUE (R/W) Stored 8-bit Data Figure 17-19: UART_SCR Register Diagram Table 17-18: UART_SCR Register Fields Bit No.
Page 831 ADSP-SC58x UART Register Descriptions Status Register register contains the UART line status and UART modem status, as indicated by the current UART_STAT states of the UART’s UART_CTS pin and internal receive buffers. Writes to this register can perform write-one-to- clear (W1C) operations on most status bits. Reading this register has no side effects. SCTS (R/W1C) DR (R) Sticky CTS...
Page 832 ADSP-SC58x UART Register Descriptions Table 17-19: UART_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Clear to Send. (R/NW) The UART_STAT.CTS bit holds the value (if UART_CTL.FCPOL set) or the com- plement value (if UART_CTL.FCPOL cleared) of the UART_CTS input pin. The UART_CTL.ACTS bit must be set to enable this feature.
Page 833 ADSP-SC58x UART Register Descriptions Table 17-19: UART_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ASTKY Address Sticky. (R/W1C) The UART_STAT.ASTKY bit is used in multi-drop bus mode to indicate whether a peripheral is currently being addressed. This bit is a sticky version of the UART_STAT.ADDR bit and is set by hardware when setting the UART_STAT.ADDR bit.
Page 834 ADSP-SC58x UART Register Descriptions Table 17-19: UART_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) THRE Transmit Hold Register Empty. (R/NW) The UART_STAT.THRE bit indicates that the UART transmit channel is ready for new data and software can write to the UART_THR UART_TAIP registers.
Page 835 ADSP-SC58x UART Register Descriptions Table 17-19: UART_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) Overrun Error. (R/W1C) The UART_STAT.OE bit indicates that further data is received while the internal re- ceive buffer was full. This bit is set when sampling the stop bit of the sixth data word. To avoid overruns, read the UART_RBR register in time.
Page 836 ADSP-SC58x UART Register Descriptions Transmit Address/Insert Pulse Register register and the register share the same physical register, but has dif- UART_TAIP UART_THR UART_TAIP ferent effect than the UART_THR register when UART_TAIP is written to in MDB and UART modes. In MDB mode, data written to the UART_TAIP register is transmitted as an address frame (as with the UART_CTL.MOD bit set).
Page 837 ADSP-SC58x UART Register Descriptions Transmit Hold Register The write-only register is the UART’s transmit buffer. The UART_STAT.THRE bit indicates whether UART_THR data can be written to UART_THR. Writes to this register automatically propagate to the internal UART_TSR regis- ter as soon as UART_TSR is ready.
Page 838 ADSP-SC58x UART Register Descriptions Transmit Shift Register The read only register which returns the content of the UART’s transmit shift register. UART_TSR VALUE (R) Contents of TSR Figure 17-23: UART_TSR Register Diagram Table 17-22: UART_TSR Register Fields Bit No. Bit Name Description/Enumeration (Access) 10:0...
Page 839 ADSP-SC58x UART Register Descriptions Transmit Counter Register read only register returns the content of 16-bit counter in the UART transmitter. This count is UART_TXCNT used for baud rate clock generation (the lower [15:0] is the count data). VALUE (R) 16-bit Counter Value Figure 17-24: UART_TXCNT Register Diagram Table 17-23: UART_TXCNT Register Fields Bit No.
Page 840 Enhanced Parallel Peripheral Interface (EPPI) 18 Enhanced Parallel Peripheral Interface (EPPI) The Enhanced Parallel Peripheral Interface (EPPI) is a half-duplex, bidirectional port with a dedicated clock pin and three frame sync (FS) pins. It can support direct connections to active TFT LCDs, parallel A/D and D/A converters, video encoders and decoders, image sensor modules and other general-purpose peripherals.
Page 841 EPPI Functional Description • RGB888 to RGB666 or RGB565 conversion for transmit modes • 4:2:2 YCrCb data Tx/Rx interleaving or de-interleaving modes • Configurable LCD data enable (DEN) output available on frame sync 3 • Delayed start of PPI frame syncs •...
Page 842 EPPI Functional Description ADSP-SC58x EPPI Register List The EPPI is a half-duplex, bidirectional parallel port. It comprises a clock pin, 3 frame sync pins, and a set of data pins. For more information on EPPI functionality, see the EPPI register descriptions. Table 18-1: ADSP-SC58x EPPI Register List Name Description...
Page 843 EPPI Functional Description Table 18-2: ADSP-SC58x EPPI Interrupt List (Continued) Interrupt Name Description Sensitivity Channel EPPI0_CH1_DMA_ERR EPPI0 DMA Channel 1 Error ADSP-SC58x EPPI Trigger List Table 18-3: ADSP-SC58x EPPI Trigger List Masters Trigger ID Name Description Sensitivity EPPI0_CH0_DMA EPPI0 Channel 0 DMA Edge EPPI0_CH1_DMA EPPI0 Channel 1 DMA...
Page 844 EPPI Functional Description In the same manner, all data values for odd samples which are more than the value in the EPPI_ODDCLIP.HIGHODD bit field are replaced with the value in the EPPI_ODDCLIP.HIGHODD field. All data values for even samples which are more than the values in the EPPI_EVENCLIP.HIGHEVEN field are re- placed with the values in the EPPI_EVENCLIP.HIGHEVEN field.
Page 845 EPPI Functional Description TRANSMIT EPPIDATA [0] DATA FLIP EPPIDATA [0] EPPIDATA [15] FLOP EPPIDATA [1] FLIP EPPIDATA [1] FLOP EPPIDATA [14] EPPIDATA [2] EPPI EPPIDATA [14] EPPIDATA [15] FLIP EPPIDATA [15] FLOP EPPIDATA [0] DAT_MRR EPPI_CLK Figure 18-2: Data Mirroring Transmit Windowing The EPPI supports windowing for general-purpose input modes.
Page 846 EPPI Functional Description Table 18-5: Video Mode Comparison (Continued) Video Mode Frame Rate Frame Resolution Active Video Resolu- Sampling Frequency Remarks tion (MHz) SMPTE 274M 2200x1125 1920x1080 74.25 Y,C separate 2200x1125 1920x1080 148.50 Y,C separate 2640x1125 1920x1080 74.25 Y,C separate 2640x1125 1920x1080 148.50...
Page 847 EPPI Functional Description SMPTE 274M An HD standard defining the spatial resolution (image sample structure) and frame rates for 1920x1080. SMPTE 296M An HD standard for defining the spatial resolution (image sample structure) and frame rates fro 1280x720. EPPI Block Diagram The EPPI Block Diagram figure shows the functional blocks within the EPPI.
Page 848 EPPI Architectural Concepts SCB IINTERFACE Y FIFO U/V FIFO data packing/unpacking EPPI_DATA_OUT EPPI_DATA_IN Figure 18-4: EPPI DMA Interface EPPI_DATA_IN PREAMBLE ERROR CORRECTION ITU_DATA_OUT SIGN EXTEND/ZERO FILL SIGN_DATA_OUT RX DATA PACKING PACK_FMX_X2F CDATA YFIFO CFIFO EPPI clock domain SCLK0 domain SCB BUS Figure 18-5: Receive Data Path ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference 18–9...
Page 849 EPPI Architectural Concepts SCB BUS SCLK0 domain EPPI clock domain YFIFO CFIFO UNPACK UNPACK DATA DATA EPPI_UNPACKDP CLIP CLIP_DATA_OUT CLIP_EN BLANKGEN_DATA BLANKGEN_EN dataout_x2f EPPI_DATA_OUT Figure 18-6: Transmit Data Path Reset Operation On a hardware reset, the entire EPPI is reset. All MMRs return to their default values. EPPI interrupt and DMA requests become inactive and internally generated EPPI_CLK and frame syncs are aborted.
Page 850 EPPI Architectural Concepts Table 18-7: Clock Polarity Selections and Receive/Transmit Pin States Receive Transmit Bit Setting Sample Data Sample/Drive Syncs Drive Data Sample/Drive Syncs POLC = b#00 Falling edge Falling edge Rising edge Rising edge POLC = b#01 Falling edge Rising edge Rising edge Falling edge...
Page 851 EPPI Architectural Concepts • Setting DMA_XCNT =38,400 (320 x 120), DMA_YCNT =2, and DMA_CFG.INT =1 causes an interrupt when half of the frame is transferred, and again when the whole frame is transferred. The following is the general procedure for setting up DMA operation with the EPPI. 1.
Page 852 EPPI Operating Modes EPPI Operating Modes The EPPI supports various receive and transmit modes of operation which include the detection and generation of preamble data. Specifically, the EPPI supports data formats described in the specifications ITU656, SMPTE 274M and SMPTE 296M. In addition to these modes, the EPPI also supports general-purpose receive and transmit using up to three frame syncs (FS).
Page 853 ITU-R 656 Modes INTERLACED VIDEO LINE # LINE 4 VERTICAL LINE BLANKING FIELD 1 NUMBER (EAV) (SAV) FIELD 1 NTSC ACTIVE VIDEO 266-282 LINE 266 4-19 VERTICAL 264-265 FIELD 2 BLANKING 20-263 FIELD 2 283-525 ACTIVE VIDEO LINE 3 LINE 1 VERTICAL BLANKING FIELD 1...
Page 854 ITU-R 656 Modes • V = 1 during vertical blanking • V = 0 when not in vertical blanking • H = 0 at SAV • H = 1 at EAV • P3 = V XOR H • P2 = F XOR H •...
Page 855 ITU-R 656 Modes Table 18-10: Operating Modes and Generic EPPI Operation How to configure in ITU How to configure Useful for R 656 Tx Mode Entire field DIR= 0 XFRTYPE = b#01 Active video DIR = 0 ITU-R BT.656 Rx XFRTYPE = b#00 Blanking only DIR = 0...
Page 856 ITU-R 656 Input Modes BLANKING BLANKING BLANKING FIELD 1 FIELD 1 FIELD 1 ACTIVE VIDEO ACTIVE VIDEO ACTIVE VIDEO BLANKING BLANKING BLANKING FIELD 2 FIELD 2 FIELD 2 ACTIVE VIDEO ACTIVE VIDEO ACTIVE VIDEO BLANKING BLANKING BLANKING ENTIRE FIELD SENT ACTIVE VIDEO ONLY SENT BLANKING ONLY SENT Figure 18-10: ITU-R 656 Input Submodes...
Page 857 ITU-R 656 Modes In VBI mode, the program must specify the number of total (active plus vertical blanking) lines per frame in the EPPI_FRAME register. The program must specify the number of total (active plus horizontal blanking plus 8) sam- ples per line in the register.
Page 858 EPPI Operating Modes HORIZONTAL BLANKING VERTICAL BLANKING HORIZONTAL BLANKING VERTICAL BLANKING F1VB_BD HORIZONTAL BLANKING VERTICAL BLANKING HORIZONTAL BLANKING ACTIVE DATA HORIZONTAL BLANKING ACTIVE DATA F1_ACT HORIZONTAL BLANKING ACTIVE DATA HORIZONTAL BLANKING ACTIVE DATA HORIZONTAL BLANKING ACTIVE DATA HORIZONTAL BLANKING VERTICAL BLANKING F1VB_AD HORIZONTAL BLANKING VERTICAL BLANKING...
Page 859 EPPI Operating Modes General-Purpose EPPI Modes The general-purpose (GP) EPPI modes accommodate a wide variety of data capture and transmission applications. Each EPPI has three bidirectional frame sync pins. The EPPI internally generates frame syncs, or an external device communicating with the EPPI generates them. GP modes differ based on the number of frame syncs used and the EPPI supports GP 0 FS—GP 3 FS modes.
Page 860 General-Purpose EPPI Modes General-Purpose 2 Frame Sync Mode This mode is useful for video applications that use two hardware synchronization signals, HSYNC and VSYNC. The HSYNC signal can be connected to EPPI_FS1 and the VSYNC signal can be connected to EPPI_FS2. Data Enable in General-Purpose 2 Frame Sync Transmit Mode The EPPI_FS3 pin functions as a data enable (DEN) pin, when EPPI is configured in GP 2 FS transmit mode and generating the frame sync internally.
Page 861 EPPI Operating Modes GP 3 FS mode is similar in operation to GP 2 FS mode. However, the start of frame synchronization in GP 3 FS also considers the state of the EPPI_FS3 pin. All the windowing register settings (EPPI_FRAME, EPPI_LINE, EPPI_HDLY, EPPI_HCNT, EPPI_VDLY, and registers), as well as data reception or transmission EPPI_VCNT...
Page 862 Supported Data Formats Table 18-11: EPPI Receive Data Formats (Continued) Input Data Width Use Model Splitting/Packing Options NTSC/PAL data Each EPPI word is zero filled or sign extended to 16 bits. EPPI_CTL.SPLTEO =1. EPPI_CTL.SUBSPLTODD =1 if necessary to separate chroma compo- nents.
Page 863 Supported Data Formats Table 18-11: EPPI Receive Data Formats (Continued) Input Data Width Use Model Splitting/Packing Options 8-bit luma/chroma pair for NTSC or EPPI_CTL.SPLTEO =1, EPPI_CTL.SPLTWRD =1, EPPI_CTL.SUBSPLTODD =1 if necessary to separate chroma compo- nents. 16-bit luma/chroma pair for NTSC EPPI_CTL.SPLTEO =1, EPPI_CTL.SPLTWRD =0, or HD EPPI_CTL.SUBSPLTODD =1 if necessary to separate chroma compo-...
Page 864 EPPI Operating Modes Table 18-12: EPPI Transmit Data Formats (Continued) Output Data Width Use Model Splitting/Packing Options DACs EPPI_CTL.SPLTEO =1, EPPI_CTL.SUBSPLTODD =0. DACs EPPI_CTL.SPLTEO =1, EPPI_CTL.SUBSPLTODD =0. 8-bit luma/chroma pair for NTSC EPPI_CTL.SPLTEO =1, EPPI_CTL.SPLTWRD =1, or HD EPPI_CTL.SUBSPLTODD =1 if the chroma components (U and V) come in separate DMA words.
Page 865 Data Transfer Modes • When EPPI_CTL.DLEN =24, the EPPI packs four 24-bit words into three 32-bit words. When EPPI_CTL.PACKEN =0, the EPPI receives the incoming data and sends it on the bus as-is. If EPPI_CTL.DLEN is less than or equal to 16 bits, the DMA is a 16-bit DMA; otherwise it is a 32-bit DMA. Data Packing for Transmit Modes For transmit modes, if the EPPI_CTL.DLEN bit =1 and the DMA is a 32-bit DMA, the EPPI unpacks the 32-bit word according to the EPPI_CTL.DLEN and EPPI_CTL.SWAPEN bit settings.
Page 866 Data Transfer Modes Split Transmit Modes The EPPI_CTL register has three control bits for split transmit modes: EPPI_CTL.SPLTEO, EPPI_CTL.SUBSPLTODD, and EPPI_CTL.DMACFG. The DMA is always a 32-bit DMA. Packing is not valid in split modes. • If EPPI_CTL.SPLTEO =1, the EPPI receives the Luma (Y3Y2Y1Y0) and interleaved Chroma (Cr1Cb1Cr0Cb0) data as 32 bits from the DMA channel.
Page 867 Data Transfer Modes PPI_CLK PPI_EN PPI_FS1 PPI_FS1D PPI_FS1W PPI_FS1W PPI_FS1P PPI_FS1P Figure 18-13: EPPI Delayed Frame Sync Generation Ignoring Premature External Frame Syncs for Data Consistency Once a frame has started with a VSYNC followed by an HSYNC (or both coming together), a line is tracked. When the count expires, the state machine waits at the end of line for an HSYNC to come.
Page 868 EPPI Event Control EPPI Status, Error, and Interrupt Signals The EPPI generates error interrupts (flagged in the register) when any one of the following error con- EPPI_STAT ditions occur. • EPPI_STAT.YFIFOERR (YFIFO underflow or overflow) • EPPI_STAT.CFIFOERR (CFIFO underflow or overflow) •...
Page 869 EPPI Status, Error, and Interrupt Signals When the EPPI_FRAME counter is running and a frame sync is detected, then an EPPI_STAT.FTERRUNDR is reported. Both errors generate an error interrupt. Perform a W1C operation to clear the interrupts at their respective locations in the status register.
Page 870 EPPI Programming Model 1. Provide active data frame in memory. 2. Set the EPPI_CTL.BLANKGEN bit so the EPPI generates blanking information. 3. Configure the EPPI_FS1_WLHB, EPPI_FS1_PASPL, EPPI_FS2_WLVB, EPPI_FS2_PALPF registers accordingly. 4. Configure the rest of the EPPI settings. 5. Configure DMA to fetch active frame data from memory buffers. 6.
Page 871 EPPI Programming Model NOTE: The EPPI_FRAME, EPPI_VDLY, and EPPI_VCNT registers have no effect in GP 1 FS mode. As a result, frame track errors and vertical windowing are not possible in this mode. 1. Configure GP 1 FS mode by setting the EPPI_CTL.XFRTYPE bit =b#11 and the EPPI_CTL.FSCFG bit =b#01.
Page 872 EPPI Programming Model 6. Program the EPPI_VDLY register to contain the number of lines to wait after the start of frame is detected. 7. Program the EPPI_VCNT register to contain the number of lines to receive or transmit. 8. If setting up the EPPI for transmit, the data enable (DEN) pin behaves according to the enabling of the blank- ing generation and the data length setting (DLEN).
Page 873 EPPI Programming Model 2. Program the EPPI_LINE register with the number of samples per line in the frame. 3. Program the EPPI_VDLY register with the number of lines to wait after the start of a new frame before start- ing to read or transmit data. 4.
Page 874 EPPI Mode Configuration Table 18-13: 8-Bit Receive Mode with Packing Enabled (Continued) Pin Data (8 bits) DMA DATA DMA DATA DMA DATA DMA DATA DMA DATA DMA DATA SKIPEN=0 SKIPEN=0 SKIPEN=1 SKIPEN=1 SKIPEN=1 SKIPEN=1 SKIPEO =X SKIPEO=X SKIPEO=1 SKIPEO=0 SKIPEO=1 SKIPEO=0 SWAPEN=0 SWAPEN=1...
Page 875 EPPI Mode Configuration Table 18-15: 10-Bit Receive Mode with Sign Extension, with Packing Enabled Pin Data (10 bits) DMA DATA DMA DATA DMA DATA SKIPEN=0 SKIPEN=0 SKIPEN=1 SKIPEO=X SKIPEO=X SKIPEO=1 SWAPEN=0 SWAPEN=1 SWAPEN=0 SIGNEXT=1 SIGNEXT=1 SIGNEXT=1 0x111 0x222 0xFE22 0111 0x0111 FE22 0x333 0xFF33 0111...
Page 876 EPPI Mode Configuration Table 18-17: 10-Bit Receive Mode, with Zero-Fill, with Packing Enabled Pin Data (10 DMA DATA DMA DATA DMA DATA DMA DATA DMA DATA DMA DATA bits) SKIPEN=0 SKIPEN=0 SKIPEN=1 SKIP_EN=1 SKIPEN=1 SKIPEN=1 SKIPEO=X SKIPEO=X SKIPEO=1 SKIP_EO=0 SKIPEO=1 SKIPEO=0 SWAPEN=0 SWAPEN=1...
Page 877 EPPI Mode Configuration EPPI_CTL.SKIPEO bits. The first incoming data can be placed either in the least significant bit positions or in the most significant bit positions, based on the EPPI_CTL.SWAPEN bit setting. Table 18-19: 16-Bit Receive Mode with Packing Enabled Pin Data (16 bits) DMA DATA DMA DATA...
Page 878 EPPI Mode Configuration skipped based on the EPPI_CTL.SKIPEN and EPPI_CTL.SKIPEO bits. The EPPI_CTL.SWAPEN bit has no effect. Table 18-21: 18-bit Receive Mode with Packing Disabled Pin Data (18 bits) DMA DATA DMA DATA DMA DATA SKIPEN=0 SKIPEN=1 SKIPEN=1 SKIPEO=X SKIPEO=1 SKIPEO=0 SWAPEN=X SWAPEN=X...
Page 879 EPPI Mode Configuration Table 18-23: 8-bit Split Receive Mode with SKIPEN = 0 and SWAPEN = 0 SPLTEO=1 SPLTEO=1 Data SUBSPLTODD= 0 SUBSPLTODD= 1 (8 bits) SWAPEN=0 SWAPEN=0 SKIPEN=0 SKIPEN=0 SKIPEO=X SKIPEO=X DMACFG=1 DMACFG=0 DMACFG=1 DMACFG=0 Primary Secondary Primary Primary Secondary Primary Channel...
Page 880 EPPI Mode Configuration Table 18-24: 8-bit Split Receive Mode with SKIPEN = 0 and SWAPEN = 1 Pin Data SPLTEO=1 SPLTEO=1 (8 bits) SUBSPLTODD=0 SUBSPLTODD=1 SWAPEN=1 SWAPEN=1 SKIPEN=0 SKIPEN=0 SKIPEO=X SKIPEO=X DMACFG=1 DMACFG=0 DMACFG=1 DMACFG=0 PRIMARY SECONDARY PRIMARY PRIMARY SECONDARY PRIMARY CHANNEL CHANNEL...
Page 881 EPPI Mode Configuration Configuring 10/12/14/16-Bit Split Receive Mode with SPLTWRD=0 For 16-bit split receive mode, the EPPI_CTL.PACKEN bit is not valid. The EPPI always packs two 16-bit words into one 32-bit word. For 10, 12, or 14-bit split receive modes, the EPPI first either sign-extends or zero-fills the incoming data into a 16-bit word.
Page 882 EPPI Mode Configuration Table 18-26: 16-bit Split Receive Mode with SPLTWRD = 0, SKIPEN = 0 and SWAPEN = 1 Pin Data SPLTEO=1 SPLTEO=1 (16 bits) SUBSPLTODD=0 SUBSPLTODD=1 SWAPEN=1 SWAPEN=1 SKIPEN=0 SKIPEN=0 SKIPEO=X SKIPEO=X DMACFG=1 DMACFG=0 DMACFG=1 DMACFG=0 PRIMARY SECONDARY PRIMARY PRIMARY SECONDARY...
Page 883 EPPI Mode Configuration Table 18-27: 16-bit Split Receive Mode with SPLTWRD = 1, SKIPEN = 0 and SWAPEN = 0 (Continued) Pin Data SPLTEO=1 SPLT_EVEN_ODD=1 (16 bits) SUBSPLTODD=0 SUBSPLTODD=1 SWAPEN=0 SWAPEN=0 SKIPEN=0 SKIPEN=0 SKIPEO=X SKIPEO=X DMACFG=1 DMACFG=0 DMACFG=1 DMACFG=0 Primary Secondary Primary Primary...
Page 884 EPPI Mode Configuration Table 18-28: 8-bit Transmit Mode with Packing Enabled (Continued) DMA Data (32 bits) Pin Data when SWAPEN=0 Pin Data when SWAPEN=1 0x55 0x88 Table 18-29: Data Sent in 8-bit Transmit Mode with Packing Disabled DMA Data (16 bits) Pin Data SWAPEN=X 0x1234 0x34...
Page 885 EPPI Mode Configuration Table 18-32: 16-bit Transmit Mode with Packing Enabled DMA Data (32 bits) Pin Data when SWAPEN=0 Pin Data when SWAPEN=1 0x1111 2222 0x2222 0x1111 0x3333 4444 0x1111 0x2222 0x4444 0x3333 0x3333 0x4444 Table 18-33: 16-bit Transmit Mode with Packing Disabled DMA Data (16 bits) Pin Data SWAPEN=X 0x1234...
Page 886 EPPI Mode Configuration Table 18-36: 8-bit Split Transmit Mode with SPLTEO=1, SUBSPLTODD=0 and SWAPEN=0 DMACFG=1 DMACFG=0 DMA0 DATA (32 bits) DMA1 DATA (32 bits) Pin Data (8 bits) DMA0 DATA (32 bits) Pin Data (8 bits) Table 18-37: 8-bit Split Transmit Mode with SPLTEO=1, SUBSPLTODD=1 and SWAPEN=0 DMACFG=1 DMACFG=0 DMA0 DATA (32 bits)
Page 887 EPPI Mode Configuration Table 18-37: 8-bit Split Transmit Mode with SPLTEO=1, SUBSPLTODD=1 and SWAPEN=0 (Continued) DMACFG=1 DMACFG=0 DMA0 DATA (32 bits) DMA1 DATA (32 bits) Pin Data (8 bits) DMA0 DATA (32 bits) Pin Data (8 bits) Table 18-38: 8-bit Split Transmit Mode with SPLTEO=1, SUBSPLTODD=0 and SWAPEN=1 DMACFG=1 DMACFG=0 DMA0 DATA (32 bits)
Page 888 EPPI Mode Configuration Table 18-39: 8-bit Split Transmit Mode with SPLTEO=1, SUBSPLTODD=1, and SWAPEN=1 DMACFG=1 DMACFG=0 DMA0 DATA (32 bits) DMA1 DATA (32 bits) Pin Data (8 bits) DMA0 DATA (32 bits) Pin Data (8 bits) Configuring 10/12/14/16-Bit Transmit Mode with SPLTWRD=0 For 16-bit split transmit mode, the EPPI_CTL.PACKEN bit is not valid.
Page 889 EPPI Mode Configuration Table 18-40: 16-bit Split Transmit Mode with SPLTEO = 1, SUBSPLTODD = 0, and SWAPEN = 0 (Continued) DMACFG = 1 DMACFG = 0 DMA0 DATA (32 bits) DMA1 DATA (32 bits) Pin Data (16 bits) DMA0 DATA (32 bits) Pin Data (16 bits) Table 18-41: 16-bit Split Transmit Mode with SPLTEO = 1, SUBSPLTODD = 1, and SWAPEN = 0 DMACFG = 1...
Page 890 EPPI Mode Configuration Table 18-43: 16-bit Split Transmit Mode with SPLTEO = 1, SUBSPLTODD = 1, and SWAPEN = 1 DMACFG = 1 DMACFG = 0 DMA0 DATA (32 bits) DMA1 DATA (32 bits) Pin Data (16 bits) DMA0 DATA (32 bits) Pin Data (16 bits) Configuring 16-Bit Split Transmit Mode with SPLTWRD=1 For 16-bit split transmit mode, the EPPI_CTL.PACKEN bit is not valid.
Page 891 EPPI Programming Model Table 18-45: 16-bit Split Transmit Mode with SPLTWRD = 1, SUBSPLTODD = 1, and SWAPEN = 0 (Continued) DMACFG = 1 DMACFG = 0 PRIMARY DMA DATA SECONDARY DMA Pin Data (16 bits) DMA0 DATA (32 bits) Pin Data (16 bits) (32 bits) DATA (32 bits)
Page 892 ADSP-SC58x EPPI Register Descriptions Table 18-47: ADSP-SC58x EPPI Register List Name Description EPPI_CLKDIV Clock Divide Register EPPI_CTL Control Register EPPI_CTL2 Control Register 2 Register EPPI_EVENCLIP Clipping Register for EVEN (Luma) Data Register EPPI_FRAME Lines Per Frame Register EPPI_FS1_DLY Frame Sync 1 Delay Value Register EPPI_FS1_PASPL FS1 Period Register / EPPI Active Samples Per Line Register EPPI_FS1_WLHB...
Page 893 ADSP-SC58x EPPI Register Descriptions Clock Divide Register register provides the divisor for EPPI internal clock generation. The generated clock frequen- EPPI_CLKDIV cy is given by following formula: EPPI_CLK = (SCLK1_0) / (EPPI_CLKDIV + 1) Note that a value of 0xFFFF is invalid for the EPPI_CLKDIV register.
Page 894 ADSP-SC58x EPPI Register Descriptions Control Register register configures the EPPI for operating mode, control signal polarities, and data width of the EPPI_CTL port. POLS (R/W) EN (R/W) Frame Sync Polarity PPI Enable POLC (R/W) DIR (R/W) Clock Polarity PPI Direction SIGNEXT (R/W) XFRTYPE (R/W) Sign Extension...
Page 895 ADSP-SC58x EPPI Register Descriptions Table 18-49: EPPI_CTL Register Fields Bit No. Bit Name Description/Enumeration (Access) CLKGATEN Clock Gating Enable. (R/W) The EPPI_CTL.CLKGATEN bit enables using the EPPI_FS3 pin as a clock gating pin. When EPPI_CTL.CLKGATEN is set, the EPPI_FS3 pin acts as a clock gating signal, and both the internal and external clock are gated.
Page 896 ADSP-SC58x EPPI Register Descriptions Table 18-49: EPPI_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) SPLTWRD Split Word. (R/W) The EPPI_CTL.SPLTWRD bit selects split word data placement when the data length (EPPI_CTL.DLEN) selects 16-, 20-, or 24-bit data words. For all other EPPI_CTL.SPLTWRD values, the set or clear selections for EPPI_CTL.SPLTWRD produce the same result (act as though EPPI_CTL.SPLTWRD is cleared).
Page 897 ADSP-SC58x EPPI Register Descriptions Table 18-49: EPPI_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PACKEN Pack/Unpack Enable. (R/W) The EPPI_CTL.PACKEN select whether or not packing is enabled (for receive modes) and unpacking is enabled (for transmit modes). When this bit is set, EPPI transfer DMA is 32-bits wide.
Page 898 ADSP-SC58x EPPI Register Descriptions Table 18-49: EPPI_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) 0 8 bits 1 10 bits 2 12 bits 3 14 bits 4 16 bits 5 18 bits 6 20 bits 7 24 bits 15:14 POLS Frame Sync Polarity.
Page 899 ADSP-SC58x EPPI Register Descriptions Table 18-49: EPPI_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) SIGNEXT Sign Extension. (R/W) The EPPI_CTL.SIGNEXT select whether (for receive modes when EPPI_CTL.DLEN selecting 16 bit data length) the data is sign extended or zero fil- led.
Page 900 ADSP-SC58x EPPI Register Descriptions Table 18-49: EPPI_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) FLDSEL Field Select/Trigger. (R/W) The EPPI_CTL.FLDSEL bits configure the EPPI field and trigger selection. These are valid for GP modes (EPPI_CTL.XFRTYPE =0x3) and ITU656 active video mode (EPPI_CTL.XFRTYPE cleared).
Page 901 ADSP-SC58x EPPI Register Descriptions Table 18-49: EPPI_CTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) XFRTYPE Transfer Type ( Operating Mode). (R/W) The EPPI_CTL.XFRTYPE bits select the EPPI operating mode. In receive mode (EPPI_CTL.DIR cleared), the EPPI modes include ITU656 active video only mode, ITU656 entire field mode, ITU656 vertical blanking only mode, and non-ITU656 mode (GP mode).
Page 902 ADSP-SC58x EPPI Register Descriptions Control Register 2 Register register controls HSYNC finish signal generation. EPPI_CTL2 FS1FINEN (R/W) HSYNC Finish Enable Figure 18-16: EPPI_CTL2 Register Diagram Table 18-50: EPPI_CTL2 Register Fields Bit No. Bit Name Description/Enumeration (Access) FS1FINEN HSYNC Finish Enable. (R/W) The EPPI_CTL2.FS1FINEN bit selects whether (if set) the EPPI sends a finish command (010) through the DDE COMMAND line soon after a LINE is received...
Page 903 ADSP-SC58x EPPI Register Descriptions Clipping Register for EVEN (Luma) Data Register register selects the clipping threshold for luma data, which provides clipping of individual EPPI_EVENCLIP video components. The high even and low even spaces in are 16-bits wide and (depending on the EPPI_EVENCLIP EPPI_CTL.DLEN bit selection) only the corresponding video component bits are considered for clipping.
Page 904 ADSP-SC58x EPPI Register Descriptions Lines Per Frame Register register tracks the frame track overflow and underflow errors. This register should be program- EPPI_FRAME med with the number of lines expected per frame. Any write to the EPPI_FRAME register will also write the same value to the EPPI_VCNT register.
Page 905 ADSP-SC58x EPPI Register Descriptions Frame Sync 1 Delay Value Register register selects the delay count (based on the period of the EPPI_CLK clock) between the EPPI_FS1_DLY first rising edge of EPPI_CLK after the EPPI is enabled and the first active edge of the associated frame sync when the internal frame sync is used.
Page 906 ADSP-SC58x EPPI Register Descriptions FS1 Period Register / EPPI Active Samples Per Line Register register content varies depending on whether the EPPI is in GP1/2/3 FS modes or in GP EPPI_FS1_PASPL transmit mode. In GP 1, 2, or 3 FS modes, the register is used for the generation of frame sync 1.
Page 907 ADSP-SC58x EPPI Register Descriptions FS1 Width Register / EPPI Horizontal Blanking Samples Per Line Register register's content varies depending on whether the EPPI is in GP1/2/3 FS modes or in GP EPPI_FS1_WLHB transmit mode. In GP 1, 2 or 3 FS modes, is used for the generation of frame sync 1.
Page 908 ADSP-SC58x EPPI Register Descriptions Frame Sync 2 Delay Value Register register selects the delay count (based on the period of the EPPI_CLK clock) between the EPPI_FS2_DLY first rising edge of EPPI_CLK after EPPI enabled and the first active edge of the associated frame sync when the internal frame sync is used.
Page 909 ADSP-SC58x EPPI Register Descriptions FS2 Period Register / EPPI Active Lines Per Field Register register content varies depending on whether the EPPI is in GP2/3 FS modes or in GP EPPI_FS2_PALPF transmit mode. In GP 2 or 3 FS modes, is used for the generation of frame sync 2.
Page 910 ADSP-SC58x EPPI Register Descriptions FS2 Width Register / EPPI Lines Of Vertical Blanking Register register content varies depending on whether the EPPI is in GP2/3 FS modes or in GP EPPI_FS2_WLVB transmit mode. In GP 2 or 3 FS modes, the register is used for the generation of frame sync 2.
Page 911 ADSP-SC58x EPPI Register Descriptions Horizontal Transfer Count Register register holds the number of samples to read in or write out per line, after number EPPI_HCNT EPPI_HDLY of cycles have expired since the assertion of EPPI_FS1. Any write to the EPPI_LINE register modifies the EPPI_HCNT register.
Page 912 ADSP-SC58x EPPI Register Descriptions Horizontal Delay Count Register register contains the number of clock cycles to delay after the assertion of EPPI_FS1 is detected EPPI_HDLY before starting to read or write data. VALUE (R/W) Horizontal Delay Count Figure 18-26: EPPI_HDLY Register Diagram Table 18-60: EPPI_HDLY Register Fields Bit No.
Page 913 ADSP-SC58x EPPI Register Descriptions Interrupt Mask Register register permits the masking (if associated bit is set) of EPPI error interrupts for YFIFO under- EPPI_IMSK flow or overflow, CFIFO underflow or overflow, line track overflow error, line track underflow error, frame track overflow error, frame track underflow error, and ERR_NCOR (ITU preamble error not corrected.
Page 914 ADSP-SC58x EPPI Register Descriptions Table 18-61: EPPI_IMSK Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) LTERRUNDR Line Track Underflow Error Interrupt Mask. (R/W) 0 Unmask Interrupt 1 Mask Interrupt LTERROVR Line Track Overflow Error Interrupt Mask. (R/W) 0 Unmask Interrupt 1 Mask Interrupt YFIFOERR YFIFO Underflow or Overflow Error Interrupt Mask.
Page 915 ADSP-SC58x EPPI Register Descriptions Samples Per Line Register register tracks the line track overflow and underflow errors. This register should be programmed EPPI_LINE with the number of samples expected per line. Any write to the EPPI_LINE register will also write the same value to the EPPI_HCNT register.
Page 916 ADSP-SC58x EPPI Register Descriptions Clipping Register for ODD (Chroma) Data Register register selects the clipping threshold for chroma data, which provides clipping of individual EPPI_ODDCLIP video components. The high odd and low odd spaces in are 16-bits wide and (depending on the EPPI_CTL.DLEN EPPI_ODDCLIP bit selection) only the corresponding video component bits are considered for clipping.
Page 917 ADSP-SC58x EPPI Register Descriptions Status Register register contains bits that provide information about the current operating state of the EPPI. EPPI_STAT FLD (R) CFIFOERR (R/W1C) Current Field Received by EPPI Chroma FIFO Error ERRDET (R/W1C) YFIFOERR (R/W1C) Preamble Error Detected Luma FIFO Error PXPERR (R/W1C) LTERROVR (R/W1C)
Page 918 ADSP-SC58x EPPI Register Descriptions Table 18-64: EPPI_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) ERRNCOR Preamble Error Not Corrected. (R/W1C) The EPPI_STAT.ERRNCOR bit is useful only in the ITU receive modes and indi- cates if an error in the status word of EAV or SAV sequences can not be cleared (if set) or not (if clear).
Page 919 ADSP-SC58x EPPI Register Descriptions Table 18-64: EPPI_STAT Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) YFIFOERR Luma FIFO Error. (R/W1C) For RX modes, the EPPI_STAT.YFIFOERR bit indicates whether the Luma FIFO has overflowed (if set) or not (if clear). For TX modes, this bit indicates whether the Luma FIFO has underflowed (if set) or not (if clear).
Page 920 ADSP-SC58x EPPI Register Descriptions Vertical Transfer Count Register register holds the number of lines to read in or write out, after number of lines EPPI_VCNT EPPI_VDLY from the start of frame. Any write to the EPPI_FRAME register modifies the EPPI_VCNT register.
Page 921 ADSP-SC58x EPPI Register Descriptions Vertical Delay Count Register register contains the number of lines to wait after the start of a new frame before starting to read/ EPPI_VDLY transmit data. VALUE (R/W) Vertical Delay Count Figure 18-32: EPPI_VDLY Register Diagram Table 18-66: EPPI_VDLY Register Fields Bit No.
Page 922 Pulse-Width Modulator (PWM) 19 Pulse-Width Modulator (PWM) The pulse-width modulator (PWM) module is a flexible and programmable waveform generator. With minimal CPU intervention, the PWM peripheral can generate complex waveforms for: • Motor control • Pulse-coded modulation (PCM) • Digital-to-analog conversion (DAC) •...
Page 923 Functional Description • Timer Units • Channel Timing Control Unit • Output Disable and Cross-Over Modes • Sync Operation Modes ADSP-SC58x PWM Register List The Pulse-Width Modulator unit (PWM) includes multiple timers (providing period flexibility) and channels (pro- viding mode, interrupt, and pulse shape flexibility), permitting a wide variety of PWM output options for motor control and other applications.
Page 924 Functional Description Table 19-1: ADSP-SC58x PWM Register List (Continued) Name Description PWM_BL0_HP Channel B-Low Heightened-Precision Duty-0 Register PWM_BL1 Channel B-Low Duty-1 Register PWM_BL1_HP Channel B-Low Heightened-Precision Duty-1 Register PWM_BL_DUTY0 Channel B-Low Full Duty0 Register PWM_BL_DUTY1 Channel B-Low Full Duty1 Register PWM_CCTL Channel C Control Register PWM_CH0...
Page 925 Functional Description Table 19-1: ADSP-SC58x PWM Register List (Continued) Name Description PWM_DH_DUTY1 Channel D-High Full Duty1 Register PWM_DL0 Channel D-Low Pulse Duty Register 0 PWM_DL0_HP Channel D-Low Heightened-Precision Duty-0 Register PWM_DL1 Channel D-Low Pulse Duty Register 1 PWM_DL1_HP Channel D-Low Heightened-Precision Duty-1 Register PWM_DLYA Channel A Delay Register PWM_DLYB...
Page 926 Functional Description Table 19-2: ADSP-SC58x PWM Interrupt List (Continued) Interrupt Name Description Sensitivity Channel PWM2_TRIP PWM2 Trip Level ADSP-SC58x PWM Trigger List Table 19-3: ADSP-SC58x PWM Trigger List Masters Trigger ID Name Description Sensitivity PWM0_SYNC PWM0 PWMTMR Grouped Edge PWM1_SYNC PWM1 PWMTMR Grouped Edge PWM2 PWMTMR Grouped...
Page 927 Functional Description recover its blocking capability before the complementary switch is turned on. This time delay prevents a potentially destructive short-circuit condition from developing across the dc link capacitor of a typical voltage source inverter. Duty Cycle The proportion of on time to the regular interval or period of time (expressed in percent, 100% being fully on). A low duty cycle corresponds to low power, because the power is off for most of the time.
Page 928 Architectural Concepts SYNC PWM_CTL PWM_SYNC_OUT GENERATION PWM_SYNC_WID SECURITY PWMTMR0 PWM_TM0 PWM_TRIPCFG PWM_DT PWM_CHOPCFG CONTROL PWM_AH0, PWM_AL0 DEAD-TIME CHANNEL A PWM_TM1 PWMTMR1 TIMING CONTROL UNIT GATE DRIVE PWM_DLY1 UNIT PWM_BH0, PWM_BL0 DEAD-TIME CHANNEL B PWM_TM2 PWMTMR2 TIMING CONTROL UNIT GATE DRIVE PWM_DLY2 UNIT TRIP...
Page 929 Timer Units • The register value of the timer must be equal to the PWM_TM0 register value. • The PWM_TM0 value must be an integer multiple of each register of the timer. Non-integer multiples are not allowed. PWM Timer Period (PWM_TM) Registers The 16-bit read/write PWM period registers (PWM_TM0 through PWM_TM4) control the PWM switching frequen-...
Page 930 Timer Units PWM_TMx = 12 Count till (PWM_TMx-1)/2 Count till -(PWM_TMx-1)/2 Same as previous count PWMTMRx Same as previous count Load (PWM_TMx-1)/2 Load (PWM_TMx-1)/2 Load -(PWM_TMx-1)/2 TMRxPHASE PWM_SYNC Figure 19-2: Operation of Timer for Odd Value of PWM_TM When the timer register value is even, for example 12, then that timer loads +5 at the beginning of the period. The timer counts from +5 to –6 in the first half, reloads –5 at the midpoint and counts up from –5 to +6 in the second half.
Page 931 Timer Units NOTE: In the operation discussed in this section, double-buffering of all channel registers and the timer registers takes place at the period boundary of the respective timers. Phase Offset Control The PWM timers (PWMTMR1 through PWMTMR4) can operate with a programmable phase lag relative to the main timer, PWMTMR0.
Page 932 Timer Units • The outputs of Channel A are referenced to PWMTMR1. The outputs of channel B are referenced to PWMTMR2. PWMTMR0 DELAY1 DELAY1 DELAY1 DELAY1 PWMTMR1 DELAY2 DELAY2 DELAY2 DELAY2 PWMTMR2 Figure 19-4: Phase Offset Control Using DELAY The delay registers are double buffered and the new value of DELAY reloads at the period boundary of PWMTMR0.
Page 933 Timer Units PWMTMR0 PWM_BH More than one period Less than one period CASE A: Increasing DELAY CASE B: Decreasing DELAY DELAY1 DELAY2 DELAY1 PWM_DLYA TMR1 forced to restart period TMR1 waits PWMTMR1 PWM_AH Figure 19-5: Impact of New DELAY Value on Timer Count for Equal Timer Periods Case 2: PWM_TM0 = N x PWM_TMy In this case, within a single period of PWMTMR0 a program can fit multiple periods (N) of PWMTMRy.
Page 934 Architectural Concepts Channel Timing Control Unit The channel timing control unit is the core of the PWM. There are four separate channels, each channel controlling a pair of output signals – the high-side output and the low-side output. Channel Control PWM_CHANCFG register controls the static configuration of all the channels and is initialized once before the beginning of a PWM operation.
Page 935 Channel Timing Control Unit The following section explains dead time in detail. • Switching Dead Time (PWM_DT) Register Values programmed into these registers that fall outside these limits result in over or under modulation. NOTE: Duty Cycle and Pulse Positioning Control The PWM_ACTL.PULSEMODEHI and PWM_ACTL.PULSEMODELO fields control how the duty cycle registers modify the waveform of the high and low-side outputs.
Page 936 Channel Timing Control Unit Centre of Period Centre of Period DUTY1 DUTY0 DUTY0 count count PWM_AH PWM_AH De-assert for Assert for count < DUTY0 Assert for count < DUTY0 count > DUTY1 De-assert for count > DUTY1 PULSEMODE = 01 PULSEMODE = 00 DUTY1 DUTY...
Page 937 Channel Timing Control Unit DUTY0 Zero Dead-Time PWM_AH PWM_AL Non-zero Dead-Time PWM_AH PWM_AL PULSEMODE = 00 Figure 19-8: Channel Outputs in Dependent Mode for Pulse Mode = 00 DUTY1 DUTY0 Zero Dead-Time PWM_AH PWM_AL Non-zero Dead-Time PWM_AH PWM_AL PULSEMODE = 01 Figure 19-9: Channel Outputs in Dependent Mode for Pulse Mode = 01 The following pair of figures shows the high and low-side outputs for the case with zero and non-zero dead-time for PWM_ACTL.PULSEMODEHI =10 and 11.
Page 938 Channel Timing Control Unit DUTY0 DUTY1 Case with Zero Dead-time PWM_AH PWM_AL Case with non-zero dead-time PWM_AH PWM_AL PULSEMODE = 10 Figure 19-10: Channel Outputs in Dependent Mode for Pulse Mode = 10 DUTY1 DUTY0 Case with Zero Dead-time PWM_AH PWM_AL Case with non-zero dead-time PWM_AH...
Page 939 Channel Timing Control Unit • Uses the PWM_ACTL.PULSEMODEHI bit to configure pulse position • Uses the PWM_CHANCFG.POLAH bit to configure polarity • Generates PWM_AL using PWM_AL0 • Uses the PWM_AL1 register to configure pulse width • Uses the PWM_ACTL.PULSEMODELO bit to configure pulse position •...
Page 940 Channel Timing Control Unit -PWM_TM/2 +PWM_TM/2 +PWM_TM/2 COUNT PWM_CH0 PWM_CH0 PWM_AH PWM_AL 2 × DT 2 × DT PWM_SYNC_OUT PWM_TM PWM_TM PWM_PHASE Figure 19-13: Channel Outputs Controlled Independently Switched Reluctance Motors Application In typical power converter configurations for switched or variable reluctance motors, motor winding is connected between the two power switches of a given inverter leg.
Page 941 Channel Timing Control Unit -PWM_TM/2 +PWM_TM/2 +PWM_TM/2 COUNT PWM_AH0 2 PWM_AH0 1 PWM_AH HARD CHOP PWM_AL0 1 PWM_AL0 2 PWM_AL PWM_AH0 2 PWM_AH0 1 PWM_AH ALTER- NATE PWM_AL0 2 CHOP PWM_AL0 1 PWM_AL PWM_AH0 2 PWM_AH0 1 PWM_AH SOFT CHOP- BOTTOM PWM_AL PWM_AH...
Page 942 Channel Timing Control Unit (PWM_CHA_DT through PWM_CHD_DT). The unit in this case produces active low signals so that a low level corre- sponds to a command to turn-on the associated power device. The Dead Time Between Outputs in Dependent Mode figure shows a typical pair of PWM outputs, PWM_AH and PWM_AL.
Page 943 Channel Timing Control Unit The negative values of T and T are not permitted and the minimum permissible value is zero, corresponding to a 0% duty cycle. In a similar fashion, the maximum value is T , the PWM switching period, corresponding to a 100% duty cycle.
Page 944 Channel Timing Control Unit In pulse mode 10, a PWM channel is in full off modulation if the high-side output of that channel is deasserted. The output is deasserted for the whole duration of the first half period of the PWM timer that the channel is refer- encing.
Page 945 Architectural Concepts -PWM_TMy/2 +PWM_TMy/2 +PWM_TMy/2 PWM_TM PWM_TM PWM_AH FULL ON PWM_AL 2 × DT EMERGENCY DEADTIME PULSEMODE 10 Figure 19-16: Over Modulation Transition Example Gate Drive Unit The gate drive unit of the PWM adds features that simplify the design of isolated gate drive circuits for PWM inver- ters.
Page 946 Functional Description Output Control Feature Precedence The order of applying output control features to the PWM signal is important and significant. Use the following order for applying the signal features to the PWM output signal. 1. Duty generation 2. Cross-over 3.
Page 947 Operating Modes are connected through the pin mux to configurable trigger masters using PWM master IDs TRGM_SYS_PWMn_SYNC_IN. Using the TRU, these masters can be connected to the PWM_SYNC trigger slaves in any desired combination. • A TTU trigger output. This option can include a member of a TTU trigger group, which can also control the timing of other devices such as ADCs, SINC filter inputs, or GP timers.
Page 948 Output Disable and Cross-Over Modes The low-side output remains off, as in the case without crossover. The difference in cross-over is that the high-side output changes character and becomes like the low-side. What actually occurs is that the low-side duty cycle is sent to the high-side output pins, and the high-side duty cycle is sent to the low side pins.
Page 949 Operating Modes -PWM_TM/2 +PWM_TM/2 +PWM_TM/2 COUNT PWM_AH0=PWM_CH0 PWM_AH0=PWM_CH0 PWM_AH PWM_AL PWM_BH 2 × DT 2 × DT PWM_BL PWM_CH PWM_CL Figure 19-19: ECM Control Heightened-Precision Edge Placement Heightened-precision edge placement allows a fine-grained edge placement within the system clock period. The Heightened-Precision Steps in a Single SCLK Period figure shows how the SCLK0_0 aligned edge is moved to finer resolution.
Page 950 Operating Modes PWM_AH0 PWM_AH0_HP -1 -2 -3 -4 -5 -6 -7 -8 Figure 19-21: Duty Cycle Notation for Heightened-Precision Edge Placement In the normal modes of operation (not involving heightened-precision edge placement), only the PWM_AH0 register value is programmed. The duty value programmed is a two’s complement integer value. If a value of -1 is desired, register is programmed with the number 0xFFFF (which is the two’s complement of 1 in 16 bits).
Page 951 Heightened-Precision Edge Placement [15:12] of represent the decimal part or heightened-precision value and bits [31:16] represent the coarse duty cycle. Sample Waveforms for High- and Low-Side with Precision Placement When the PWM module uses heightened-precision in the dependent mode of operation, both high and low-side outputs shift in the same direction.
Page 952 Heightened-Precision Edge Placement Figure 19-23: Precision Placement: PULSEMODE=01 Figure 19-24: Precision Placement: PULSEMODE=10 Figure 19-25: Precision Placement: PULSEMODE=11 ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference 19–31...
Page 953 Operating Modes Emulation Mode Depending upon system configuration, a debug halt may be presented to the PWM unit. The PWM has local con- trol of its response to an emulator halt based on the PWM_CTL.EMURUN bit setting. • PWM_CTL.EMURUN =1. When the processor is halted in emulation mode, the outputs continue to toggle and be driven out of the PWM block.
Page 954 Event Control Status information about the PWM is available in the PWM_STAT register, which stores all status bits, including raw interrupt status bits. In particular, the period boundary of each timer is available, as well as status bits. The PWM uses the status bits to indicate whether the operation is in the first half or the second half of the timer.
Page 955 Programming Model called a self-restart trip condition. If the trip condition is not active at the next period boundary of the PWMTMRy that the channel is using, the status register bit is cleared. The outputs are restored. The trip input pins have an external pull-down resistor on the chip pin. If the pin becomes disconnected, the pro- cessor disables the PWM.
Page 956 Programming Model The typical three-phase AC motor configuration shown in the PWM Module and Interaction with System figure applies for both permanent magnet and induction motor types. S ETUP AND CONTROL H W CONFIGURATION P W M CONFIGURATION CONTROL G LOBAL SYSTEM PARAMETERS D UTY A DUTY B...
Page 957 Programming Model for Three-Phase AC Motor Control INIT PWM MOTOR STOPPED ENABLE PWM STOP PWM MOTOR RUNNING PWM SYNC IRQ Figure 19-27: PWM System States As shown in the state diagram, the module configuration is updated on state transitions (indicated by the arrows). The transitions are initialization, motor start, PWM sync interrupt request (on each), and motor stop.
Page 958 Programming Model for Three-Phase AC Motor Control • Low-side is always the inverse of high-side (PWM_CHANCFG.POLAL through PWM_CHANCFG.POLDL = 1). • System uses active high gate driver (PWM_CHANCFG.ENCHOPAH through PWM_CHANCFG.ENCHOPDH =1). • Disable gate chopping (PWM_CHANCFG.ENCHOPAL through PWM_CHANCFG.ENCHOPDL =0). PWM does not use the pulse transformer. 2.
Page 959 Programming Model for Three-Phase AC Motor Control • Disable all outputs (PWM_ACTL.DISHI through PWM_CCTL.DISHI =0, PWM_ACTL.DISLO through PWM_CCTL.DISLO =0) • Use conventional PWM, disable crossover (PWM_ACTL.XOVR through PWM_CCTL.XOVR =0) • Use symmetrical pulse position on all outputs (PWM_ACTL.PULSEMODEHI through PWM_CCTL.PULSEMODEHI =0, PWM_ACTL.PULSEMODELO through PWM_CCTL.PULSEMODELO =0) •...
Page 960 Programming Model for Three-Phase AC Motor Control PWM_AH0 = Duty_A_mc_algorithm_current_value PWM_BH0 = Duty_B_mc_algorithm_current_value PWM_CH0 = Duty_C_mc_algorithm_current_value PWM Disable (and Stop the Motor) for Motor Control The processor must program the PWM as follows to stop the motor, disable the PWM, and disable PWM inter- rupts.
Page 961 ADSP-SC58x PWM Register Descriptions Table 19-5: ADSP-SC58x PWM Register List (Continued) Name Description PWM_AH0 Channel A-High Duty-0 Register PWM_AH0_HP Channel A-High Heightened-Precision Duty-0 Register PWM_AH1 Channel A-High Duty-1 Register PWM_AH1_HP Channel A-High Heightened-Precision Duty-1 Register PWM_AH_DUTY0 Channel A-High Full Duty0 Register PWM_AH_DUTY1 Channel A-High Full Duty1 Register PWM_AL0...
Page 962 ADSP-SC58x PWM Register Descriptions Table 19-5: ADSP-SC58x PWM Register List (Continued) Name Description PWM_CHA_DT Channel A Dead-time Register PWM_CHB_DT Channel B Dead-time Register PWM_CHC_DT Channel C Dead-time Register PWM_CHD_DT Channel D Dead-time Register PWM_CHOPCFG Chop Configuration Register PWM_CH_DUTY0 Channel C-High Full Duty0 Register PWM_CH_DUTY1 Channel C-High Full Duty1 Register PWM_CL0...
Page 963 ADSP-SC58x PWM Register Descriptions Table 19-5: ADSP-SC58x PWM Register List (Continued) Name Description PWM_ILAT Interrupt Latch Register PWM_IMSK Interrupt Mask Register PWM_STAT Status Register PWM_SYNC_WID Sync Pulse Width Register PWM_TM0 Timer 0 Period Register PWM_TM1 Timer 1 Period Register PWM_TM2 Timer 2 Period Register PWM_TM3 Timer 3 Period Register...
Page 964 ADSP-SC58x PWM Register Descriptions Channel A Control Register register selects the low and high side output pulse mode, enables low and high side output, and PWM_ACTL enables low/high side output crossover. PULSEMODELO (R/W) DISHI (R/W) Low Side Output Pulse Position Channel High Side Output Disable PULSEMODEHI (R/W) DISLO (R/W)
Page 965 ADSP-SC58x PWM Register Descriptions Table 19-6: PWM_ACTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PULSEMODEHI High Side Output Pulse Position. (R/W) The PWM_ACTL.PULSEMODEHI bits select the pulse position for Channel A high side output. In symmetrical mode, the channel forms a symmetrical pulse waveform around the center of the PWM period.
Page 966 ADSP-SC58x PWM Register Descriptions Channel A-High Duty-0 Register registers determine the width for the high side output pulses. The values in these PWM_AH0 PWM_AH1 registers select the assertion count (in terms of t ) of the high side output pulses for the channel A duty cycle. The operation of the duty-cycle registers varies, depending on the pulse mode selected with the PWM_ACTL.PULSEMODEHI bits.
Page 967 ADSP-SC58x PWM Register Descriptions Channel A-High Heightened-Precision Duty-0 Register register provides a fine-grained edge placement within the system clock period. This register, in PWM_AH0_HP conjunction with the PWM_AH0 register, allows programs to specify fractional duty cycles.The PWM_AH0_HP regis- ter and the PWM_AH0 register work together in a Q15.8 signed two’s complement fixed-point format.
Page 968 ADSP-SC58x PWM Register Descriptions Channel A-High Duty-1 Register registers determine the width for the high side output pulses. For more information, PWM_AH0 PWM_AH1 see the PWM_AH0 register description. DUTY (R/W) Duty Cycle De-Asserted Count Figure 19-31: PWM_AH1 Register Diagram Table 19-9: PWM_AH1 Register Fields Bit No.
Page 969 ADSP-SC58x PWM Register Descriptions Channel A-High Heightened-Precision Duty-1 Register register provides a fine-grained edge placement within the system clock period. This register, in PWM_AH1_HP conjunction with the PWM_AH0 register, allows programs to specify fractional duty cycles.The PWM_AH1_HP regis- ter and the PWM_AH1 register work together in a Q15.8 signed two’s complement fixed-point format.
Page 970 ADSP-SC58x PWM Register Descriptions Channel A-High Full Duty0 Register The full duty registers can be used instead of the combined duty and heightened-precision duty registers.The register contains the PWM_AH_DUTY0.DUTY bit field from the register and the PWM_AH_DUTY0 PWM_AH0 PWM_AH_DUTY0.ENHDIV bit field from the PWM_AH0_HP register.
Page 971 ADSP-SC58x PWM Register Descriptions Channel A-High Full Duty1 Register The full duty registers can be used instead of the combined duty and heightened-precision duty registers.The register contains the PWM_AH_DUTY1.DUTY bit field from the register and the PWM_AH_DUTY1 PWM_AH1 PWM_AH_DUTY1.ENHDIV bit field from the PWM_AH1_HP register.
Page 972 ADSP-SC58x PWM Register Descriptions Channel A-Low Duty-0 Register registers determine the width for the low side output pulses. The values in these PWM_AL0 PWM_AL1 registers select the assertion count (in terms of t ) of the low side output pulses for the channel A duty cycle. The operation of the duty-cycle registers varies, depending on the pulse mode selected with the PWM_ACTL.PULSEMODELO bits.
Page 973 ADSP-SC58x PWM Register Descriptions Channel A-Low Heightened-Precision Duty-0 Register register provides a fine-grained edge placement within the system clock period. This register, in PWM_AL0_HP conjunction with the PWM_AL0 register, allows programs to specify fractional duty cycles.The PWM_AL0_HP regis- ter and the PWM_AL0 register work together in a Q15.8 signed two’s complement fixed-point format.
Page 974 ADSP-SC58x PWM Register Descriptions Channel A-Low Duty-1 Register registers determine the width for the low side output pulses. For more information, PWM_AL0 PWM_AL1 see the PWM_AL0 register description. DUTY (R/W) Duty Cycle De-Asserted Count Figure 19-37: PWM_AL1 Register Diagram Table 19-15: PWM_AL1 Register Fields Bit No.
Page 975 ADSP-SC58x PWM Register Descriptions Channel A-Low Heightened-Precision Duty-1 Register register provides a fine-grained edge placement within the system clock period. This register, in PWM_AL1_HP conjunction with the PWM_AL1 register, allows programs to specify fractional duty cycles.The PWM_AL1_HP regis- ter and the PWM_AL1 register work together in a Q15.8 signed two’s complement fixed-point format.
Page 976 ADSP-SC58x PWM Register Descriptions Channel A-Low Full Duty0 Register The full duty registers can be used instead of the combined duty and heightened-precision duty registers.The register contains the PWM_AL_DUTY0.DUTY bit field from the register and the PWM_AL_DUTY0 PWM_AL0 PWM_AL_DUTY0.ENHDIV bit field from the PWM_AL0_HP register.
Page 977 ADSP-SC58x PWM Register Descriptions Channel A-Low Full Duty1 Register The full duty registers can be used instead of the combined duty and heightened-precision duty registers.The register contains the PWM_AL_DUTY1.DUTY bit field from the register and the PWM_AL_DUTY1 PWM_AL1 PWM_AL_DUTY1.ENHDIV bit field from the PWM_AH0_HP register.
Page 978 ADSP-SC58x PWM Register Descriptions Channel B Control Register register selects the low and high side output pulse mode, enables low and high side output, and PWM_BCTL enables low/high side output crossover. PULSEMODELO (R/W) DISHI (R/W) Low Side Output Pulse Position Channel High Side Output Disable PULSEMODEHI (R/W) DISLO (R/W)
Page 979 ADSP-SC58x PWM Register Descriptions Table 19-19: PWM_BCTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PULSEMODEHI High Side Output Pulse Position. (R/W) The PWM_BCTL.PULSEMODEHI bits select the pulse position for Channel B high side output. In symmetrical mode, the channel forms a symmetrical pulse waveform around the center of the PWM period.
Page 980 ADSP-SC58x PWM Register Descriptions Channel B-High Duty-0 Register registers determine the width for the high side output pulses. The values in these PWM_BH0 PWM_BH1 registers select the assertion count (in terms of t ) of the high side output pulses for the channel B duty cycle. The operation of the duty-cycle registers varies, depending on the pulse mode selected with the PWM_BCTL.PULSEMODEHI bits.
Page 981 ADSP-SC58x PWM Register Descriptions Channel B-High Heightened-Precision Duty-0 Register register provides a fine-grained edge placement within the system clock period. This register, in PWM_BH0_HP conjunction with the PWM_BH0 register, allows programs to specify fractional duty cycles. The PWM_BH0_HP reg- ister and the PWM_BH0 register work together in a Q15.8 signed two’s complement fixed-point format.
Page 982 ADSP-SC58x PWM Register Descriptions Channel B-High Duty-1 Register registers determine the width for the high side output pulses. For more information, PWM_BH0 PWM_BH1 see the PWM_BH0 register description. DUTY (R/W) Duty Cycle De-Asserted Count Figure 19-44: PWM_BH1 Register Diagram Table 19-22: PWM_BH1 Register Fields Bit No.
Page 983 ADSP-SC58x PWM Register Descriptions Channel B-High Heightened-Precision Duty-1 Register register provides a fine-grained edge placement within the system clock period. This register, in PWM_BH1_HP conjunction with the PWM_BH1 register, allows programs to specify fractional duty cycles. The PWM_BH1_HP reg- ister and the PWM_BH1 register work together in a Q15.8 signed two’s complement fixed-point format.
Page 984 ADSP-SC58x PWM Register Descriptions Channel B-High Full Duty0 Register The full duty registers can be used instead of the combined duty and heightened-precision duty registers.The register contains the PWM_BH_DUTY0.DUTY bit field from the register and the PWM_BH_DUTY0 PWM_BH0 PWM_BH_DUTY0.ENHDIV bit field from the PWM_BH0_HP register.
Page 985 ADSP-SC58x PWM Register Descriptions Channel B-High Full Duty1 Register The full duty registers can be used instead of the combined duty and heightened-precision duty registers.The register contains the PWM_BH_DUTY1.DUTY bit field from the register and the PWM_BH_DUTY1 PWM_BH1 PWM_BH_DUTY1.ENHDIV bit field from the PWM_BH1_HP register.
Page 986 ADSP-SC58x PWM Register Descriptions Channel B-Low Duty-0 Register registers determine the width for the low side output pulses. The values in these PWM_BL0 PWM_BL1 registers select the assertion count (in terms of t ) of the low side output pulses for the channel B duty cycle. The operation of the duty-cycle registers varies, depending on the pulse mode selected with the PWM_BCTL.PULSEMODELO bits.
Page 987 ADSP-SC58x PWM Register Descriptions Channel B-Low Heightened-Precision Duty-0 Register register provides a fine-grained edge placement within the system clock period. This register, in PWM_BL0_HP conjunction with the PWM_BL0 register, allows programs to specify fractional duty cycles. The PWM_BL0_HP reg- ister and the PWM_BL0 register work together in a Q15.8 signed two’s complement fixed-point format.
Page 988 ADSP-SC58x PWM Register Descriptions Channel B-Low Duty-1 Register registers determine the width for the low side output pulses. For more information, PWM_BL0 PWM_BL1 see the PWM_BL0 register description. DUTY (R/W) Duty Cycle De-Asserted Count Figure 19-50: PWM_BL1 Register Diagram Table 19-28: PWM_BL1 Register Fields Bit No.
Page 989 ADSP-SC58x PWM Register Descriptions Channel B-Low Heightened-Precision Duty-1 Register register provides a fine-grained edge placement within the system clock period. This register, in PWM_BL1_HP conjunction with the PWM_BL1 register, allows programs to specify fractional duty cycles. The PWM_BL1_HP reg- ister and the PWM_BL1 register work together in a Q15.8 signed two’s complement fixed-point format.
Page 990 ADSP-SC58x PWM Register Descriptions Channel B-Low Full Duty0 Register The full duty registers can be used instead of the combined duty and heightened-precision duty registers.The register contains the PWM_BL_DUTY0.DUTY bit field from the register and the PWM_BL_DUTY0 PWM_BL0 PWM_BL_DUTY0.ENHDIV bit field from the PWM_BL0_HP register.
Page 991 ADSP-SC58x PWM Register Descriptions Channel B-Low Full Duty1 Register The full duty registers can be used instead of the combined duty and heightened-precision duty registers.The register contains the PWM_BL_DUTY1.DUTY bit field from the register and the PWM_BL_DUTY1 PWM_BL1 PWM_BL_DUTY1.ENHDIV bit field from the PWM_BL1_HP register.
Page 992 ADSP-SC58x PWM Register Descriptions Channel C Control Register register selects the low and high side output pulse mode, enables low and high side output, and PWM_CCTL enables low/high side output crossover. PULSEMODELO (R/W) DISHI (R/W) Low Side Output Pulse Position Channel High Side Output Disable PULSEMODEHI (R/W) DISLO (R/W)
Page 993 ADSP-SC58x PWM Register Descriptions Table 19-32: PWM_CCTL Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) PULSEMODEHI High Side Output Pulse Position. (R/W) The PWM_CCTL.PULSEMODEHI bits select the pulse position for Channel C high side output. In symmetrical mode, the channel forms a symmetrical pulse waveform around the center of the PWM period.
Page 994 ADSP-SC58x PWM Register Descriptions Channel C-High Pulse Duty Register 0 registers determine the width for the high side output pulses. The values in these PWM_CH0 PWM_CH1 registers select the assertion count (in terms of t ) of the high side output pulses for the channel C duty cycle. The operation of the duty-cycle registers varies, depending on the pulse mode selected with the PWM_CCTL.PULSEMODEHI bits.
Page 995 ADSP-SC58x PWM Register Descriptions Channel C-High Pulse Heightened-Precision Duty Register 0 register provides a fine-grained edge placement within the system clock period. This register, in PWM_CH0_HP conjunction with the PWM_CH0 register, allows programs to specify fractional duty cycles. The PWM_CH0_HP reg- ister and the PWM_CH0...
Page 996 ADSP-SC58x PWM Register Descriptions Channel C-High Pulse Duty Register 1 registers determine the width for the high side output pulses. For more information, PWM_CH0 PWM_CH1 see the PWM_CH0 register description. DUTY (R/W) Duty Cycle De-Asserted Count Figure 19-57: PWM_CH1 Register Diagram Table 19-35: PWM_CH1 Register Fields Bit No.
Page 997 ADSP-SC58x PWM Register Descriptions Channel C-High Pulse Heightened-Precision Duty Register 1 register provides a fine-grained edge placement within the system clock period. This register, in PWM_CH1_HP conjunction with the PWM_CH1 register, allows programs to specify fractional duty cycles. The PWM_CH1_HP reg- ister and the PWM_CH1...
Page 998 ADSP-SC58x PWM Register Descriptions Channel Configuration Register register configures Channel A, B, C, and D reference timer selection, high and low side out- PWM_CHANCFG put features, and enables high frequency chopping operation. Do not change the value of any bits in the PWM register while the PWM is enabled (PWM_CTL.GLOBEN =1).
Page 999 ADSP-SC58x PWM Register Descriptions Table 19-37: PWM_CHANCFG Register Fields Bit No. Bit Name Description/Enumeration (Access) ENCHOPDL Channel D Gate Chopping Enable Low Side. (R/W) The PWM_CHANCFG.ENCHOPDL bit enables mixing of the Channel D low side out- put signals with a high-frequency chopping signal, which is configured with the PWM_CHOPCFG register.
Page 1000 ADSP-SC58x PWM Register Descriptions Table 19-37: PWM_CHANCFG Register Fields (Continued) Bit No. Bit Name Description/Enumeration (Access) MODELSD Channel D Mode of low Side Output. (R/W) The PWM_CHANCFG.MODELSD bit selects whether the low side output waveform is based on independent controls or whether the low side output depends on the high side output controls.

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