Analog Devices ADSP-SC58 Series Hardware Reference Manual page 434

ADSP-SC58x DMC Register Descriptions
Table 10-13: DMC_CTL Register Fields (Continued)
Bit No.
(Access)
13 DLLCAL
(R0/W)
12 PPREF
(R/W)
11:9 RDTOWR
(R/W)
10–28
Bit Name
DLL Calibration Start.
The DMC_CTL.DLLCAL bit starts the PHY DLL calibration sequence. Note that this
bit always reads as 0.
Postpone Refresh.
The DMC_CTL.PPREF bit enables postponing the DMCs sending of auto-refresh
commands.
When enabled, the DMC accumulates refresh commands. The
DMC_EFFCTL.NUMREF field selects the number of refresh commands that the
DMC can accumulate.
When disabled, the DMC_TR1.TREF field selects the interval for auto-refresh com-
mand distribution. A maximum of eight auto-refresh commands can be accumulated
in DDR2 and DDR3 mode and a maximum of four auto-refresh commands in low
power DDR mode.
Read-to-Write Cycle.
The DMC_CTL.RDTOWR bits select the number of cycles that the DMC adds when a
write operation follows a read operation. For proper operation, it should be program-
med with the value of 010.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 No effect
1 Start PHY DLL calibration
0 Disable Postpone Refresh
1 Enable Postpone Refresh
0 1 Cycle Added from JEDEC Spec Value
1 2 Cycles Added from JEDEC Spec Value
2 3 Cycles Added from JEDEC Spec Value
3 4 Cycles Added from JEDEC Spec Value
4 5 Cycles Added from JEDEC Spec Value
5 6 Cycles Added from JEDEC Spec Value
6 7 Cycles Added from JEDEC Spec Value
7 8 Cycles Added from JEDEC Spec Value