Analog Devices ADSP-SC58 Series Hardware Reference Manual page 932

• The outputs of Channel A are referenced to PWMTMR1. The outputs of channel B are referenced to
PWMTMR2.
Figure 19-4: Phase Offset Control Using DELAY
The delay registers are double buffered and the new value of DELAY reloads at the period boundary of
PWMTMR0. The two options exist when the new value is different from the older one. The behavior of
PWMTMRy in both these cases is discussed. The Impact of New DELAY Value on Timer Count for Equal Timer
Periods figure shows the behavior in the two cases. It is assumed that channel B references its outputs to
PWMTMR0 and channel A references its outputs to PWMTMR1.
1. The new delay value is higher than the previous value. Here the corresponding PWMTMRy allows more than
one time period between consecutive triggers from the channel delay
this case, after reaching its period boundary, PWMTMRy holds its count at the period boundary and waits for
the trigger from the channel delay register. The Impact of New DELAY Value on Timer Count for Equal Timer
Periods figure shows case A functionality.
2. The next delay value programmed is smaller than the previous value. Here, the corresponding PWMTMRy
allows only less than one time period between consecutive triggers from the channel delay register. Though the
trigger comes earlier in this case, before PWMTMRy has counted out one full period, it reloads and starts its
period again. The Impact of New DELAY Value on Timer Count for Equal Timer Periods figure shows case B
functionality.
Therefore, PWMTMR1 waits and obeys a synchronization pulse from the
periods.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
PWMTMR0
DELAY1
DELAY1
PWMTMR1
AH
DELAY2
DELAY2
PWMTMR2
BH
DELAY1 DELAY1
DELAY2 DELAY2
(PWM_DLYA
PWM_DLYA
Timer Units
- PWM_DLYD) registers. In
register in every one of its
19–11