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ADSP-SC58x SMC Register Descriptions
Bank 2 Extended Timing Register
The
register configures extensions to access times and idle times, augmenting the setup, hold, and
SMC_B2ETIM
access times configured with the
PGWS (R/W)
Page Wait States
Figure 11-20: SMC_B2ETIM Register Diagram
Table 11-10: SMC_B2ETIM Register Fields
Bit No.
(Access)
19:16
PGWS
(R/W)
14:12
IT
(R/W)
11–36
SMC_B2TIM
15
14
13
12
11
0
0
0
0
0
IT (R/W)
Idle Time
TT (R/W)
Transition Time
31
30
29
28
27
0
0
0
0
0
Bit Name
Page Wait States.
The SMC_B2ETIM.PGWS bits select a page access extension time (in SCLK0_0 cy-
cles) that the SMC waits during read accesses when configured for flash page protocol
(SMC_B2CTL.MODE =2). The wait time is from 2 to 15 SCLK0_0 cycles.
Idle Time.
The SMC_B2ETIM.IT bits select a bus idle time (in SCLK0_0 cycles) that the SMC
waits between de-asserting the SMC_AMS[n] pin and asserting the SMC_AMS[n]
pin for the next access. Note that the SMC_B2ETIM.IT period may be extended us-
ing the SMC_B2ETIM.TT selection. The idle time is from 0 to 7 SCLK0_0 cycles.
register.
10
9
8
7
6
5
4
3
0
1
0
0
0
0
0
0
26
25
24
23
22
21
20
19
0
0
0
0
0
0
0
0
Description/Enumeration
0 Not supported
1 Not supported
2-15 2-15 SCLK0_0 clock cycles
0 0 SCLK0_0 clock cycles
7 7 SCLK0_0 clock cycles
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
2
1
0
0
0
0
PREST (R/W)
Pre Setup Time
PREAT (R/W)
Pre Access Time
18
17
16
0
1
0
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