Page 1: Hardware Reference
® ADSP-BF535 Blackfin Processor Hardware Reference Revision 3.3, February 2013 Part Number 82-000410-13 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106...
Page 2 Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use;...
Page 3: Table Of Contents
Manual Contents ................. xliv What’s New in This Manual ............. xlviii Technical Support ..............xlviii Supported Processors ..............xlix Product Information ................ l Analog Devices Web Site ............l EngineerZone ................li Notation Conventions ..............lii Register Diagram Conventions ............liii INTRODUCTION ADSP-BF535 Peripherals ..............
Page 4 Full On Operating Mode (Maximum Performance) ....1-22 Active Operating Mode (Low Power Savings) ......1-22 Sleep Operating Mode (High Power Savings) ......1-23 Deep Sleep Operating Mode (Maximum Power Savings) ..1-23 Clock Signals ................1-23 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 5 Data Formats ................ 2-11 Endianess ................2-12 ALU Data Types ..............2-12 Multiplier Data Types ............2-13 Shifter Data Types ..............2-14 Arithmetic Formats Summary ..........2-15 Using Multiplier Integer and Fractional Formats ....2-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 6 ALU Division Support Features ..........2-31 Special SIMD Video ALU Operations ........2-32 Multiply Accumulators (Multipliers) ........... 2-32 Multiplier Operation ............. 2-33 Placing Multiplier Results in Multiplier Accumulator Registers ................ 2-34 Rounding or Saturating Multiplier Results ......2-34 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 7 Bit Test, Set, Clear, Toggle ..........2-48 Field Extract and Field Deposit ......... 2-48 Shifter Instruction Summary ..........2-48 OPERATING MODES AND STATES User Mode ..................3-3 Protected Resources and Instructions ........3-4 Protected Memory ..............3-5 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 8 Booting Methods ................ 3-17 PROGRAM SEQUENCER Sequencer Related Registers ............4-3 Sequencer Status Register (SEQSTAT) ........4-4 Zero-Overhead Loop Registers (LC, LT, LB) ......4-5 System Configuration Register (SYSCFG) ....... 4-6 Instruction Pipeline ..............4-7 viii ADSP-BF535 Blackfin Processor Hardware Reference...
Page 9 System Interrupt Assignment Registers (SIC_IARx) ....4-29 Event Controller Registers ............4-31 Core Interrupt Mask Register (IMASK) ......... 4-32 Core Interrupt Latch Register (ILAT) ........4-32 Core Interrupts Pending Register (IPEND) ......4-33 Global Enabling/Disabling of Interrupts ........4-34 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 10 Example Code for an Exception Handler ......4-55 Example Code for an Exception Routine ......4-57 Executing RTX, RTN, or RTE in a Lower Priority Event ... 4-57 Recommendation for Allocating the System Stack ..... 4-58 Latency in Servicing Events ........... 4-58 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 11 Overview of L1 Instruction SRAM ........6-10 Overview of L1 Data SRAM ..........6-10 Overview of Scratchpad Data SRAM ......... 6-11 Overview of On-Chip L2 Memory ........6-11 Level 1 Memory ..............6-12 Data Memory Control Register (DMEM_CONTROL) ..6-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 12 Example Code for Direct Invalidation ........6-30 L1 Data Memory ..............6-37 L1 Data SRAM ..............6-38 L1 Data Cache ..............6-40 Example of Mapping Cacheable Address Space into Data Banks ................ 6-41 Data Cache Access ............6-45 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 13 DCPLB Data Registers (DCPLB_DATAx) ......6-65 ICPLB Data Registers (ICPLB_DATAx) ........ 6-67 DCPLB Address Registers (DCPLB_ADDRx) ......6-69 ICPLB Address Registers (ICPLB_ADDRx) ......6-71 DCPLB and ICPLB Status Registers (DCPLB_STATUS, ICPLB_STATUS) ............... 6-72 DCPLB Status Register (DCPLB_STATUS) ......6-73 ADSP-BF535 Blackfin Processor Hardware Reference xiii...
Page 14 Core MMR Programming Code Example ......6-85 CHIP BUS HIERARCHY Internal Interfaces ................. 7-1 ADSP-BF535 Internal Clocks ............7-2 Core Overview ................7-3 System Overview ................7-5 System Bus Interface Unit (SBIU) ........... 7-5 On-Chip L2 SRAM Memory Interface ........7-7 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 15 Resources Accessible From EMB ........7-19 DYNAMIC POWER MANAGEMENT Clocking ..................8-1 Phase Locked Loop and Clock Control ........8-2 PLL Overview ..............8-2 PLL Clock Multiplier Ratios ............ 8-3 Core Clock/System Clock Ratio Control ......8-5 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 16 Peripheral Clock Enable Register (PLL_IOCK) ....8-22 Dynamic Supply Voltage Control .......... 8-23 PCI Power Savings ............8-24 Changing Voltage ............. 8-24 External Voltage Regulator Example ........8-25 Power Saving Sequence ..........8-25 High Performance Sequence .......... 8-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 17 Memory DMA (MemDMA) ............9-31 MemDMA Control Registers ............9-32 Destination Memory DMA Configuration Register (MDD_DCFG) ..............9-33 Destination Memory DMA Transfer Count Register (MDD_DCT) ..............9-34 Destination Memory DMA Start Address Registers (MDD_DSAH, MDD_DSAL) ........... 9-35 ADSP-BF535 Blackfin Processor Hardware Reference xvii...
Page 18 (MDS_DCP) ..............9-43 Source Memory DMA Interrupt Register (MDS_DI) ..... 9-43 Performance/Throughput for MemDMA ....... 9-44 DMA Abort Conditions .............. 9-44 DMA Bus Error Conditions ............9-45 Data Misalignment ............... 9-46 Illegal Memory Access ............9-46 xviii ADSP-BF535 Blackfin Processor Hardware Reference...
Page 19 DMA Registers ..............10-19 SPIx DMA Current Descriptor Pointer Register (SPIx_CURR_PTR) ............10-20 SPIx DMA Configuration Register (SPIx_CONFIG) ..10-21 SPIx DMA Start Address High Register (SPIx_START_ADDR_HI) and SPIx DMA Start Address Low Register (SPIx_START_ADDR_LO) ..10-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 20 Reception Error (RBSY) ............10-37 Transmit Collision Error (TXCOL) ........10-37 Beginning and Ending an SPI Transfer ........10-38 SERIAL PORT CONTROLLERS SPORT Operation ..............11-7 SPORT Disable ................11-7 Setting SPORT Modes ..............11-8 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 21 SPORTx Receive DMA Start Address High (SPORTx_START_ADDR_HI_RX) Registers ....11-35 SPORTx Receive DMA Start Address Low (SPORTx_START_ADDR_LO_RX) Registers ....11-36 SPORTx Receive DMA Count (SPORTx_COUNT_RX) Registers ................11-37 SPORTx Receive DMA Next Descriptor Pointer (SPORTx_NEXT_DESCR_RX) Registers ......11-37 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 22 (SPORTx_IRQSTAT_TX) Registers ......... 11-49 Register Writes and Effect Latency ..........11-50 Clock and Frame Sync Frequencies ........... 11-50 Maximum Clock Rate Restrictions ........11-51 Data Word Formats ..............11-52 Word Length ..............11-52 Endian Format ..............11-52 xxii ADSP-BF535 Blackfin Processor Hardware Reference...
Page 23 Channel Selection Registers ..........11-66 Multichannel Enable ............11-67 Multichannel DMA Data Packing ........11-68 Moving Data Between SPORTS and Memory ......11-69 Support for Standard Protocols ..........11-69 2X Clock Recovery Control ..........11-70 ADSP-BF535 Blackfin Processor Hardware Reference xxiii...
Page 24 Non-DMA Mode ..............12-15 DMA Mode ................12-17 Mixing Modes ................12-17 UART DMA Receive Registers ..........12-18 UARTx Receive DMA Current Descriptor Pointer Registers (UARTx_CURR_PTR_RX) ..........12-19 UARTx Receive DMA Configuration Registers (UARTx_CONFIG_RX) ..........12-20 xxiv ADSP-BF535 Blackfin Processor Hardware Reference...
Page 25 UARTx Transmit DMA Start Address Low Registers (UARTx_START_ADDR_LO_TX) ........12-31 UARTx Transmit DMA Count Registers (UARTx_COUNT_TX) ........... 12-32 UARTx Transmit DMA Next Descriptor Pointer Registers (UARTx_NEXT_DESCR_TX) ......... 12-33 UARTx Transmit DMA Descriptor Ready Registers (UARTx_DESCR_RDY_TX) ........... 12-34 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 26 Supported Transactions to PCI ......... 13-8 Inbound Transactions (ADSP-BF535 Processor as PCI Target) ................13-10 General Inbound Operation ..........13-10 Inbound Error Detection and Reporting ......13-12 Supported Transactions From PCI ........13-12 Unsupported Transactions From PCI ......13-12 xxvi ADSP-BF535 Blackfin Processor Hardware Reference...
Page 27 PCI Inbound I/O Base Address Register (PCI_TIBAP) ..13-25 Configuration Space Control and Status Registers ...... 13-26 PCI Device Memory BAR Mask Register (PCI_DMBARM) ............. 13-26 PCI Device I/O BAR Mask Register (PCI_DIBARM) ..13-27 ADSP-BF535 Blackfin Processor Hardware Reference xxvii...
Page 28 (PCI_CFG_MAXL) ............13-41 PCI Configuration Minimum Grant Register (PCI_CFG_MING) ............13-42 PCI Configuration Interrupt Pin Register (PCI_CFG_IP) ... 13-42 PCI Configuration Interrupt Line Register (PCI_CFG_IL) .. 13-43 PCI Host Memory Control Register (PCI_HMCTL) ... 13-43 xxviii ADSP-BF535 Blackfin Processor Hardware Reference...
Page 29 Transaction Decode and Clock Synchronization Block ... 14-7 Registers and Control Block ........... 14-8 Memory Interface Block ............14-8 DMA Master Block ............... 14-9 PAB Interface Block ............14-10 Features and Modes ..............14-10 Endpoint Types ..............14-10 ADSP-BF535 Blackfin Processor Hardware Reference xxix...
Page 30 USBD Module Configuration and Control Register (USBD_CTRL) ............... 14-21 Global Interrupt Register (USBD_GINTR) ......14-22 Global Interrupt Mask Register (USBD_GMASK) ....14-24 DMA Master Channel Configuration Register (USBD_DMACFG) ............14-24 DMA Master Channel Base Address Low Register (USBD_DMABL) ............14-25 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 31 USBD_MSOF – Missed Start of Frame ......14-39 USBD_RST – Reset Signaling Detected ......14-39 USBD_SUSP – Device Suspended ........14-39 USBD_RESUME – Resume Signaling ......14-39 USBD_FRMAT – Frame Match ........14-40 USBD_EPxINT – Endpoint(x) Interrupt ......14-40 ADSP-BF535 Blackfin Processor Hardware Reference xxxi...
Page 32 USB Transfer Concepts ........... 14-47 How to Transfer Data ............. 14-48 Bulk Transfers ............. 14-49 Bulk In ............... 14-50 Bulk Out ..............14-51 Isochronous Transfers ..........14-53 Iso In ................. 14-54 Iso Out ..............14-55 xxxii ADSP-BF535 Blackfin Processor Hardware Reference...
Page 33 Flag Interrupt Mask Registers (FIO_MASKA_C, FIO_MASKA_S, FIO_MASKB_C, FIO_MASKB_S) ........15-5 Flag Polarity Register (FIO_POLAR) ........15-9 Flag Interrupt Sensitivity Register (FIO_EDGE) ....15-10 Flag Set on Both Edges Register (FIO_BOTH) ....15-10 Performance/Throughput ............15-11 ADSP-BF535 Blackfin Processor Hardware Reference xxxiii...
Page 34 Core Timer Count Register (TCOUNT) ......16-23 Core Timer Period Register (TPERIOD) ......16-24 Core Timer Scale Register (TSCALE) ........16-24 Watchdog Timer ............... 16-25 Watchdog Timer Operation ..........16-25 Watchdog Count Register (WDOG_CNT) ......16-26 xxxiv ADSP-BF535 Blackfin Processor Hardware Reference...
Page 35 EBIU Arbitration ................ 18-5 External Memory Interfaces ............18-5 EBIU Programming Model ............18-7 Error Detection ..............18-8 Asynchronous Memory Interface ..........18-9 Asynchronous Memory Address Decode ....... 18-10 Asynchronous Memory Global Control Register (EBIU_AMGCTL) ............18-10 ADSP-BF535 Blackfin Processor Hardware Reference xxxv...
Page 36 Setting the SDRAM Buffering Timing Option (EBUFE) ..............18-45 Selecting the CAS Latency Value (CL) ......18-46 SDQM Operation ............18-47 Executing a Parallel Refresh Command ......18-47 Selecting the Bank Activate Command Delay (TRAS) ..18-47 xxxvi ADSP-BF535 Blackfin Processor Hardware Reference...
Page 37 Bank Activate Command ..........18-77 Load Mode Register Command ........18-77 Read/Write Command ............ 18-78 Auto-Refresh Command ..........18-78 Self-Refresh Command ........... 18-79 No Operation/Command Inhibit Commands ....18-80 SDRAM Timing Specifications ..........18-80 SDRAM Performance ............18-81 ADSP-BF535 Blackfin Processor Hardware Reference xxxvii...
Page 38 Example Asynchronous Memory Interfaces ......19-9 Avoiding Bus Contention ........... 19-10 Supported SDRAM Configurations ........19-11 Example SDRAM Interfaces ..........19-12 High Frequency Design Considerations ........19-14 Point-to-Point Connections on Serial Ports ......19-14 Signal Integrity ..............19-15 xxxviii ADSP-BF535 Blackfin Processor Hardware Reference...
Page 39 Trace Unit ................20-14 Trace Buffer Control Register (TBUFCTL) ......20-16 Trace Buffer Status Register (TBUFSTAT) ......20-17 Trace Buffer Register (TBUF) ..........20-18 Code to Recreate the Execution Trace in Memory .... 20-18 ADSP-BF535 Blackfin Processor Hardware Reference xxxix...
Page 40 L1 Instruction Memory Controller Registers ......... A-4 Interrupt Controller Registers ............A-7 Core Timer Registers ..............A-9 DSP Device ID Register ............... A-9 Trace Unit Registers ..............A-10 Watchpoint and Patch Registers ..........A-10 Performance Monitor Registers ........... A-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 41 Memory DMA Controller Registers ..........B-26 Asynchronous Memory Controller—EBIU ......... B-28 PCI Bridge Registers ..............B-28 USB Device Registers ..............B-31 System DMA Control Registers ..........B-35 SDRAM Controller External Bus Interface Unit ......B-35 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 42 Boundary-Scan Register ............C-8 NUMERIC FORMATS Unsigned or Signed: Two’s-Complement Format ......D-1 Integer or Fractional ..............D-1 Binary Multiplication ..............D-4 Fractional Mode and Integer Mode ......... D-5 Block Floating-Point Format ............D-6 GLOSSARY INDEX xlii ADSP-BF535 Blackfin Processor Hardware Reference...
Page 43: Preface
Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices processors. The manual assumes the audience has a working knowledge of the appropriate processor architecture and instruc- tion set. Programmers who are unfamiliar with Analog Devices processors...
Page 44: Manual Contents
DAG and Pointer registers, memory address align- ment, and DAG instructions. • Chapter 6, Memory Describes L1 memories and L2 memories. In particular, details their memory architecture, memory model, memory transaction model, and memory-mapped registers (MMRs). The L1 section xliv ADSP-BF535 Blackfin Processor Hardware Reference...
Page 45 SPI0 and SPI1, that provide an I/O interface to a variety of SPI compatible peripheral devices. • Chapter 11, Serial Port Controllers Describes the two independent, synchronous Serial Port Control- lers (SPORT0 and SPORT1) that provide an I/O interface to a variety of serial peripheral devices. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 46 Blackfin processor core. • Chapter 17, Real-Time Clock (RTC) Describes a set of digital watch features of the ADSP-BF535 pro- cessor, including time of day, alarm, and stopwatch countdown. xlvi ADSP-BF535 Blackfin Processor Hardware Reference...
Page 47 Describes various aspects of the 16-bit data format. The chapter also describes how to implement a block floating-point format in software. • Appendix G, Glossary Contains definitions of terms used in this book, including acronyms. ADSP-BF535 Blackfin Processor Hardware Reference xlvii...
Page 48: What's New In This Manual
What’s New in This Manual What’s New in This Manual This is Revision 3.3 of ADSP-BF535 Blackfin Processor Hardware Refer- ence. This revision corrects minor typographical errors and the following issues: • instructions need not be first in nested interrupts and com-...
Page 49: Supported Processors
• E-mail your questions about processors and processor applications processor.support@analog.com (Greater China support) processor.china@analog.com • In the USA only, call 1-800-ANALOGD (1-800-262-5643) • Contact your Analog Devices sales office or authorized distributor. Locate one at: www.analog.com/adi-sales • Send questions by mail to: Processors and DSP Technical Support Analog Devices, Inc.
Page 50: Product Information
Product Information Product Information Product information can be obtained from the Analog Devices Web site and the CCES or VisualDSP++ online help. Analog Devices Web Site The Analog Devices Web site, , provides information www.analog.com about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors.
Page 51: Engineerzone
Preface EngineerZone EngineerZone is a technical support forum from Analog Devices, Inc. It allows you direct access to ADI technical support engineers. You can search FAQs and technical information to get quick answers to your embedded processing and DSP design questions.
Page 52: Notation Conventions
A Warning identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for devices users. In the online version of this book, the word Warning appears instead of this symbol. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 53: Register Diagram Conventions
• Shaded bits are reserved.  To ensure upward compatibility with future implementations, write back the value that is read for reserved bits in a register, unless otherwise specified. ADSP-BF535 Blackfin Processor Hardware Reference liii...
Page 54 0 - Sample TMRx pin or OUT_DIS (Output Pad Disable) PF1 pin. 0 - Enable pad in PWM_OUT mode. 1 - Sample UART RX pin 1 - Disable pad in PWM_OUT mode. or PPI_CLK pin. Figure 1. Register Diagram Example ADSP-BF535 Blackfin Processor Hardware Reference...
Page 55: Introduction
Memory Access (DMA) controller, and the interfaces between these, the system, and the optional, external (off chip) resources. ADSP-BF535 Peripherals The ADSP-BF535 processor system peripherals include: • Universal Asynchronous Receiver Transmitters (UARTs) • Serial Peripheral Interfaces (SPIs) ADSP-BF535 Blackfin Processor Hardware Reference...
Page 56: Adsp-Bf535 Core Architecture
1-2. The computational units process 8-, 16-, or 32-bit data from the register file. Each MAC performs a 16- by 16-bit multiply per cycle, with accumulation to a 40-bit result. This pro- vides eight bits of extended precision. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 57 The 40-bit shifter can deposit data and perform shifting, rotating, normal- ization, and extraction operations. Data for the computational units is located in a multiported register file of sixteen 16-bit entries or eight 32-bit entries. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 58 The DAGs share a register file con- taining four sets of 32-bit Index, Modify, Length, and Base registers. Eight additional 32-bit registers provide pointers for general indexing of variables and stack locations. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 59: Memory Architecture
C/C++ compiler. Memory Architecture The Blackfin architecture structures memory as a single, unified 4 Gbyte address space using 32-bit addresses. All resources, including internal memory, external memory, PCI address spaces, and I/O control registers ADSP-BF535 Blackfin Processor Hardware Reference...
Page 60 Figure 1-3. ADSP-BF535 Processor Internal/External Memory Map The L1 memory system is the primary highest performance memory avail- able to the Blackfin core. The L2 memory system provides additional capacity with slightly lower performance. The off-chip memory system, ADSP-BF535 Blackfin Processor Hardware Reference...
Page 61: Internal (On-Chip) Memory
SRAM at the full bandwidth of the core and slightly longer latency than the L1 memory banks. The L2 memory is a unified instruc- tion and data memory and can hold any mixture of code and data required by the system design. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 62: External (Off-Chip) Memory
64 Mbytes of memory. The PCI bus defines three separate address spaces, which are accessed through windows in the ADSP-BF535 processor memory space: • PCI memory • PCI I/O • PCI configuration space ADSP-BF535 Blackfin Processor Hardware Reference...
Page 63 PCI configuration space. This window is fixed and receives the address of the value, and the value if the operation is a write. Otherwise the device returns the value into the same address on a read operation. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 64: I/O Memory Space
• Emulation • Causes the processor to enter Emulation mode, allowing command and control of the processor via the JTAG interface. • Reset • Resets the processor. • Nonmaskable Interrupt (NMI) 1-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 65: Dma Support
ADSP-BF535 internal memories and any of its DMA capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA capable peripherals and external devices connected to the external memory interfaces. These include the SDRAM controller, asynchronous ADSP-BF535 Blackfin Processor Hardware Reference 1-11...
Page 66: External Bus Interface Unit
The SDRAM controller provides an interface to up to four separate banks of industry-standard SDRAM devices or DIMMs. Fully compliant with the PC133 SDRAM standard, each bank can be configured to contain between 16 and 128 Mbytes of memory. 1-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 67: Asynchronous Controller
Peripheral Component Interconnect (PCI) interface. The PCI provides a bus bridge function between the processor core and on-chip peripherals and an external PCI bus. The PCI interface of the ADSP-BF535 processor supports two PCI functions: ADSP-BF535 Blackfin Processor Hardware Reference 1-13...
Page 68: Pci Host Function
The ADSP-BF535 external memory space, internal L2, and some I/O MMRs can be selectively enabled as target memory spaces. Devices on the PCI bus can use these as PCI memory transaction targets. 1-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 69: Pci Target Function
The RTC provides several programmable interrupt options, including interrupt per second, minute, or day clock ticks, or interrupt on programmable stopwatch countdown. ADSP-BF535 Blackfin Processor Hardware Reference 1-15...
Page 70: Watchdog Timer
ADSP-BF535 peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the timer control register, which is set only upon a watchdog generated reset. 1-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 71: Timers
16-bit period register and the count resumed. Serial Ports (SPORTs) The ADSP-BF535 processor incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor com- munications. The SPORTs support these features: ADSP-BF535 Blackfin Processor Hardware Reference 1-17...
Page 72 • Companding in hardware • Each SPORT can perform A-law or µ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit and/or receive channel of the SPORT without additional latencies. 1-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 73: Serial Peripheral Interface (Spi) Ports
Each SPI port baud rate and clock phase/polarities are programmable, and each has an integrated DMA controller, configurable to support either transmit or receive data streams. ADSP-BF535 Blackfin Processor Hardware Reference 1-19...
Page 74: Uart Ports
Each UART has two dedicated DMA channels, one for transmit and one for receive. These DMA channels have lower priority than most DMA channels because of their relatively low service rates. 1-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 75: Programmable Flags
Serial Port Interface (SPI) as a chip select and by the phase locked loop (PLL) circuitry to determine the multiplica- tion factor applied. For more information, see “Serial Port Controllers” on page 11-1 “Dynamic Power Management” on page 8-1. ADSP-BF535 Blackfin Processor Hardware Reference 1-21...
Page 76: Low Power Operation
The system clock however, continues to operate in this mode. Any interrupt, typically via some external event or Real-Time clock (RTC) activity, will wake up the processor. In this mode, the core proces- 1-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 77: Deep Sleep Operating Mode (Maximum Power Savings)
All on-chip peripherals operate at the rate set by the system clock. The sys- tem clock frequency is programmable by the PLL Control register. The programmable values define a divide ratio between the core clock (CCLK) and the system clock (SCLK). ADSP-BF535 Blackfin Processor Hardware Reference 1-23...
Page 78: Boot Modes
Development Tools The processor is supported by a complete set of software and hardware development tools, including Analog Devices’ emulators and the Cross- Core Embedded Studio or VisualDSP++ development environment. (The emulator hardware that supports other Analog Devices processors also emulates the processor.)
Page 79 (boards and extenders). In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the Blackfin processors. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.
Page 80 Development Tools 1-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 81: Computational Units
An examination of each computational unit provides details about its operation and is followed by a summary of computational instructions. Tracing inputs to the computational units and considering details about ADSP-BF535 Blackfin Processor Hardware Reference...
Page 82 File and computational units: multipliers, ALUs, and shifter. ADDRE SS ARITHME TIC UNIT DAG0 DAG 1 SEQ UE NCER ALIGN DECODE LOOP BUFFER CO NTROL UNIT BARREL S HI FTE R DATA ARITHM ETI C UNIT Figure 2-1. ADSP-BF535 Core Architecture ADSP-BF535 Blackfin Processor Hardware Reference...
Page 83: Using Data Formats
Examples of computations using this for- mat are the logical operations: NOT, AND, OR, XOR. These ALU operations treat their operands as binary strings with no provision for sign bit or binary point placement. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 84: Unsigned
1.15 NUMBER (HEXADECIMAL) DECIMAL EQUIVALENT 0X0001 0.000031 0X7FFF 0.999969 0XFFFF –0.000031 0X8000 –1.000000 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 –12 –13 –14 –15 –11 Figure 2-2. Bit Weighting for 1.15 Numbers ADSP-BF535 Blackfin Processor Hardware Reference...
Page 85: Register Files
Figure 2-3. Data Registers Data Address Generator Registers (DAGs) R0.H R0.L R1.H R1.L R2.H R2.L R3.H R3.L R4.H R4.L R5.H R5.L R6.H R6.L R7.H R7.L A0.X A0.W A1.X A1.W Figure 2-3. ADSP-BF535 Processor Register Files ADSP-BF535 Blackfin Processor Hardware Reference...
Page 86: Data Register File
Pointer Register File The general-purpose address Pointer registers, also called the P-registers, are organized as: • A 6-entry, P-register file P[5:0] • A Frame Pointer ( ) used to point to the current procedure’s acti- vation record ADSP-BF535 Blackfin Processor Hardware Reference...
Page 87: Dag Register Set
B register pair is associated with the corresponding I register. For example, are always associated with . However, any M register may be associated with any I register. For example, may be modified by . For more information, see “Data Address Generators” on page 5-1. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 88: Register File Instruction Summary
• Dreg_hi denotes the upper 16 bits of any Data Register File register. • An.L denotes the lower 16 bits of Accumulator • An.H denotes the upper 16 bits of Accumulator • Dreg_byte denotes the low order 8 bits of each Data register. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 89 – Dreg = Dreg_lo (Z) ; – – – **/– Dreg = Dreg_lo (X) ; – – – **/– An.X = Dreg_lo ; – – – – Dreg_lo = An.X ; – – – – ADSP-BF535 Blackfin Processor Hardware Reference...
Page 90: Data Types
Some instructions manipulate data in the registers by sign extending or zero extending the data to 32 bits: • Instructions zero-extend unsigned data • Instructions sign-extend signed 16-bit half words and 8-bit bytes 2-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 91: Data Formats
0000 0000 0000 0000 0000 0000 dddd Byte dddd 8.0 Signed sddd dddd ssss ssss ssss ssss ssss ssss sddd dddd Byte 0.16 Unsigned .dddd dddd dddd dddd 0000 0000 0000 0000 .dddd dddd dddd Fraction dddd ADSP-BF535 Blackfin Processor Hardware Reference 2-11...
Page 92: Endianess
ASTAT depending on the transfer of the result from both accumulators to the reg- ister file. Furthermore, the sticky bit is set with the bit and remains set until cleared. 2-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 93: Multiplier Data Types
(2 sign bits and 30 fractional bits) number. In the fractional mode, the multiplier automatically shifts the multiplier product left one bit before transferring the result to the multiplier result register ( ). This shift of ADSP-BF535 Blackfin Processor Hardware Reference 2-13...
Page 94: Shifter Data Types
The exponent logic assumes two’s-complement numbers. The exponent logic supports block floating point, which is also based on two’s-comple- ment fractions. Shifter results generate status information. For more information about using shifter status, see “Shifter Instruction Summary” on page 2-48. 2-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 95: Arithmetic Formats Summary
Operand Formats Result Formats Multiplication 16.0 explicitly signed or 32.0 not shifted unsigned Multiplication / addition 16.0 explicitly signed or 32.0 not shifted unsigned Multiplication / subtraction 16.0 explicitly signed or 32.0 not shifted unsigned ADSP-BF535 Blackfin Processor Hardware Reference 2-15...
Page 96: Using Multiplier Integer And Fractional Formats
With either fractional or integer operations, the multiplier output product is fed into a 40-bit adder/subtracter which adds or subtracts the new prod- uct with the current contents of the register to produce the final 40-bit result. 2-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 97 3 1 30 2 9 28 2 7 26 2 5 24 2 3 22 2 1 20 1 9 18 1 7 16 1 5 14 1 3 12 1 1 10 9 A0.W A0.X Figure 2-5. Integer Multiplier Results Format ADSP-BF535 Blackfin Processor Hardware Reference 2-17...
Page 98: Rounding Multiplier Results
When rounding is selected, A0.H/A1.H contain the rounded 16-bit result; the rounding effect in A0.H/A1.H affects as well. The registers repre- A0.X/A1.X A0.X/A0.H A1.X/A1.H sent the rounded 24-bit result, including sign extension and overflow. 2-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 99 Figure 2-6. Typical Unbiased Multiplier Rounding The compensation to avoid net bias becomes visible when all lower 15 bits are zero and bit 15 is one (the midpoint value) as shown in Figure 2-7. ADSP-BF535 Blackfin Processor Hardware Reference 2-19...
Page 100: Biased Rounding
When operating in biased rounding mode, all rounding operations with set to 0x8000 round up, rather A0.L/A1.L than only rounding odd values up. For an example of biased rounding, see Figure 2-8. 2-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 101: Truncation
The ALU provides the ability to round the arithmetic results directly into a data register with biased or unbiased rounding as described above. It also provides the ability to round on different bit boundaries. The options ADSP-BF535 Blackfin Processor Hardware Reference 2-21...
Page 102: Using Computational Status
This method permits monitoring each instruction’s outcome. register is a 32-bit register, with some bits reserved. To ensure ASTAT compatibility with future implementations, writes to this register should write back the values read from these reserved bits. 2-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 103: Arithmetic Status Register (Astat)
0 - Last result written to A0 1 - Last result written to A1 has not overflowed has overflowed 1 - Last result written to A0 has overflowed Figure 2-9. Arithmetic Status Register ADSP-BF535 Blackfin Processor Hardware Reference 2-23...
Page 104: Arithmetic Logic Unit (Alu)
Combination of 32-bit result from the multiplier with a 40-bit accumulation result Combining operations in both ALUs can result in four 16-bit results, two 32-bit results, or two 40-bit results generated in a single instruction. 2-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 105: Single 16-Bit Operations
In quad 16-bit operations, any two 32-bit registers may be used as the inputs to ALU0 and ALU1, considered as pairs of 16-bit operands. A small number of addition or subtraction operations produces four 16-bit ADSP-BF535 Blackfin Processor Hardware Reference 2-25...
Page 106 Explicitly, the four equivalent instructions are: R3.H = R0.H + R1.H (S) ; R3.L = R0.L + R1.L (S) ; R2.H = R0.H - R1.H (S) ; R2.L = R0.L - R1.L (S) ; 2-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 107: Single 32-Bit Operations
Because only two 32-bit data paths go from the Register File to the arithmetic units, the same two 32-bit input registers are presented to ALU0 and ALU1. For example: R3 = R1 + R2, R4 = R1 – R2 (NS) ; ADSP-BF535 Blackfin Processor Hardware Reference 2-27...
Page 108: Alu Instruction Summary
32-bit input ports that can be considered a pair of 16-bit operands or a single 32-bit operand. For single 16-bit operations, any of the four possible 16-bit operands may be used with any of the other 16-bit oper- ands presented at the input to the ALU. 2-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 109 Figure 2-11, for dual 16-bit operations, the high halves and low halves are paired, providing four possible combinations of addition and subtraction: (A) H+H, L+L (B) H+H, L-L (C) H-H, L+L (D) H-H, L-L ADSP-BF535 Blackfin Processor Hardware Reference 2-29...
Page 110: Dual 16-Bit Cross Options
(see Figure 2-12). This is particularly useful when dealing with complex math and portions of the Fast Fourier Transform (FFT). 2-30 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 111: Alu Status Signals
Arithmetic on 32-bit operands directly support multiprecision operations in the ALU. ALU Division Support Features The ALU supports division with two special divide primitives. These instructions ( ) let programs implement a non-restoring, condi- DIVS DIVQ tional (error checking), add-subtract-division algorithm. ADSP-BF535 Blackfin Processor Hardware Reference 2-31...
Page 112: Special Simd Video Alu Operations
Multiplier fixed-point instructions operate on 16-bit fixed-point data and produce 32-bit results that may be added or subtracted from a 40-bit accumulator. 2-32 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 113: Multiplier Operation
• for Fractional Unsigned • for Integer Signed • for Mixed signed and unsigned operands Also available is the option, which specifies 32-bit saturation of the accumulation result. ADSP-BF535 Blackfin Processor Hardware Reference 2-33...
Page 114: Placing Multiplier Results In Multiplier Accumulator Registers
2-18. • If an overflow or underflow has occurred, the saturate operation sets the specified result register to the maximum positive or nega- tive value. For more information, see the following section. 2-34 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 115: Saturating Multiplier Results On Overflow
Input data operands are signed integer. No shift (IS) correction is made. Input data operands are unsigned fraction. No shift (FU) correction is made. Input data operands are unsigned integer. No shift (IU) correction is made. ADSP-BF535 Blackfin Processor Hardware Reference 2-35...
Page 116 Accumulator contents (multiply x2 by a one-place shift-left). If scaling produces a signed value larger than 32 bits, the number is saturated to its maximum positive or negative value. 2-36 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 117 Operand one is signed; operand two is unsigned. MAC0 performs an unmixed multiply on signed fractions by default or another format, as specified. The (M) option can be used alone or in conjunction with one other format option. ADSP-BF535 Blackfin Processor Hardware Reference 2-37...
Page 118: Multiplier Data Flow Details
Each multiplier has two 16-bit inputs, performs a 16-bit multiplication, and stores the result in a 40-bit accumulator or extracts to a 16-bit or 32-bit register. Two 32-bit words are available at the MAC inputs, provid- ing four 16-bit operands to chose from. 2-38 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 119 MAC0 in the accumulator register. A1 += R3.H * R4.H (S) ; multiplier/accumulator performs a multiply and accumulates MAC1 the result with the previous results in the accumulator. ADSP-BF535 Blackfin Processor Hardware Reference 2-39...
Page 120: Multiply Without Accumulate
16 bits or 32 bits. If a 16-bit destination register is a low half, then MAC0 is used; if it is a high half, then MAC1 is used. For a 32-bit desti- nation register, either MAC0 or MAC1 is used. 2-40 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 121 The instruction deposits the upper 16 bits of the multiply answer with rounding and saturation into the lower half of , using MAC0. This example uses unsigned integer operands: R0.H = R2.H * R3.H (IU) ; ADSP-BF535 Blackfin Processor Hardware Reference 2-41...
Page 122: Special 32-Bit Integer Mac Instruction
The ADSP-BF535 processor supports a multicycle 32-bit MAC instruc- tion, that is, Dreg *= Dreg The single instruction multiplies two 32-bit integer operands and provides a 32-bit integer result, destroying one of the input operands. 2-42 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 123: Dual Mac Operations
16-bit halves, as a pair of 32-bit registers, or as an independent 16-bit half register or 32-bit register. For example: R3.H = ( A1 += R1.H * R2.L ), R3.L = ( A0 += R1.L * R2.L ) ; ADSP-BF535 Blackfin Processor Hardware Reference 2-43...
Page 124: Barrel Shifter (Shifter)
Shifter Operations The shifter instructions ( ) can be used various >>> >> ASHIFT LSHIFT ways, depending on the underlying arithmetic requirements. ASHIFT represents the arithmetic shift. represent the logical >>> LSHIFT >> shift. 2-44 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 125: Two Operand Shifts
The following example shows the input value down-shifted. R0 = 0x0000 B6A3 ; R0 >>= 0x04 ; results in R0.H = 0x0000 ; R0.L = 0xB6A3 ; ADSP-BF535 Blackfin Processor Hardware Reference 2-45...
Page 126: Register Shifts
Three operand shifter instructions shift an input register and deposit the result in a destination register. Immediate Shifts Immediate shift instructions use the data value in the instruction itself to control the amount and direction of the shifting operation. 2-46 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 127: Register Shifts
) bit is set to 0. For more information about , see “Condition Code Flag” on page 4-12. R0 = 0xABCD EF12 ; R2.L = 0x0004 ; R1 = R0 ROT by R2.L ; ADSP-BF535 Blackfin Processor Hardware Reference 2-47...
Page 128: Bit Test, Set, Clear, Toggle
Shifter Instruction Summary For information about assembly language syntax and the effect of shifter instructions on the status flags, see Appendix A, “ADSP-BF535 Consider- ations”, in Blackfin Processor Programming Reference. 2-48 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 129: Operating Modes And States
User mode. The current processor mode may be identified by interrogating the IPEND memory-mapped register (MMR), as shown in Table 3-1.  MMRs cannot be read while the processor is in User mode. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 130 IPEND[15:1] 1’s.  0x00 None User In addition, the ADSP-BF535 processor supports two nonprocessing states: • Idle state • Reset state Figure 3-1 illustrates the processor modes and states and the transition conditions between them. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 131: User Mode
Any attempt to access restricted system registers causes an exception event. Table 3-2 lists the registers that may be accessed in User mode. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 132: Protected Resources And Instructions
Table 3-3. Protected Instructions Instruction Description Return from Interrupt Return from Exception Return from NMI Disable Interrupts Enable Interrupts RAISE Force Interrupt/Reset IDLE Idle Return from Emulation Causes an exception only if executed outside Emulation mode ADSP-BF535 Blackfin Processor Hardware Reference...
Page 133: Protected Memory
User mode from various processor event service routines. When these instructions are used in service routines, the value of the return address must be first stored in the appropriate event register. If the RETx ADSP-BF535 Blackfin Processor Hardware Reference...
Page 134: Supervisor Mode
This Register Interrupt Service Routine RETI Exception Service Routine RETX Nonmaskable Interrupt Service RETN Routine Emulation Service Routine RETE Supervisor Mode The processor services all interrupt, NMI, and exception events in Super- visor mode. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 135: Non-Os Environments
As a result, the proces- sor remains in Supervisor mode because remains set. At this IPEND[15] point, the processor is servicing the lowest priority interrupt. This ensures that higher priority interrupts can be processed. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 136: Example Code To Stay In Supervisor Mode Coming Out Of Reset
WAIT_HERE : /* Wait here till IVG15 interrupt is serviced */ JUMP WAIT_HERE ; START : /* IVG15 vectors here */ [--SP] = RETI ; /* Enables interrupts and saves return address to stack */ ADSP-BF535 Blackfin Processor Hardware Reference...
Page 137: Emulation Mode
IDLE the processor into an Idle state. The processor remains in the Idle state until a peripheral or external device, such as a SPORT or the Real-Time Clock (RTC), generates an interrupt that requires servicing. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 138: Example Code For Transition To Idle State
/* drain the pipeline, IDLE asserts after SSYNC_ACK back from system */ STI R0 ; /* re-enable interrupts after wakeup */ Reset State Reset state initializes the processor logic. During Reset state, application programs and the operating system do not execute. 3-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 139 Cache validity bits Random (must be set to invalid prior to cache initialization) System Booting methods Determined by the values of BMODE pins at reset MSEL clock frequency Determined by sampling MSEL pins at reset ADSP-BF535 Blackfin Processor Hardware Reference 3-11...
Page 140: System Reset And Power-Up Configuration
DPMC. The DPMC resets only causes a System Software the Peripheral Clock Enable register reset. ) and the No Boot on Software PLL_IOCK Reset bit in . Does not reset the SYSCR core. 3-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 141: Hardware Reset
Universal Serial Bus (USB), have recognized and completed a reset. After the reset, the ADSP-BF535 processor transitions into the boot mode sequence con- figured by the BMODE state. ADSP-BF535 Blackfin Processor Hardware Reference 3-13...
Page 142: System Reset Configuration Register (Syscr)
A software reset may be initiated in three ways: • By the watchdog timer, if appropriately configured • By setting the System Software Reset field in the Software Reset register (see Figure 3-3) • By the instruction RAISE1 3-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 143 For a reset generated by the watchdog timer, the ADSP-BF535 processor transitions into the boot mode sequence. The boot mode is configured by the state of the and the No Boot on Software Reset control bits. BMODE ADSP-BF535 Blackfin Processor Hardware Reference 3-15...
Page 144: Software Reset Register (Swrst)
Reset bit in is set, the ADSP-BF535 processor starts executing from SYSCR the start of on-chip L2 memory. In this configuration, the core begins fetching instructions from address 0xF000 0000 (the beginning of on-chip L2 memory). 3-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 145: Core Only Software Reset
L2 memory (0xF000 0000). The boot kernel terminates the boot process with a jump to the start of the L2 memory space. The processor then begins execution from this address. ADSP-BF535 Blackfin Processor Hardware Reference 3-17...
Page 146 The boot kernel assumes that the SPI baud rate is 500 kHz. Both 8-bit and 16-bit addressable SPI serial PROMs are supported. A second stage loader is available to include the SPI baud rate up to 2 MHz. 3-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 147: Program Sequencer
• Interrupts and Exceptions. A runtime event or instruction triggers the execution of a subroutine. • Idle. An instruction causes the processor to stop operating and hold its current state until an interrupt occurs. Then, the processor services the interrupt and continues normal execution. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 148 ). The pipeline contains the 32-bit addresses of the instructions currently being fetched, decoded, and executed. The cou- ples with the registers, which store return addresses. All addresses RETn generated by the Sequencer are 32-bit memory instruction addresses. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 149: Sequencer Related Registers
Sequencer related registers are directly readable and writable. Manually pushing or popping registers to or from the stack is done using the explicit instructions (for push) or (for pop). [--SP] = Rn Rn = [SP++] ADSP-BF535 Blackfin Processor Hardware Reference...
Page 150: Sequencer Status Register (Seqstat)
), shown in Figure 4-2, contains SEQSTAT information about the current state of the Sequencer as well as diagnostic information from the last event. is a read-only register and is SEQSTAT accessible only in Supervisor mode. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 151: Zero-Overhead Loop Registers (Lc, Lt, Lb)
After evaluation, processing branches to a new target address. Both sets of regis- ters include the Loop Counter ( ), Loop Top ( ), and Loop Bottom ) registers. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 152: System Configuration Register (Syscfg)
0 - Disable 64-bit, free-running event. If precise exception timing cycle counter is required, CSYNC must be 1 - Enable 64-bit, free-running used after setting this bit. cycle counter Figure 4-3. System Configuration Register ADSP-BF535 Blackfin Processor Hardware Reference...
Page 153: Instruction Pipeline
Execute 2 (EX2) Finish accesses of data memory and start execution of dual cycle instructions. Execute 3 (EX3) Execute single cycle instructions. Write Back (WB) Write states to Data and Pointer register files and process events. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 154 IF1 and IF2 stages or stall the Instruction Memory Unit. The Execution Unit contains two 16-bit multipliers, two 40-bit ALUs, two 40-bit accumulators, one 40-bit shifter, a video unit (which adds 8-bit ALU support), and an 8-entry 32-bit Data Register File. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 155: Branches And Sequencing
CALL RETS The return address is the next sequential address after the CALL instruction. This push makes the address available for the CALL instruction’s matching return instruction, allowing easy return from the subroutine. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 156 CALL address. Indirect branches are instructions that use a dynamic JUMP CALL address—an address that changes at runtime—that comes from a Data Address Generator. For more information, see “Data Address Generators” on page 5-1. 4-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 157: Direct Short And Long Jumps
Data Address Gen- erator. The effective address is stored in a P-register. For the CALL instruction, the register is loaded with the address of the instruction RETS following the instruction. CALL ADSP-BF535 Blackfin Processor Hardware Reference 4-11...
Page 158: Pc-Relative Indirect Branch And Call
, and the value in may be copied to a status flag. • may be set to the result of a Pointer register comparison. • may be set to the result of a Data register comparison. 4-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 159: Conditional Branches
For condition handling where the value of a register is set based on the condition code, a conditional move instruction can be used instead of a branch statement. A register move can be performed, depending on ADSP-BF535 Blackfin Processor Hardware Reference 4-13...
Page 160: Branch Prediction
For all unconditional branches, the branch target address computed in the AC stage of the pipeline is sent to the Instruction Fetch address bus at the beginning of the EX1 stage. All unconditional branches have a latency of 3 cycles. CCLK 4-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 161: Loops And Sequencing
The condition for terminating a loop is that the counter decreases to zero. This condition tests whether the loop has completed the number of itera- tions loaded from the Loop Count register ( LC[1] LC[0] ADSP-BF535 Blackfin Processor Hardware Reference 4-15...
Page 162 PC-relative addresses from the instruction plus an LSETUP offset. In each case, the offset value is added to the location of the LSETUP instruction. are unsigned 32-bit registers supporting 2 –1 iterations through the loop. 4-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 163: Events And Sequencing
Events and Sequencing The Event Controller of the processor manages five types of activities: • Emulation • Reset • Non-maskable interrupts (NMI) • Exceptions • Interrupts ADSP-BF535 Blackfin Processor Hardware Reference 4-17...
Page 164 ) to support the IVG7 IVG13 ADSP-BF535 processor system. Refer to Table 4-6. Note the System Interrupt to Core Event mappings shown are the default values at reset and can be changed by software. 4-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 165 SPORT1 RX/TX SPI0 IVG9 SPI1 UART0 RX/TX IVG10 UART1 RX/TX Timer0, Timer1, Timer2 IVG11 Programmable Flags Interrupt A/B IVG12 Memory DMA IVG13 Watchdog Timer Software Interrupt 1 IVG14 Software Interrupt 2 (lowest priority) IVG15 ADSP-BF535 Blackfin Processor Hardware Reference 4-19...
Page 166: System Interrupt Processing
8. When the event vector for Interrupt A has entered the core pipe- line, the appropriate bit is set, which clears the respective IPEND bit. Thus, tracks all pending interrupts, as well as those ILAT IPEND being presently serviced. 4-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 167 TO DYN AMI C POWER MA NAGEME NT CONTROLLER SYSTEM INTERRUPT CONTROLLER CORE EVENT CONTROLLER N ote: N am es in parentheses are m em ory -m apped regis ters . Figure 4-5. Interrupt Processing Block Diagram ADSP-BF535 Blackfin Processor Hardware Reference 4-21...
Page 168: System Peripheral Interrupts
USB interrupt IVG7 PCI interrupts IVG7 SPORT0 RX DMA interrupt IVG8 SPORT0 TX DMA interrupt IVG8 SPORT1 RX DMA interrupt IVG8 SPORT1 TX DMA interrupt IVG8 SPI0 DMA interrupt IVG9 SPI1 DMA interrupt IVG9 4-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 169 If the default assignments shown in Table 4-7 are acceptable, then inter- rupt initialization involves only initialization of the core EVT vector address entries and register, and unmasking the specific peripheral IMASK interrupts in that the system requires. SIC_IMASK ADSP-BF535 Blackfin Processor Hardware Reference 4-23...
Page 170 Note the wake-up function is independent of the interrupt mask function. If an interrupt source is enabled in but masked SIC_ISR off in , the core wakes up if it is idled, but it does not SIC_IMASK generate an interrupt. 4-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 171: System Interrupt Wakeup-Enable Register (Sic_Iwr)
(usually by writing a system MMR) to the time that the SIC senses that the interrupt has been deasserted. ADSP-BF535 Blackfin Processor Hardware Reference 4-25...
Page 172 SIC_ISR register is not affected by the state of the Interrupt Mask reg- SIC_ISR ister and can be read at any time. Writes to have no effect on its SIC_ISR contents. 4-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 173 A reset forces the contents of to all 0s to mask off all peripheral SIC_IMASK interrupts. Writing a 1 to a bit location turns off the mask and enables the interrupt. ADSP-BF535 Blackfin Processor Hardware Reference 4-27...
Page 174: System Interrupt Mask Register (Sic_Imask)
• If the condition is unmasked and the core detects a double-fault condition, a hardware reset is generated. • If the condition is masked and the core detects a double-fault con- dition, core behavior may be unreliable. 4-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 175: System Interrupt Assignment Registers (Sic_Iarx)
SPORT0 TX Interrupt SPORT1 RX Interrupt IVG select IVG select 15 14 13 12 11 10 Real-Time Clock Interrupt PCI Interrupt IVG select IVG select USB Interrupt IVG select Figure 4-9. System Interrupt Assignment Register 0 ADSP-BF535 Blackfin Processor Hardware Reference 4-29...
Page 176 Reset interrupt service rou- tine before enabling interrupts. To prevent spurious or lost interrupt activity, these registers should be written to only when all peripheral inter- rupts are disabled. 4-30 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 177: Event Controller Registers
Supervisor mode. The registers may be both ILAT IMASK read and written in Supervisor mode, with the exception of ILAT[0] which is read-only. None of the three registers can be accessed in User mode. ADSP-BF535 Blackfin Processor Hardware Reference 4-31...
Page 178: Core Interrupt Mask Register (Imask)
ILAT corresponding bit is set. Otherwise, the write is ignored. This write IMASK functionality to is provided for cases where latched interrupt requests ILAT need to be cleared (cancelled) instead of servicing them. 4-32 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 179: Core Interrupts Pending Register (Ipend)
The IPEND least significant bit in that is currently set indicates the interrupt IPEND that is currently being serviced. At any given time, holds the current IPEND status of all nested events. ADSP-BF535 Blackfin Processor Hardware Reference 4-33...
Page 180: Global Enabling/Disabling Of Interrupts
Blackfin Processor Programming Reference. When program code is too time critical to be delayed by an interrupt, dis- able general-purpose interrupts, but be sure to re-enable them at the conclusion of the code sequence. 4-34 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 181: Event Vector Table
0xFFE0 2010 Reserved vector. EVT5 Hardware Error IVHW 0xFFE0 2014 EVT6 Core Timer IVTMR 0xFFE0 2018 EVT7 Interrupt 7 IVG7 0xFFE0 201C EVT8 Interrupt 8 IVG8 0xFFE0 2020 EVT9 Interrupt 9 IVG9 0xFFE0 2024 ADSP-BF535 Blackfin Processor Hardware Reference 4-35...
Page 182 This is a non-recoverable state. The SIC (via ) can be pro- SIC_IMASK grammed to send a reset request if a double-fault condition is detected. Subsequently, the reset request forces a system reset for core and peripherals. 4-36 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 183 In this mode, the internal boot ROM is not used. To support reads from this memory region, the external bus interface unit (EBIU) uses the default external memory configuration that results from hardware reset. ADSP-BF535 Blackfin Processor Hardware Reference 4-37...
Page 184: Nmi (Non-Maskable Interrupt)
• Violate the protection specification for the CPLB entry • Generate multiple hits on the respective CPLB • Receive a bus error response on an instruction fetch For more information about alignment and CPLBs, see “Memory” on page 6-1. 4-38 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 185 When the instruction should not be re-executed, the exception handler must advance the return address by the instruction length. • is placed in the Sequencer Status register ( EXCAUSE[5:0] SEQSTAT depending on the type of event. ADSP-BF535 Blackfin Processor Hardware Reference 4-39...
Page 186 In addition, this entry is used to signal a protec- tion violation caused by disallowed memory access, and it is defined by the Memory Management Unit (MMU) cacheability protection loo- kaside buffer (CPLB). 4-40 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 187 (Note that this exception can never be generated from PC-relative branches, only from indirect branches.) Instruction fetch 0x2B Illegal instruction fetch access (mem- CPLB protection vio- ory protection violation). lation ADSP-BF535 Blackfin Processor Hardware Reference 4-41...
Page 188 Table 4-12. Exceptions by Descending Priority Priority Exception EXCAUSE Unrecoverable Event 0x25 I-Fetch Multiple CPLB Hits 0x2D I-Fetch Misaligned Access 0x2A I-Fetch Protection Violation 0x2B I-Fetch CPLB Miss 0x2C I-Fetch Access Exception 0x29 Watchpoint Match 0x28 4-42 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 189: Exceptions While Executing An Exception Handler
• The generated exception is not taken. • The field in is updated with an unrecoverable EXCAUSE SEQSTAT event code. • The address of the offending instruction is saved in RETX ADSP-BF535 Blackfin Processor Hardware Reference 4-43...
Page 190: Hardware Error Interrupt
• Attempted access to uninitialized external memory space • Bus parity errors • Internal error conditions within the core, such as Performance Monitor overflow • The DMA Access Bus Comparator interrupt (attempted write to an active DMA register) 4-44 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 191 0b11000 0x18 Software issued a instruc- RAISE RAISE tion to invoke the hardware error interrupt ( IVHW Reserved All other bit combi- All other bit combi- nations. nations. ADSP-BF535 Blackfin Processor Hardware Reference 4-45...
Page 192: Core Timer
The minimum latency from the rising edge transition of the general-pur- pose interrupt to the output asserted is three core clock cycles. IPEND However, the latency can be much higher, depending on the core’s activ- ity level and state. 4-46 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 193 4. Before the first instruction starts execution, the corresponding interrupt bit in is cleared and the corresponding bit in ILAT IPEND is set. is also set to disable all interrupts until the return IPEND[4] address in is saved. RETI ADSP-BF535 Blackfin Processor Hardware Reference 4-47...
Page 194: Interrupts With And Without Nesting
Supervisor stack. Processor state is stored in the Supervisor stack, not in the User stack. Hence, the instructions to push ) and pop RETI [--SP]=RETI RETI ) use the Supervisor stack. RETI=[SP++] 4-48 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 195 IPEND[4] set. return address. instruction. Change processor Instruction A1 is Dashed lines mode. return address. indicate aborts (A1-A8), which are re-is sued at the completion of the interrupt. Figure 4-15. Non-Nested Interrupt Handling ADSP-BF535 Blackfin Processor Hardware Reference 4-49...
Page 196 Instruction I1 pushes return address. (A1-A8), which RETI on stack. Bit are r e-issued at IPEND[4] cleared. All the completion interrupts of priority of the interrupt. higher than 8 enabled. Figure 4-16. Nested Interrupt Handling 4-50 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 197: Example Prolog Code For Nested Interrupt Service Routine
/* Restore ASTAT, Data, and Pointer registers. Popping RETI from Supervisor stack ensures that interrupts are suspended between load of return address and RTI. */ (R7:0, P5:0) = [SP++] ; = [SP++] ; ASTAT = [SP++] ; RETI = [SP++] ; ADSP-BF535 Blackfin Processor Hardware Reference 4-51...
Page 198: Logging Of Nested Interrupt Requests
For a shared inter- rupt, the interrupt acknowledge mechanism described above IPEND re-enables all shared interrupts. If any of the shared interrupt sources are 4-52 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 199: Self-Nesting Mode
The bit is automatically RETI[0] set on entry into an interrupt service routine, and it is simply used as a sta- tus bit to flag the processor that the current ISR is self-nesting. ADSP-BF535 Blackfin Processor Hardware Reference 4-53...
Page 200: Exception Handling
NMIs, and emulation events do not affect the interrupt system. Note, however, the return instructions for exceptions ( , and do clear the least significant bit currently set in IPEND 4-54 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 201: Deferring Exception Processing
/* Mask the contents of SEQSTAT, and leave only EXCAUSE in R0 */ R0 <<= 26 ; R0 >>= 26 ; /* Using jump table EVTABLE, jump to the event pointed by R0 */ P0 = R0 ; ADSP-BF535 Blackfin Processor Hardware Reference 4-55...
Page 202 .byte2 addr_event1; .byte2 addr_event2; .byte2 addr_eventN; /* The jump table EVTABLE holds 16-bit address offsets for each event. With offsets, this code is position-independent and the table is small. +--------------+ | addr_event1 | _EVTABLE 4-56 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 203: Example Code For An Exception Routine
NMI, or emulator event, respectively. Do not use them to return from a lower-priority event. To return from an interrupt, use the instruction. Failure to use the correct instruction produces the following results. ADSP-BF535 Blackfin Processor Hardware Reference 4-57...
Page 204: Recommendation For Allocating The System Stack
(ISR) may be held off for around 30 instruction clock cycles. When cache line fill operations are taken into account, the ISR could be held off for many hundreds of cycles. 4-58 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 205 Note the ISR must reside in L1 cache or SRAM memory and must not generate a cache miss, an L2 memory access, or a peripheral access, as the SBIU is already busy completing the original cache line fill operation. If a ADSP-BF535 Blackfin Processor Hardware Reference 4-59...
Page 206 Writes to slow memory generally do not show this behavior, as the writes are deemed to be single cycle, being immediately transferred to the write buffer for subsequent execution. For detailed information about cache and memory structures, see “Mem- ory” on page 6-1. 4-60 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 207: Data Address Generators
The DAG subsystem comprises two DAG Arithmetic units, eight Pointer registers, four Index registers and four complete sets of related Modify, Base and Length registers. These registers hold the values that the DAGs use to generate addresses. The types of registers are: ADSP-BF535 Blackfin Processor Hardware Reference...
Page 208 . The Pointer registers have no effect on circular buffer addressing. They can be used for 8-, 16-, and 32-bit memory accesses. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 209 B-register does not automatically initialize the I-register. Data Address Generator Registers (DAGs) User SP Supervisor SP Supervisor only register. Attempted read or write in User mode causes an exception error. Figure 5-1. ADSP-BF535 Processor DAG Registers ADSP-BF535 Blackfin Processor Hardware Reference...
Page 210: Addressing With Dags
Instructions using Index registers use an M-register or a small immediate value (+/– 2 or 4) as the modifier. Instructions using Pointer registers use a small immediate value or another P-register as the modifier. For instruc- tion summary details, see Table 5-3 on page 5-17. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 211: Frame And Stack Pointers
User Stack Pointer into . The register alias can only be used in Supervisor mode. Some load/store instructions use exclusively, for example: • -indexed load/store, which extends the addressing range for 16-bit encoded load/stores • Stack push/pop instructions ADSP-BF535 Blackfin Processor Hardware Reference...
Page 212: Addressing Circular Buffers
To address a circular buffer, the DAG steps the index pointer (I-register) through the buffer values, post-modifying and updating the index on each access with a positive or negative modify value from the M-register. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 213 • If M is positive: • I if I + M < buffer base + length (end of buffer) • I + M – L  if I buffer base + length (end of buffer) ADSP-BF535 Blackfin Processor Hardware Reference...
Page 214 Figure 5-2. Circular Data Buffers • If M is negative: • I  if I buffer base (start of buffer) • I + M + L if I + M < buffer base (start of buffer) ADSP-BF535 Blackfin Processor Hardware Reference...
Page 215: Addressing With Bit-Reversed Addresses
16-bit value from an address pointed to by and stores it in the 16-bit destination register R0.H. [ P1 ] = R0 is an example of a 32-bit store operation. Pointer registers can be used for 8-bit loads and stores. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 216: Auto-Increment And Auto-Decrement Addressing
Auto-decrement works the same way by decrementing the address after the access. For example: R0 = [ I2-- ] ; loads a 32-bit value into the destination register and decrements the Index register by 4. 5-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 217: Pre-Modify Stack Pointer Addressing
Pointer registers are modified by another Pointer register. Index registers are modified by a Modify register. This instruction does not sup- port the Pointer registers as a destination register, nor does it support byte-addressing. ADSP-BF535 Blackfin Processor Hardware Reference 5-11...
Page 218: Modifying Dag And Pointer Registers
The instruction modifies addresses in any DAG Index and Pointer register ) without accessing memory. If the Index register’s I[3:0] P[5:0] corresponding B- and L-registers are set up for circular buffering, the instruction performs the specified buffer wraparound (if needed). 5-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 219: Memory Address Alignment
• 32-bit word load/stores are accessed on four-byte boundaries, meaning the two least significant bits of the address are b#00. • 16-bit word load/stores are accessed on two-byte boundaries, meaning the least significant bit of the address must be b#0. ADSP-BF535 Blackfin Processor Hardware Reference 5-13...
Page 220 16-bit half word from Data Register high half 16-bit half word from Data Register low half  Be careful when using the instruction, because it dis- DISALGNEXPT ables automatic detection of memory alignment errors. 5-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 221 I Post-inc Indirect Indexed Indexed Post- Auto- Indirect [P0++] [P0--] [P0] [P0+im] [FP+im] [P0++P1] [I0++] [I0--] [I0] [I0++M0] 32-bit Word 16-bit Half Word 8-bit Byte Sign/ Zero Extend Data Register Pointer Register Data Register Half ADSP-BF535 Blackfin Processor Hardware Reference 5-15...
Page 222: Dag Instruction Summary
• X denotes the sign-extension qualifier. • BREV denotes the bit-reversal qualifier. Blackfin Processor Programming Reference more fully describes the options that may be applied to these instructions and the sizes of immediate fields. 5-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 223 Dreg =W [ Preg ++ ] (Z) ; Dreg =W [ Preg -- ] (Z) ; Dreg =W [ Preg + uimm5m2 ] (Z) ; Dreg =W [ Preg + uimm16m2 ] (Z) ; ADSP-BF535 Blackfin Processor Hardware Reference 5-17...
Page 224 Dreg = B [ Preg + uimm15 ] (Z) ; Dreg = B [ Preg – uimm15 ] (Z) ; Dreg = B [ Preg ] (X) ; Dreg = B [ Preg ++ ] (X) ; 5-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 225 [ Ireg ++ Mreg ] = Dreg ; W [ Ireg ] = Dreg_hi ; W [ Ireg ++ ] = Dreg_hi ; W [ Ireg -- ] = Dreg_hi ; W [ Preg ] = Dreg_hi ; ADSP-BF535 Blackfin Processor Hardware Reference 5-19...
Page 226 B [ Preg – uimm15 ] = Dreg ; Preg = imm7 (X) ; Preg = imm16 (X) ; Preg += Preg (BREV) ; Ireg += Mreg (BREV) ; Preg –= Preg ; Ireg –= Mreg ; 5-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 227: Memory
The smallest unit of memory that is transferred to/from the next level of memory from/to a cache as a result of a cache miss. cache hit. A memory access that is satisfied by a valid, present entry in the cache. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 228 Address portion that is used to select an array element (for example, a line index). invalid. Describes the state of a cache line. When a cache line is invalid, a cache line match cannot occur. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 229 A group of N-line storage locations in the Ways of an N-Way cache, selected by the field of the address (see Figure 6-6 on page 6-18). INDEX set-associative. Cache architecture that limits line placement to a number of sets (or Ways). ADSP-BF535 Blackfin Processor Hardware Reference...
Page 230 A cache write policy (also known as store through). The write data is writ- ten to both the cache line and to the source memory. The modified cache line is not written to the source memory when it is replaced. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 231: Memory Architecture
6-1, L1 instruction and data memories occupy 52 KB of internal memory space: • 16 KB of instruction SRAM/cache • 32 KB of data SRAM/cache (two 16 KB banks) • 4 KB of data scratchpad SRAM ADSP-BF535 Blackfin Processor Hardware Reference...
Page 232 The upper portion of internal memory space is allocated to the core and system MMRs of the ADSP-BF535 processor. Accesses to this area are allowed only when the processor is in Supervisor mode or Emulation mode (see “Operating Modes and States” on page 3-1). ADSP-BF535 Blackfin Processor Hardware Reference...
Page 233 SDRAM. Each bank can vary in size from 16 MB to 128 MB. An additional four banks of asynchronous memory space are also available. Each of the asynchronous banks is 64 MB. Figure 6-2 shows the overall memory architecture for the ADSP-BF535 processor. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 234 32 KB BLOCK 0 BLOCK 7 EXTERNAL ACCESS BUS SRAM SRAM (EAB) MEMORY MEMO RY EXTERNAL MASTERED BUS (EMB) EBIU PCI MEMORY ASYNCHRO NO US AND I /O SYNCHRONOUS MEMORY Figure 6-2. ADSP-BF535 Memory Architecture ADSP-BF535 Blackfin Processor Hardware Reference...
Page 235: Internal Memory
• Fast SRAM access for critical processor algorithms and fast context switching • Instruction and data cache options for microcontroller code, excel- lent High-Level Language (HLL) support, and ease of programming cache control instructions, such as PREFETCH FLUSH • Memory protection ADSP-BF535 Blackfin Processor Hardware Reference...
Page 236: Overview Of L1 Instruction Sram
2-Way cache rather than as a 16 KB direct mapped cache. This also provides two separate locations that can hold cached data, decreasing the rate of cache line replacements and increasing overall performance. 6-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 237: Overview Of Scratchpad Data Sram
SRAM and cannot be configured as cache. For more information about on-chip L2 Memory, see “On-Chip Level 2 (L2) Memory” on page 6-52.  On-chip and off-chip L2 memories are capable of storing both instructions and data. ADSP-BF535 Blackfin Processor Hardware Reference 6-11...
Page 238: Level 1 Memory
L1 Instruction Mem- ENIM ory is enabled and configured as SRAM after reset. The bit is used ENICPLB to enable/disable the sixteen CPLBs used for instructions (see “L1 Instruc- tion Cache” on page 6-17). 6-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 239: Data Memory Control Register (Dmem_Control)
Cacheable Address Space into 10 - Data Bank A is cache, Data Banks” on page 6-41. Data Bank B is SRAM 11 - Both data banks are cache Figure 6-3. L1 Data Memory Control Register ADSP-BF535 Blackfin Processor Hardware Reference 6-13...
Page 240: Instruction Memory Control Register (Imem_Control)
• A simple SRAM • A 4-Way, set associative instruction cache • A cache with as many as four locked Ways L1 Instruction SRAM L1 Instruction Memory can be configured as a 16 KB SRAM. 6-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 241 Supervisor mode or Emulation mode.  Before changing the configuration state, be sure to flush the cache or move all modified data from the SRAM, if so configured. ADSP-BF535 Blackfin Processor Hardware Reference 6-15...
Page 242 0xFFA0 3000 Figure 6-5 describes the bank architecture of the L1 Instruction Memory. 4 KB SUB-BANK 4 KB SUB-BANK FILL INSTRUCTION 4 KB SUB-BANK 4 KB SUB-BANK Figure 6-5. L1 Instruction Memory Bank Architecture 6-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 243: L1 Instruction Cache
Instead, these bits are used to identify the 4 KB memory sub-bank targeted for the access. The LRU bits are part of an LRU algorithm used to determine which cache line should be replaced if a cache miss occurs. ADSP-BF535 Blackfin Processor Hardware Reference 6-17...
Page 244 32-BYTE LINE 2 32-BYTE LINE 3 32-BYTE LINE 4 32-BYTE LINE 5 ..LINE 127 SHADED BOXES ACROSS EACH WAY CONSTITUTE A SET Figure 6-6. Blackfin Instruction Cache Organization 6-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 245: Cache Hits And Misses
The cache set is selected, using bits 9 through 5 of the instruction fetch address. If the address tag compare operation results in a match, a cache hit occurs. If the address tag compare operation does not result in a match, a cache miss occurs. ADSP-BF535 Blackfin Processor Hardware Reference 6-19...
Page 246: Cache Line Fills
L2 memory returns the target instruction word first. After it has returned the target instruction word, the next three words are fetched in sequential address order. This fetch will wrap around if necessary, as shown in Table 6-2. 6-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 247: Line Fill Buffer
18 bits plus bits 11 and 10 of the instruction fetch address. The contents of the Way field identify the cache Way selected for replacement (see Table 6-3). Both fields are loaded at the end of a tag-address compare operation that results in a cache miss. ADSP-BF535 Blackfin Processor Hardware Reference 6-21...
Page 248: Non-Cacheable Accesses
Way0, Way1, Way2, or Way3 (see the cache organization in Figure 6-6 on page 6-18). 6-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 249 The coherency of instruction cache must be explicitly managed. To accomplish this and ensure that the instruction cache fetches the latest version of any modified instruction space, invalidate instruc- tion cache line entries, as required. ADSP-BF535 Blackfin Processor Hardware Reference 6-23...
Page 250: Instruction Cache Management
(ISRs) from potentially corrupting the locked cache. • Set the locks for the other Ways of the cache by setting ILOC[3:1] Only Way0 of the instruction cache can now be replaced by new code. 6-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 251: Instruction Cache Invalidation
ADSP-BF535 processor comes out of reset; it sets the Valid bit of each cache line to the invalid state. To implement this technique, additional MMRs are available to allow arbitrary read/write of all cache entries directly. ADSP-BF535 Blackfin Processor Hardware Reference 6-25...
Page 252: Instruction Test Registers
Access to these registers is possible only in Supervisor mode or Emulation mode. When writing to registers, always write to the ITEST ITEST_DATAx registers first, then the register. When reading from ITEST_COMMAND ITEST registers, write the register first, then read the ITEST_COMMAND ITEST_DATA registers. 6-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 253: Instruction Test Command Register (Itest_Command)
1 - Write access Array Access 0 - Access tag array 1 - Access data array Double-Word Index[1:0] Selects one of four 64-bit double words in a 256-bit line Figure 6-9. Instruction Test Command Register ADSP-BF535 Blackfin Processor Hardware Reference 6-27...
Page 254: Instruction Test Data 1 Register (Itest_Data1)
When accessing tag arrays, all bits are reserved. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = Undefined 15 14 13 12 11 10 9 Figure 6-10. Instruction Test Data 1 Register 6-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 255: Instruction Test Data 0 Register (Itest_Data0)
Dirty Physical address 0 - Cache line unmodified since it was copied from source memory 1 - Cache line modified since it was copied from source memory Figure 6-11. Instruction Test Data 0 Register ADSP-BF535 Blackfin Processor Hardware Reference 6-29...
Page 256: Example Code For Direct Invalidation
/* r4 - contains mask for the set index (bit[5:9]=00000) */ /* r5 - contains mask for the ways (bit[26:27]=00) */ /* r6 - value written to ITEST DATA0 */ * TAG write */ - contains the original address */ 6-30 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 257 /* Writing zero to the ITEST_DATA0 */ /* Whenever we write to Cache TAG/ARRAY, the value in the ITEST_DATA0 gets written to the caches. The ITEST_DATA0/1 should be written to before the write to ITEST_COMMAND register */ ADSP-BF535 Blackfin Processor Hardware Reference 6-31...
Page 258 /* sub-bank increment, at the end of inner loop */ R3.H = 1; P4 = 4; /* Number of sub-bank - also outer loop counter (Should be 2 for D-cache) */ P3 = R2; /* Inner loop counter (Number of set index) */ 6-32 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 259 = p4; LBL0B: r0 = r4; r1 = r5; lsetup(LBL1B,LBL2B) lc0 = p3; LBL1B: r0 = r0+|+r2 || [i0]=r0; LBL2B: r1 = r1+|+r2 || [i0]=r1; r4 = r4+r3; LBL3B: r5 = r5+r3; ADSP-BF535 Blackfin Processor Hardware Reference 6-33...
Page 260 Instruction Cache has 64 sets (cache lines), hence loop count is 64 */ - Outer loop: */ Increment sub-banks */ repeat inner loop */ do it 4 times because of 4 sub-banks. */ - Repeat again for superbank B */ 6-34 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 261 = p4; LBL0C: r0 = r4; r1 = r5; lsetup(LBL1C,LBL2C) lc0 = p3; LBL1C: r0 = r0+|+r2 || [i0]=r0; LBL2C: r1 = r1+|+r2 || [i0]=r1; r4 = r4+r3; LBL3C: r5 = r5+r3; ADSP-BF535 Blackfin Processor Hardware Reference 6-35...
Page 262 /* Configure L1 SRAM code bank as SRAM */ /* - Default to ILOC==0000 */ /* - Set ENIM==1, so Code memory is enabled. */ P0.L = (IMEM_CONTROL & 0xFFFF); P0.H = (IMEM_CONTROL >> 16); R0 = (ENIM); 6-36 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 263: L1 Data Memory
Figure 6-3 on page 6-13). The bit is used to enable or disable both ENDM L1 data banks.  is cleared, L1 memory is disabled, and all data memory ref- ENDM erences generate exceptions. ADSP-BF535 Blackfin Processor Hardware Reference 6-37...
Page 264: L1 Data Sram
DAG references to the same data bank. The division into sub-banks and subsequent code optimization also permit system DMA access—for example, to preload or postunload data buffers. For more information, see“Data Address Generators” on page 5-1. 6-38 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 265 L1 Data Memory architecture. FILL A 16 KB DATA BANK A DMA A 4 KB SRAM FILL B DATA 0 16 KB DATA BANK B DATA 1 DMA B Figure 6-12. L1 Data Memory Architecture ADSP-BF535 Blackfin Processor Hardware Reference 6-39...
Page 266: L1 Data Cache
CPLB entry. The data cache cannot, however, contain data from the MMR address space, which is always cache inhibited. Software must maintain the CPLBs in a manner consis- tent with the hardware configuration. 6-40 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 267: Example Of Mapping Cacheable Address Space Into Data Banks
An example of how the cacheable address space maps into the two banks follows. When both banks are configured as cache, they operate as two indepen- dent, 16 KB, 2-Way set associative caches that can be independently mapped into the Blackfin address space. ADSP-BF535 Blackfin Processor Hardware Reference 6-41...
Page 268 2-Way set-associative 32 KB cache. Each Way is 16 KB long and all data elements having the same first 14 bits of address compete for two entries that may be used to store them. 6-42 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 269 This arrangement causes the core to use both data buses for cache line transfer and achieves the maximum data bandwidth between the cache and the core. Figure 6-14 shows an example of how mapping is performed when DCBS ADSP-BF535 Blackfin Processor Hardware Reference 6-43...
Page 270 If a col- lision is detected, the access priority is: • System DMA access • Cache Line Fill • DAGs 6-44 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 271: Data Cache Access
DAG as it updates the cache line. In other words, the cache performs critical word forwarding. ADSP-BF535 Blackfin Processor Hardware Reference 6-45...
Page 272: Cache Write Method
The L1 Data Memory employs a full cache line width copyback buffer on each data bank. In addition, a four-entry write buffer in the L1 Data Memory accepts all stores with cache inhibited or store through protec- tion. An instruction flushes the write buffer. SSYNC 6-46 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 273: Data Cache Control Instructions
Data Test Registers Like L1 Instruction Memory, L1 Data Memory contains additional MMRs to allow arbitrary read/write of all cache entries directly. They make provide a mechanism for data cache test, initialization, and debug. ADSP-BF535 Blackfin Processor Hardware Reference 6-47...
Page 274 Access to these registers is possible only in Supervisor or Emulation mode. When writing to registers, always write to the registers DTEST DTEST_DATA first, then the register. When reading from registers, DTEST_COMMAND DTEST reverse the sequence. Always read the register first, then DTEST_COMMAND registers. DTEST_DATA 6-48 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 275: Data Test Command Register (Dtest_Command)
) contain the 64-bit data to be DTEST_DATA[1:0] written, or they contain the destination for the 64-bit data read. The Data Test Data 1 register ( ), shown in Figure 6-16, stores the DTEST_DATA1 upper 32 bits. ADSP-BF535 Blackfin Processor Hardware Reference 6-49...
Page 276 32 bits of the 64-bit data to be written or of the destination for the 64-bit data read. register is also used to access the tag arrays and contains DTEST_DATA0 the Valid and Dirty bits, which indicate the state of the cache line. 6-50 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 277: Data Test Data 0 Register (Dtest_Data0)
Physical address Dirty 0 - Cache line unmodified since it was copied from source memory 1 - Cache line modified after it was copied from source memory Figure 6-17. Data Test Data 0 Register ADSP-BF535 Blackfin Processor Hardware Reference 6-51...
Page 278: On-Chip Level 2 (L2) Memory
In this case, the L2 finishes the burst transfer before the system bus is granted access. 6-52 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 279: Latency
L1 cache line fills from the L2 SRAM in cycles. In other 7+1+1+1=10 words, after seven core cycles, the first 64-bit (8-byte) fill is available for the processor. Figure 6-19 shows an example of L2 latency with cache on. ADSP-BF535 Blackfin Processor Hardware Reference 6-53...
Page 280 When on-chip L2 memory is configured as non-cacheable, instruction fetches and data fetches occur in 64-bit fills. In this case, each fill takes seven core cycles to complete. As shown in Figure 6-20, on-chip L2 6-54 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 281: Off-Chip L2 Memory
SDRAM bank is programmable. Each SDRAM bank can range in size from 16 MB to 128 MB. The start address of bank 0 is 0x0000 0000. The start addresses of banks 1, 2, and 3 follow contiguously from the previous ADSP-BF535 Blackfin Processor Hardware Reference 6-55...
Page 282: Memory Protection And Properties
The MMU provides great flexibility in allocating memory and I/O resources between tasks, with complete control over access rights and cache behavior. 6-56 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 283 ICPLB_DATA[n] CPLB descriptor. For data operations: • defines the start address of the page described by DCPLB_ADDR[m] the CPLB descriptor. • defines the properties of the page described by the DCPLB_DATA[m] CPLB descriptor. ADSP-BF535 Blackfin Processor Hardware Reference 6-57...
Page 284: Memory Pages
] and a properties descriptor word xCPLB_ADDR[n . The address descriptor word provides the base address of xCPLB_DATA[n] the page in memory. Pages must be aligned on page boundaries that are an 6-58 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 285 • User write access permission • Enables or disables writes to this page when in User mode • Data pages only • User read access permission Enables or disables reads from this page when in User mode ADSP-BF535 Blackfin Processor Hardware Reference 6-59...
Page 286: Page Descriptor Table
Page Descriptor Table structures that are consistent with the OS requirements. This allows adjustments to be made between the level of protection afforded versus the performance attributes of the memory-management support routines. 6-60 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 287: Cplb Management
After the new CPLB descriptor is loaded, the exception handler returns, and the faulting memory operation restarted. It should then find a valid CPLB descriptor for the requested address, and the operation should proceed. ADSP-BF535 Blackfin Processor Hardware Reference 6-61...
Page 288: Mmu Application
CPLB descriptors for protected memory ranges that allow write access only when in Supervisor mode. If a write to a protected memory region is attempted while in User mode, an 6-62 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 289: Examples Of Protected Memory Regions
For example, on-chip L2 memory would typically be configured as cacheable with an instruction and data CPLB. In such a case, external memory would take advantage of the page replacement mechanism described in the section above. ADSP-BF535 Blackfin Processor Hardware Reference 6-63...
Page 290 Async: Non-cacheable One 4 MB page Two 4 MB pages One 4 MB page Scratchpad: Non-cacheable Async: Cacheable DATA CPLB SETUP 4 KB page One 4 MB page Figure 6-21. Examples of Protected Memory Regions 6-64 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 291: Dcplb Data Registers (Dcplb_Datax)
0 - Write access not allowed in Supervisor mode. If a write access is attempted in Supervisor mode, a Protection Violation exception occurs. 1 - Write access allowed in Supervisor mode Figure 6-22. DCPLB Data Registers ADSP-BF535 Blackfin Processor Hardware Reference 6-65...
Page 292 0xFFE0 0210 DCPLB_DATA5 0xFFE0 0214 DCPLB_DATA6 0xFFE0 0218 DCPLB_DATA7 0xFFE0 021C DCPLB_DATA8 0xFFE0 0220 DCPLB_DATA9 0xFFE0 0224 DCPLB_DATA10 0xFFE0 0228 DCPLB_DATA11 0xFFE0 022C DCPLB_DATA12 0xFFE0 0230 DCPLB_DATA13 0xFFE0 0234 DCPLB_DATA14 0xFFE0 0238 DCPLB_DATA15 0xFFE0 023C 6-66 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 293: Icplb Data Registers (Icplb_Datax)
0 - Read access not allowed in User mode. If a read access is attempted in User mode, a Protection Violation exception occurs. 1 - Read access allowed in User mode Figure 6-23. ICPLB Data Registers ADSP-BF535 Blackfin Processor Hardware Reference 6-67...
Page 294 0xFFE0 1210 ICPLB_DATA5 0xFFE0 1214 ICPLB_DATA6 0xFFE0 1218 ICPLB_DATA7 0xFFE0 121C ICPLB_DATA8 0xFFE0 1220 ICPLB_DATA9 0xFFE0 1224 ICPLB_DATA10 0xFFE0 1228 ICPLB_DATA11 0xFFE0 122C ICPLB_DATA12 0xFFE0 1230 ICPLB_DATA13 0xFFE0 1234 ICPLB_DATA14 0xFFE0 1238 ICPLB_DATA15 0xFFE0 123C 6-68 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 295: Dcplb Address Registers (Dcplb_Addrx)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ments, see Reset = Undefined Table 6-10. Address for Match[21:6] 15 14 13 12 11 10 Address for Match[5:0] Figure 6-24. DCPLB Address Registers ADSP-BF535 Blackfin Processor Hardware Reference 6-69...
Page 296 0xFFE0 0110 DCPLB_ADDR5 0xFFE0 0114 DCPLB_ADDR6 0xFFE0 0118 DCPLB_ADDR7 0xFFE0 011C DCPLB_ADDR8 0xFFE0 0120 DCPLB_ADDR9 0xFFE0 0124 DCPLB_ADDR10 0xFFE0 0128 DCPLB_ADDR11 0xFFE0 012C DCPLB_ADDR12 0xFFE0 0130 DCPLB_ADDR13 0xFFE0 0134 DCPLB_ADDR14 0xFFE0 0138 DCPLB_ADDR15 0xFFE0 013C 6-70 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 297: Icplb Address Registers (Icplb_Addrx)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 For MMR assign- Reset = Undefined ments, see Table 6-11. Address for Match[21:6] 15 14 13 12 11 10 Address for Match[5:0] Figure 6-25. ICPLB Address Registers ADSP-BF535 Blackfin Processor Hardware Reference 6-71...
Page 298 ) and ICPLB Status reg- DCPLB_STATUS ister ( ) identify the CPLB entry that has triggered CPLB ICPLB_STATUS related exceptions. The exception service routine can infer the cause of the fault by examining the CPLB entries. 6-72 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 299 1 - Access was made in Supervisor mode 15 14 13 12 11 10 FAULT[15:0] Each bit indicates that the DCPLB associated with that bit has faulted. DCPLB0 fault sets FAULT0, DCPLB15 sets FAULT15. Figure 6-26. DCPLB Status Register ADSP-BF535 Blackfin Processor Hardware Reference 6-73...
Page 300: Icplb_Status)
), shown in DCPLB_FAULT_ADDR Figure 6-28, and ICPLB Fault Address register ( ICPLB_FAULT_ADDR shown in Figure 6-29, hold the address that has caused a fault in the L1 Data Memory or L1 Instruction Memory, respectively. 6-74 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 301: Dcplb Fault Address Register (Dcplb_Fault_Addr)
Data address that has caused a fault in L1 Data Memory 15 14 13 12 11 10 FAULT_ADDR[15:0] Data address that has caused a fault in the L1 Data Memory Figure 6-28. DCPLB Fault Address Register ADSP-BF535 Blackfin Processor Hardware Reference 6-75...
Page 302: Memory Transaction Model
B0 refers to the least significant byte of the 32-bit word. DATA IN REGISTER DATA IN MEMORY addr+3 addr+2 addr+1 addr Figure 6-30. Data Stored in Little Endian Order 6-76 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 303: Load/Store Operation
The separation is made, because memory operations, particu- larly instructions that access off-chip memory or I/O devices, often take multiple cycles to complete and would normally halt the processor, pre- venting an instruction execution rate of one instruction per cycle. ADSP-BF535 Blackfin Processor Hardware Reference 6-77...
Page 304: Interlocked Pipeline
If the instruction immedi- ately following the load uses the same register, it simply stalls until the value is returned. Consequently, it operates as the programmer expects. 6-78 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 305: Ordering Of Loads And Stores
This ordering provides significant performance advantages in the opera- tion of most memory instructions. However, it can cause side effects that the programmer must be aware of to avoid improper system operation. ADSP-BF535 Blackfin Processor Hardware Reference 6-79...
Page 306: Synchronizing Instructions
Pending core operations may include any pending interrupts, speculative states (such as branch predictions) or exceptions. Consider this example code sequence: IF CC JUMP away_from_here csync; r0 = [p0]; away_from_here: 6-80 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 307: Speculative Load Execution
For example, IF CC JUMP away_from_here RO = [P2]; … away_from_here: ADSP-BF535 Blackfin Processor Hardware Reference 6-81...
Page 308: Conditional Load Behavior
However, for some memory-mapped devices, such as peripheral data FIFOs, reads are destructive. Each time the device is read, the FIFO advances, and the data cannot be recovered and re-read. 6-82 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 309: Working With Memory
6-47), and/or explicit line invalidation through the core MMRs (see “ICPLB Address Registers (ICPLB_ADDRx)” on page 6-71). Atomic Operations Atomic operations are used to provide non-interruptible memory opera- tions in support of semaphores between tasks. ADSP-BF535 Blackfin Processor Hardware Reference 6-83...
Page 310: Memory-Mapped Registers
MMRs (0xFFC0 0000-0xFFE0 0000) and core MMRs (0xFFE0 0000-0xFFFF FFFF).  If strong ordering is required, place a synchronization instruction after stores to MMRs. For more information, see “Load/Store Operation” on page 6-77. 6-84 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 311: Core Mmr Programming Code Example
In the code listing, CLI saves the contents of the register and dis- IMASK ables interrupts by clearing , while restores the contents of the IMASK register, thus enabling interrupts. The instructions between IMASK are not interruptible. ADSP-BF535 Blackfin Processor Hardware Reference 6-85...
Page 312 Working With Memory 6-86 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 313: Chip Bus Hierarchy
In the figure, a box receiving an arrow is a slave on that bus and a box sourcing an arrow is a master on that bus. The System Bus Interface Unit (SBIU) functions as the major crossbar switch between the various buses. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 314: Adsp-Bf535 Internal Clocks
Access Bus (EAB), the External Mastered Bus (EMB), and the External Bus Interface Unit (EBIU) run at the core clock frequency ( domain) CCLK divided by 2, 2.5, 3, or 4. This divided frequency is the frequency of the ADSP-BF535 Blackfin Processor Hardware Reference...
Page 315: Core Overview
• Bank1 Load/Store (Core D1 bus), used to write or store 32 bits of data to or from memory The core can generate up to three simultaneous off-core accesses per cycle. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 316 The Core I bus, the Core D0 bus, the Core D1 bus, and the System L1 bus run at the full core frequency, have data paths up to 64 bits, and sup- port burst transfers. All four ports have 32-bit address buses. The Core D0 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 317: System Overview
System Bus Interface Unit (SBIU) The SBIU functions as a high-speed parallel switch, or router. It provides crossbar switches between the core buses, operating at the full core fre- quency, and the system buses, running at the frequency. SCLK ADSP-BF535 Blackfin Processor Hardware Reference...
Page 318 • A peripheral DMA channel is accessing L1 memory. • PCI is accessing L2 memory. • The core is fetching instructions from L2 memory. • Core D0 is accessing a system MMR on the PAB. • Core D1 is accessing external memory. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 319: On-Chip L2 Sram Memory Interface
There are also two primary chip pin buses, the PCI Bus and the External Bus Interface Unit (EBIU). The PCI Bus is discussed in “PCI Bus Inter- face” on page 13-1. The External Bus Interface Unit is discussed in “External Bus Interface Unit” on page 18-1. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 320: Peripheral Bus (Pab)
MMR (single cycle) read or write accesses take 6 core clocks ( ) of latency. CCLK With a 300 MHz core clock and a 1:2.5 bus clock ratio, the peak periph- eral bus throughput is 240 MBytes per second. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 321: Pab Agents (Masters, Slaves)
• Clock and Power Management Controller • Watchdog Timer • Real Time Clock • Timer 0, 1, and 2 • SPORT0 • SPORT1 • SPI0 • SPI1 • Programmable Flags • UART0 • UART1 • USB ADSP-BF535 Blackfin Processor Hardware Reference...
Page 322: Dma Bus (Dab)
SRAM and L2. For off-chip memory, the core has priority over the DAB on the EAB bus. The ADSP-BF535 processor uses a fixed prior- ity arbitration policy on the DAB. Table 7-2 shows the arbitration priority. 7-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 323: Dab Performance
PCI direct access, and the DMA access are not to the same memory bank (4 KB size for L1, 32 KB size for L2). If there is a conflict, PCI is the highest priority requester, followed by the DMA access, then by the core. ADSP-BF535 Blackfin Processor Hardware Reference 7-11...
Page 324 Burst Read from L1 Memory Best case (4:1) 6-2-2-2 6-2-2-2-2-2-2-2 Burst Write to L2 Memory All ratios 4-1-1-1 4-1-1-1-1-1-1-1 (16-byte and 32-byte) Burst Read from L2 Memory 4:1, 3:1 5-1-1-1 5-1-1-1-1-1-1-1 (16-byte and 32-byte) 2.5:1, 2:1 6-1-1-1 6-1-1-1-1-1-1-1 7-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 325 The throughput rate for an on-chip/off-chip memory access is limited by the slower of the two accesses. An additional 1 to 2 cycles per burst access is inherent in the design. ADSP-BF535 Blackfin Processor Hardware Reference 7-13...
Page 326: Dab Bus Agents (Masters)
The EAB provides a way for the processor core and the Memory DMA controller to directly access off-chip memory and the PCI memory space to perform instruction fetches, data loads, data stores, and high through- put memory-to-memory DMA transfers. 7-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 327: Eab Arbitration
EAB slaves, and the many possible uses of these resources for different applications, this analysis may not apply to a particular application. It is presented here for comparative purposes only. ADSP-BF535 Blackfin Processor Hardware Reference 7-15...
Page 328 PCI write, 16-byte burst, FIFO empty PCI write, 32-byte burst, FIFO empty PCI write, non-burst, 1 PCI cycle for arbitration + 1 FIFO full PCI cycle for address + 1 PCI cycle for data (4 bytes) 7-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 329: Eab Bus Agents (Masters, Slaves)
10% page misses burst, to SDRAM EAB Bus Agents (Masters, Slaves) The SBIU and the Memory DMA controller devices are masters on this bus. The PCI, boot ROM, and EBIU are slaves on this bus. ADSP-BF535 Blackfin Processor Hardware Reference 7-17...
Page 330: External Mastered Bus (Emb)
EMB Bus Agents (Masters, Slaves, Bridges) The PCI is the only master on this bus. The SBIU and EBIU are the slaves on this bus. The PCI controller is a bridge between the EMB and the PCI buses. 7-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 331: Resources Accessible From Emb
The EMB does not have access to: • L1 memory • Boot ROM • PCI space (the PCI EAB slave cannot be accessed by the EMB bus, but the system MMRs of the PCI can be accessed) ADSP-BF535 Blackfin Processor Hardware Reference 7-19...
Page 332 System Interfaces 7-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 333: Dynamic Power Management
8 DYNAMIC POWER MANAGEMENT This chapter describes the Dynamic Power Management functionality of the ADSP-BF535 Blackfin processor. This functionality includes: • Clocking • Phase Locked Loop (PLL) • Dynamic Power Management Controller • Operating Modes • Voltage Control Clocking The input clock into the ADSP-BF535 processor,...
Page 334: Phase Locked Loop And Clock Control
, is a square wave derived from a crystal oscillator CLKIN or external reference clock. The Voltage Controlled Oscillator ( ) is an intermediate clock from which the core clock ( ) and system clock CCLK ) are derived. SCLK ADSP-BF535 Blackfin Processor Hardware Reference...
Page 335: Pll Clock Multiplier Ratios
MSEL[6] • The bits control the feedback dividers MSEL[5:0] • The feedback divider is composed in two stages, a divide by N (1:32), selected by and a divide by 2, selected by MSEL[4:0], MSEL[5] ADSP-BF535 Blackfin Processor Hardware Reference...
Page 336 MSEL[5] to 1. Whether are set to 1 or both are set to 0, multiplica- MSEL[5] tion factors are the same. See ADSP-BF535 Blackfin Embedded Processor Data Sheet for maximum and minimum frequencies for , and CLKIN CCLK Table 8-1.
Page 337: Core Clock/System Clock Ratio Control
Note that the divider ratio CCLK SCLK must be chosen so that does not exceed its maximum frequency. See SCLK ADSP-BF535 Blackfin Embedded Processor Data Sheet for more informa- tion about the maximum frequency of SCLK ADSP-BF535 Blackfin Processor Hardware Reference...
Page 338 Table 8-2 shows the system clock ratio, or frequency ratio of relative SCLK CCLK Table 8-2. System Clock Ratio Signal Name Divider Ratio Example Frequency Ratios (MHz) SSEL[1:0] CCLK/SCLK CCLK SCLK 2.5:1 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 339: Pll Memory-Mapped Registers (Mmrs)
– This bit is used to bypass the PLL. When the PLL is BYPASS bypassed, runs at half the frequency of . Upon reset, the CCLK CLKIN value for this field is sensed from the pin. BYPASS ADSP-BF535 Blackfin Processor Hardware Reference...
Page 340 Figure 8-2. The PLL Control Register  Note some fields of the register cannot be updated with a PLL_CTL new value simultaneously. Specifically, the fields can- MSEL not be updated at the same time as the field. Should BYPASS MSEL ADSP-BF535 Blackfin Processor Hardware Reference...
Page 341: Pll Status Register (Pll_Stat)
( ). For more information, see “PLL Lock PLL_LOCKCNT Count Register (PLL_LOCKCNT)” on page 8-10. • – This field is set to 1 when the ADSP-BF535 processor is in SLEEP the Sleep operating mode. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 342 PLL_LOCKCNT PLL_LOCKED See ADSP-BF535 Blackfin Embedded Processor Data Sheet for more infor- mation about PLL stabilization time and values that should be programmed into this register. For more information about operating modes, see “Operating Modes” on page 8-12.
Page 343: Pll Lock Count Register (Pll_Lockcnt)
Additionally, logic is provided to allow an external power management controller to manipulate the Blackfin processor core’s internal voltage, further reducing power. ADSP-BF535 Blackfin Processor Hardware Reference 8-11...
Page 344: Operating Modes
( ) runs at one-half the input clock CCLK ) frequency, offering significant power savings. The system clock CLKIN ) frequency is also reduced, because it is derived from SCLK 8-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 345: Sleep Mode
STOPCK hardware when the wakeup occurs. Software must explicitly clear in the next write to to avoid going back into sleep STOPCK PLL_CTL mode. ADSP-BF535 Blackfin Processor Hardware Reference 8-13...
Page 346: Deep Sleep Mode
In the diagram, an ellipse represents an operating mode. Thin arrows between the ellipses show the allowed transitions into and out of each mode. 8-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 347 BYPASS=0 & PLL_OFF=0 & STOPCK=0 & PDWN=0 Full On Active BYPASS=1 & STOPCK=0 & PDWN=1 PDWN=0 PDWN=1 RTC_WAKEUP HARDWARE RESET Reset MSEL=new & PLL_OFF=0 & MSEL=new & PLL_OFF=0 & BYPASS=1 BYPASS=0 Figure 8-5. Operating Mode Transitions ADSP-BF535 Blackfin Processor Hardware Reference 8-15...
Page 348 PLL must be powered up to lock to the new ratio. To program a new multiplier, write the new and/or CLKIN CCLK MSEL[6:0] values to the register; then execute the PLL programming PLL_CTL sequence. 8-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 349: Pll Programming Sequence
PLL Programming Sequence Assuming that the PLL Control register ( ) has been modified with PLL_CTL the new values, the instruction sequence shown in Listing 8-1 puts those changes into effect. ADSP-BF535 Blackfin Processor Hardware Reference 8-17...
Page 350 • The wake-up signal is an interrupt generated by a peripheral, watchdog or other timer, RTC, or other source. For more informa- tion about events that cause the processor to wake-up from being idled, see “System Interrupt Wakeup-Enable Register (SIC_IWR)” on page 4-24. 8-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 351: Pll Programming Sequence Continues
Listing 8-1 on page 8-18 then contin- ues with the instruction. Interrupts are re-enabled, is restored IMASK and normal program flow resumes.  To prevent spurious activity, DMA should be suspended while exe- cuting this instruction sequence. ADSP-BF535 Blackfin Processor Hardware Reference 8-19...
Page 352: Examples
/* source NOPs into pipeline, prepare to enter idled state */ SSYNC; /* drain pipeline, enter idled state, wait for watchdog STI R1; /* after watchdog occurs, restore interrupts and IMASK /* processor is now in the Full-On mode */ 8-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 353 /* processor is now in the Active mode */ R1.H = 0x0000; /* set CLKIN to CCLK multiplier to 2x in PLL_CTL, keeping BYPASS bit set as both MSEL and BYPASS cannot be changed simultaneously */ ADSP-BF535 Blackfin Processor Hardware Reference 8-21...
Page 354: Peripheral Clocking
8-6, the Peripheral Clock Enable register ( ) is PLL_IOCK a 16-bit MMR that controls clocking to the peripherals. Each peripheral whose clocking can be controlled is represented by a bit in the register. A 1 8-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 355: Dynamic Supply Voltage Control
8-6. Each power domain has a separate V supply. Note the internal logic of the processor and much of the processor I/O can be run over a range of voltages. See ADSP-BF535 Blackfin Embed- ded Processor Data Sheet for details on the allowed voltage ranges for each power domain and power dissipation data.
Page 356: Pci Power Savings
Minor changes in operating voltage can be accommodated without requir- ing special consideration or action by the application program. See ADSP-BF535 Blackfin Embedded Processor Data Sheet for more informa- tion about voltage tolerances and allowed rates of change. Reducing the ADSP-BF535 processor’s operating voltage to greatly con-...
Page 357: External Voltage Regulator Example
( ), are CCLK within the limits specified in ADSP-BF535 Blackfin Embedded Processor Data Sheet for the new operating voltage level. External Voltage Regulator Example A programmable voltage regulator external to the ADSP-BF535 processor can be used to modify the operating voltage of the processor dynamically.
Page 358: High Performance Sequence
• This signal wakes up the ADSP-BF535 processor, allowing it to complete the transition to the Active operating mode. High Performance Sequence The same sequence used to toggle to power saving mode can be used to return the ADSP-BF535 into a high performance mode. 8-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 359 ADSP-BF535 processor, via a programmable flag, that the voltage has been raised. • The signal from the voltage regulator wakes up the ADSP-BF535 processor, allowing it to complete the transition to the Full On operating mode. ADSP-BF535 Blackfin Processor Hardware Reference 8-27...
Page 360 Dynamic Power Management Controller 8-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 361: Direct Memory Access
Memory DMA controller (MemDMA). Twelve DMA channels and bus masters support these devices: • SPORT0 RCV DMA Controller • SPORT1 RCV DMA Controller • SPORT0 XMT DMA Controller • SPORT1 XMT DMA Controller ADSP-BF535 Blackfin Processor Hardware Reference...
Page 362 DMA transfer automatically after the current sequence com- pletes. Autobuffer based DMA allows the processor to program DMA control registers directly to initiate a DMA transfer. Upon completion, the control registers are automatically updated with their original setup values. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 363: Descriptor Based Dma
• The 32-bit starting address of the data block to be transferred • The number of data transfers • Other miscellaneous control information—for example, the con- figuration for what the DMA channel does when the transfer is complete • A pointer to the next descriptor block ADSP-BF535 Blackfin Processor Hardware Reference...
Page 364: Dma Descriptor Block Structure
A set of descriptor blocks is called a linked list (see Figure 9-1). When a linked list has been generated, the DMA channel has all the information needed to perform multiple transfer sequences without processor intervention. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 365 32-bit load into the descriptor block rather than as two 16-bit loads. For this reason, it is recommended DMA descriptor blocks be 32-bit aligned within memory. At a minimum, descriptor blocks must be 16-bit aligned. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 366: Dma Configuration Word
0 - Processor has ownership 1 - DMA channel has ownership 1 Bit 12 of the DMA Configuration Word is read as a FIFO Status bit and written as a data size bit in some peripherals (see Table 9-3). ADSP-BF535 Blackfin Processor Hardware Reference...
Page 367 Data Size Bit 12 16-bit half word 32-bit word Reserved 8-bit byte 1 Bit 12 of the DMA Configuration Word is read as a FIFO Status bit and writ- ten as a data size bit. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 368: Setting Up Descriptor Based Dma
1. Write the DMA Configuration Word (with bit 15 set to 1), DMA Transfer Count, DMA Start Address[15:0], DMA Start Address[31:16], and Next Descriptor Pointer[15:0] to the descrip- tor block memory addresses BASE+0 through BASE+8. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 369: Descriptor-Based Dma Operation
Descriptor-Based DMA Operation Upon detecting the assertion of the DMA Enable bit in the peripheral’s DMA Configuration register, the DMA channel fetches the first element from the descriptor block, the DMA Configuration Word, and copies it to ADSP-BF535 Blackfin Processor Hardware Reference...
Page 370 (BASE+2, BASE+4, BASE+6, BASE+8) from the descriptor block, loads them to the respective DMA control registers, and begins DMA transfers. • The status of the transfer sequence is updated every cycle in the appropriate peripheral’s DMA status registers. 9-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 371 (Time T1 through Time T5). Figure 9-4, the actions in T1 and T2 are the same as those in T3 and T4 except for the name of the descriptor block. ADSP-BF535 Blackfin Processor Hardware Reference 9-11...
Page 372 DMA. (See Time T2.) DMA channel writes back contents of DMA Configuration register to address A+0 (DMA Configuration Word A) of Descriptor Block A. NEXT PAGE Figure 9-2. Consecutive DMA Sequences With Descriptor Blocks (1 of 2) 9-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 373 B+0 (DMA Configuration Word B) of Descriptor Block B. DMA channel fetches and copies DMA_END Word (=0x0001) into DMA Configuration register and disables DMA. (See Time T5.) Figure 9-3. Consecutive DMA Sequences With Descriptor Blocks (2 of 2) ADSP-BF535 Blackfin Processor Hardware Reference 9-13...
Page 374 LOW REGISTER DMA_END DMA_END DMA START ADDRESS HIG H REG ISTER DMA NEXT DESCRIPTOR POINTER REGISTER DMA CONFIGURATION REGISTER 0x0001 DMA_END Figure 9-4. Time T1 Through T5 of Consecutive DMA Sequences Using Descriptor Blocks 9-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 375: Autobuffer Based Dma
DMA error abort as it would for descriptor based DMA. The Autobuffer Enable bit in the DMA Configuration register can then be cleared. ADSP-BF535 Blackfin Processor Hardware Reference 9-15...
Page 376: Dma Control Registers
The Buffer Clear bit is used to clear the DMA buffer and should be accessed only when a DMA channel is not enabled.  The Buffer Clear bit should not be set when using autobuffer mode. 9-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 377 Control State[1:0] - RO Enable - RO See peripheral 0 - Interrupt disabled documentation 1 - Interrupt enabled Buffer Clear 0 - Normal buffer operation 1 - Clear buffer Figure 9-5. Peripheral DMA Configuration Register ADSP-BF535 Blackfin Processor Hardware Reference 9-17...
Page 378 Word is loaded into the peripheral’s DMA Configuration register. If bit 15 of the Configuration Word is set (DMA channel has ownership), a full descriptor block download is performed, and bit 15 of the peripheral’s DMA Configuration register is set once again. 9-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 379: Peripheral Dma Transfer Count Register
MMR assignments for the peripheral DMA Transfer Count registers. Table 9-5. Peripheral DMA Transfer Count Register MMR Assignments Register Name Memory-Mapped Address SPI0_COUNT 0xFFC0 3208 SPI1_COUNT 0xFFC0 3608 SPORT0_COUNT_RX 0xFFC0 2A08 SPORT1_COUNT_RX 0xFFC0 2E08 SPORT0_COUNT_TX 0xFFC0 2B08 SPORT1_COUNT_TX 0xFFC0 2F08 ADSP-BF535 Blackfin Processor Hardware Reference 9-19...
Page 380 The DMA Transfer Count always decrements by 1 for each bus transfer, independent of the transfer size (8, 16, or 32 bits). A DMA transfer sequence is complete when the transfer count reaches 0. 9-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 381: Peripheral Dma Start Address Registers
MMR assignments for the peripheral DMA Start Address registers. Table 9-6. Peripheral DMA Start Address Register MMR Assignments Register Name Memory-Mapped Address SPI0_START_ADDR_HI 0xFFC0 3204 SPI1_START_ADDR_HI 0xFFC0 3604 SPI0_START_ADDR_LO 0xFFC0 3206 SPI1_START_ADDR_LO 0xFFC0 3606 SPORT0_START_ADDR_HI_TX 0xFFC0 2B04 ADSP-BF535 Blackfin Processor Hardware Reference 9-21...
Page 382 Start Address must be 32-bit aligned. Upon completion of the current access, the DMA address generators increment the start address by 1 for 8-bit transfers, by 2 for 16-bit trans- fers, or by 4 for 32-bit transfers. 9-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 383: Peripheral Dma Next Descriptor Pointer Register
16-bit aligned. This register is not used for autobuffer mode. Peripheral DMA Next Descriptor Pointer Register For MMR assign- 15 14 13 12 11 10 ments, see Table 9-8. Reset = 0x0000 Next Descriptor Pointer[15:0] Figure 9-8. Peripheral DMA Next Descriptor Pointer Register ADSP-BF535 Blackfin Processor Hardware Reference 9-23...
Page 384: Dma Descriptor Base Pointer Register (Dma_Dbp)
9-9, is not updated on DMA descriptor block fetches; software controls it directly. The DMA Descriptor Base Pointer must be restricted to L2 memory space. This register is not used for autobuffer mode and is shared across all peripherals. 9-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 385: Peripheral Dma Descriptor Ready Register
This register is not used for autobuffer mode. Peripheral DMA Descriptor Ready Register Read/write For MMR assign- 15 14 13 12 11 10 Reset = 0x0000 ments, see Table 9-9. Reactivate Descriptor Fetch Figure 9-10. Peripheral DMA Descriptor Ready Register ADSP-BF535 Blackfin Processor Hardware Reference 9-25...
Page 386: Peripheral Dma Current Descriptor Pointer Register
DMA channel is actively processing. This register, shown in Figure 9-11, is loaded with the value from the peripheral’s DMA Next Descriptor Pointer register before each DMA work block is fetched. This register is not used for autobuffer mode. 9-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 387 Memory-Mapped Address SPI0_CURR_PTR 0xFFC0 3200 SPI1_CURR_PTR 0xFFC0 3600 SPORT0_CURR_PTR_RX 0xFFC0 2A00 SPORT1_CURR_PTR_RX 0xFFC0 2E00 SPORT0_CURR_PTR_TX 0xFFC0 2B00 SPORT1_CURR_PTR_TX 0xFFC0 2F00 UART0_CURR_PTR_RX 0xFFC0 1A00 UART1_CURR_PTR_RX 0xFFC0 1E00 UART0_CURR_PTR_TX 0xFFC0 1B00 UART1_CURR_PTR_TX 0xFFC0 1F00 USBD (N/A) ADSP-BF535 Blackfin Processor Hardware Reference 9-27...
Page 388: Peripheral Dma Irq Status Register
Table 9-11. Peripheral DMA Interrupt Status Register MMR Assignments Register Name Memory-Mapped Address SPI0_DMA_INT 0xFFC0 320E SPI1_DMA_INT 0xFFC0 360E SPORT0_IRQSTAT_RX 0xFFC0 2A0E SPORT1_IRQSTAT_RX 0xFFC0 2E0E SPORT0_IRQSTAT_TX 0xFFC0 2B0E SPORT1_IRQSTAT_RX 0xFFC0 2E0E UART0_IRQSTAT_RX 0xFFC0 1A0E UART1_IRQSTAT_RX 0xFFC0 1E0E UART0_IRQSTAT_TX 0xFFC0 1B0E 9-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 389 • The Interrupt on Error Enable bit is associated with peripheral spe- cific interrupts. • The Bus Error IRQ Status bit is non-maskable because of misalign- ment or illegal access. For conditions resulting in a peripheral specific interrupt, see the chapter that describes the peripheral. ADSP-BF535 Blackfin Processor Hardware Reference 9-29...
Page 390 UARTx TX UARTx_ UARTx_ UARTx_ UARTx_ UARTx_ UARTx_ UARTx_ UARTx_ CONFIG_ NEXT_ DESCR_ IRQSTAT_ CURR_ START_ START_ COUNT_ DESCR_ RDY_TX PTR_TX ADDR_ ADDR_ HI_TX LO_TX USBD_ USBD_ USBD_ USBD_ USBD_ DMACFG DMAIRQ DMABH DMABL DMACT 9-30 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 391: Memory Dma (Memdma)
It is preferable to activate interrupts on only one channel. This eliminates ambiguity when trying to identify the channel (either source or destina- tion) that requested the interrupt. ADSP-BF535 Blackfin Processor Hardware Reference 9-31...
Page 392: Memdma Control Registers
MemDMA control registers consist of source registers, used to read from memory, and destination registers, used to write to memory. This section shows destination registers first, then source registers. For descriptions of the registers, see the related DMA register. 9-32 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 393: Destination Memory Dma Configuration Register (Mdd_Dcfg)
1 - Clear buffer 0 - 16-bit half word or 32-bit word 1 - 8-bit byte Writable if autobuffer mode enabled (Shared with DMA Buffer Status bit) Figure 9-13. Destination Memory DMA Configuration Register ADSP-BF535 Blackfin Processor Hardware Reference 9-33...
Page 394: Destination Memory Dma Transfer Count Register (Mdd_Dct)
Count Register” on page 9-19. Destination Memory DMA Transfer Count (MDD_DCT) 15 14 13 12 11 10 0xFFC0 3808 Reset = 0x0000 DMA Block Transfer Count[15:0] Figure 9-14. Destination Memory DMA Transfer Count Register 9-34 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 395 Address High[31:16] Destination Memory DMA Start Address Low Register (MDD_DSAL) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 3806 Destination DMA Start Address Low [15:0] Figure 9-15. Destination Memory DMA Start Address Registers ADSP-BF535 Blackfin Processor Hardware Reference 9-35...
Page 396: Destination Memory Dma Next Descriptor Pointer
Destination Memory DMA Descriptor Ready Register (MDD_DDR) 15 14 13 12 11 10 0xFFC0 380C Reset = 0x0000 Reactivate Descriptor Pointer 1 - Reactivate Descriptor Pointer Figure 9-17. Destination Memory DMA Descriptor Ready Register 9-36 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 397: Register (Mdd_Dnd)
DMA Current Descriptor Pointer Register” on page 9-26. Destination Memory DMA Current Descriptor Pointer Register (MDD_DCP) 15 14 13 12 11 10 0xFFC0 3800 Reset = 0x0000 Current Descriptor Pointer[15:0] Figure 9-18. Destination Memory DMA Current Descriptor Pointer Register ADSP-BF535 Blackfin Processor Hardware Reference 9-37...
Page 398: Register (Mdd_Dcp)
DMA transfer sequence Interrupt on DMA Bus Error - W1C 1 - Bus error interrupt generated because of misaligned data or illegal memory access Figure 9-19. Destination Memory DMA Interrupt Register 9-38 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 399: Source Memory Dma Configuration Register
0 - 16-bit half word or 32-bit word 1 - Clear buffer 1 - 8-bit byte Writable if autobuffer mode enabled (Shared with DMA Buffer Status bit) Figure 9-20. Source Memory DMA Configuration Register ADSP-BF535 Blackfin Processor Hardware Reference 9-39...
Page 400: Source Memory Dma Transfer Count Register
Count Register” on page 9-19. Source Memory DMA Transfer Count Register (MDS_DCT) 15 14 13 12 11 10 0xFFC0 3908 Reset = 0x0000 DMA Block Transfer Count[12:0] Figure 9-21. Source Memory DMA Transfer Count Register 9-40 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 401: Source Memory Dma Start Address Registers
Address High [31:16] Source Memory DMA Start Address Low Register (MDS_DSAL) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 3906 Source DMA Start Address Low [15:0] Figure 9-22. Source Memory DMA Start Address Registers ADSP-BF535 Blackfin Processor Hardware Reference 9-41...
Page 402 Source Memory DMA Descriptor Ready Register (MDS_DDR) 15 14 13 12 11 10 0xFFC0 390C Reset = 0x0000 Reactivate Descriptor Pointer 1 - Reactivate Descriptor Pointer Figure 9-24. Source Memory DMA Descriptor Ready Register 9-42 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 403: Source Memory Dma Interrupt Register (Mds_Di)
1 - Interrupt generated at end of DMA transfer sequence Interrupt on DMA Bus Error 1 - Bus error interrupt generated because of misaligned data or illegal memory access Figure 9-26. Source Memory DMA Interrupt Register ADSP-BF535 Blackfin Processor Hardware Reference 9-43...
Page 404: Performance/Throughput For Memdma
• The processor clears the DMA Enable bit during active DMA processing. • The DMA channel does not relinquish the descriptor block back to the processor, nor does it write back error status information. No interrupt is generated. 9-44 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 405: Dma Bus Error Conditions
• The DMA channel relinquishes the descriptor block to the proces- sor and writes back error status. If enabled, an interrupt is generated. DMA Bus Error Conditions Two general conditions cause DMA bus error conditions: • Data misalignment • Illegal memory access ADSP-BF535 Blackfin Processor Hardware Reference 9-45...
Page 406: Data Misalignment
• The DMA Enable bit (bit 0 of the Configuration Word) is cleared. • The Bus Error interrupt is generated, and Bit 2 of the IRQ Status register is set. • The Configuration Word is not written back to the descriptor block. 9-46 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 407: Spi Compatible Port Controllers
• Other CPUs or microcontrollers • Codecs • A/D converters • D/A converters • Sample rate converters • SP/DIF or AES/EBU digital audio transmitters and receivers • LCD displays • Shift registers • FPGAs with SPI emulation ADSP-BF535 Blackfin Processor Hardware Reference 10-1...
Page 408 (shifted serially out of the shift register) as new data is received (shifted serially into the other end of the same shift register). The synchronizes the shifting and sampling of the data on the two serial data pins. 10-2 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 409 This must be enforced in broad- cast mode, where several slaves can be selected to receive data from the master, but only one slave at a time can be enabled to send data back to the master. ADSP-BF535 Blackfin Processor Hardware Reference 10-3...
Page 410: Interface Signals
The data is always shifted out on active edges of the clock MOSI and sampled on inactive edges of the clock. Clock polarity and clock phase relative to data are programmable in the SPIx Control register (SPIx_CTL) and define the transfer format. 10-4 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 411: Serial Peripheral Interface Slave Select Input Signal
MISO slave and shifted into the input pin of the master. MISO  Only one slave is allowed to transmit data at any given time. ADSP-BF535 Blackfin Processor Hardware Reference 10-5...
Page 412: Interrupt Behavior
An interrupt is also generated in a master when the mode fault error occurs. For more information about this interrupt output, see the discussion of bits in “SPIx Control Register (SPIx_CTL)” on page 10-8. TIMOD 10-6 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 413: Spi Registers
= (System clock frequency)/(2  • SCKx SPIx_BAUD Writing a value of 0 or 1 to the register disables the serial clock. There- fore, the maximum serial clock rate is one-fourth the system clock rate. ADSP-BF535 Blackfin Processor Hardware Reference 10-7...
Page 414: Spix Control Register (Spix_Ctl)
SPI system. This SPIx_CTL register is used to enable the SPI interface, select the device as a master or slave, and determine the data transfer format and word size. 10-8 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 415 0 - MISO disabled 1 - 16 bits 1 - MISO enabled Figure 10-4. SPIx Control Register Table 10-3. SPIx Control Register MMR Assignments Register Name Memory-Mapped Address SPI0_CTL 0xFFC0 3000 SPI1_CTL 0xFFC0 3400 ADSP-BF535 Blackfin Processor Hardware Reference 10-9...
Page 416: Spix Flag Register (Spix_Flg)
0 - SPIxSEL6 disabled SPIxSEL2 value 1 - SPIxSEL6 enabled FLG1 (Slave Select FLS7 (Slave Select Enable 7) Value 1) 0 - SPIxSEL7 disabled SPIxSEL1 value 1 - SPIxSEL7 enabled Figure 10-5. SPIx Flag Register 10-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 417 Clearing FLS1 SPI1_FLG drives low; setting drives high. The FLG1 SPI1_FLG FLG1 pin can be cycled high and low between transfers by setting and clearing . Otherwise, remains active (low) between FLG1 transfers. ADSP-BF535 Blackfin Processor Hardware Reference 10-11...
Page 418 PF10 FLS6 SPI0SEL6 Enable PF12 FLS7 SPI0SEL7 Enable PF14 Reserved FLG1 SPI0SEL1 Value FLG2 SPI0SEL2 Value FLG3 SPI0SEL3 Value FLG4 SPI0SEL4 Value FLG5 SPI0SEL5 Value PF10 FLG6 SPI0SEL6 Value PF12 FLG7 SPI0SEL7 Value PF14 10-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 419: Slave Select Inputs
PSSE = 1 SPISS Otherwise, is ignored. The state of these input pins can be observed SPISS in the Flag Clear register ( or the Flag Set register FIO_FLAG_C) FIO_FLAG_S ADSP-BF535 Blackfin Processor Hardware Reference 10-13...
Page 420: Multiple Slave Spi Systems
This feature may be available in some other microcontrollers. EMISO Therefore, it is possible to use the feature with any other SPI EMISO device that includes this functionality. 10-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 421: Spix Status Register (Spix_St)
. For example, if the bit is set, the user must write SPIx_ST a 1 to bit 2 of to clear the error condition. This allows the SPIx_ST user to read without changing its value. SPIx_ST ADSP-BF535 Blackfin Processor Hardware Reference 10-15...
Page 422 The receive buffer becomes full at the end of a transfer when the shift register value is loaded into the receive buffer. It becomes empty when the receive buffer is read. 10-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 423: Spix Transmit Data Buffer Register (Spix_Tdbr)
SPIx Transmit Data Buffer Register (SPIx_TDBR) For MMR 15 14 13 12 11 10 assignments, Reset = 0x0000 Table 10-8. Transmit Data Buffer Figure 10-8. SPIx Transmit Data Buffer Register ADSP-BF535 Blackfin Processor Hardware Reference 10-17...
Page 424: Spix Receive Data Buffer Register (Spix_Rdbr)
This register is at a different address than , but its contents are identical to that of . When SPIx_RDBR SPIx_RDBR a software read of occurs, the bit in is cleared and SPIx_RDBR SPIx_ST 10-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 425: Dma Registers
DATA SIZE BIT 1 INTERRUPT ENABLE writing to the Next Descriptor Pointer register, followed by a write to the DMA Configuration register. For more information about DMA, see “Direct Memory Access” on page 9-1. ADSP-BF535 Blackfin Processor Hardware Reference 10-19...
Page 426: Spix Dma Current Descriptor Pointer Register
Reset = 0x0000 Table 10-11. Current Descriptor Pointer Figure 10-11. SPIx DMA Current Descriptor Pointer Register Table 10-11. SPIx Current Descriptor Pointer Register MMR Assignments Register Name Memory-Mapped Address SPI0_CURR_PTR 0xFFC0 3200 SPI1_CURR_PTR 0xFFC0 3600 10-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 427: Spix Dma Configuration Register (Spix_Config)
Can be set following a DMA DERE (Interrupt on Error) - RO termination due to an error 0 - Disabled condition 1 - Enabled Writable if DAUTO = 1 Figure 10-12. SPIx DMA Configuration Register ADSP-BF535 Blackfin Processor Hardware Reference 10-21...
Page 428: Spix_Start_Addr_Hi) And Spix Dma Start Address Low Register (Spix_Start_Addr_Lo)
RW if DAUTO = 1 in SPIx_CONFIG 15 14 13 12 11 10 For MMR Reset = 0x0000 assignments, see Table 10-13. DMA Start Address[15:0] Figure 10-13. SPIx DMA Start Address High and Low Registers 10-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 429: Spix Dma Count Register (Spix_Count)
Reset = 0x0000 Table 10-14. DMA Block Transfer Count Figure 10-14. SPIx DMA Count Register Table 10-14. SPIx DMA Count Register MMR Assignments Register Name Memory-Mapped Address SPI0_COUNT 0xFFC0 3208 SPI1_COUNT 0xFFC0 3608 ADSP-BF535 Blackfin Processor Hardware Reference 10-23...
Page 430 Table 10-15. Reset = 0x0000 Next Descriptor Pointer[15:0] Figure 10-15. DMA Next Descriptor Pointer Register Table 10-15. SPIx Next Descriptor Pointer Register MMR Assignments Register Name Memory-Mapped Address SPI0_NEXT_DESCR 0xFFC0 320A SPI1_NEXT_DESCR 0xFFC0 360A 10-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 431: Spix Dma Descriptor Ready Register
Reset = 0x0000 Table 10-16. Reactivate Descriptor Fetch Figure 10-16. SPIx DMA Descriptor Ready Register Table 10-16. SPIx DMA Descriptor Ready Register MMR Assignments Register Name Memory-Mapped Address SPI0_DESCR_RDY 0xFFC0 320C SPI1_DESCR_RDY 0xFFC0 360C ADSP-BF535 Blackfin Processor Hardware Reference 10-25...
Page 432 Figure 10-17. SPIx DMA Interrupt Register Table 10-17. SPIx DMA Interrupt Register MMR Assignments Register Name Memory-Mapped Address SPI0_DMA_INT 0xFFC0 320E SPI1_DMA_INT 0xFFC0 360E Register Functions Table 10-18 shows the functions of the SPI registers. 10-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 433 Register can only be written to via software count when the DAUTO bit in SPIx_CONFIG is SPIx_NEXT_DESCR SPI port DMA next Register is concatenated with Next Descrip- descriptor pointer tor Base Pointer register to form head address ADSP-BF535 Blackfin Processor Hardware Reference 10-27...
Page 434: Spix_Descr_Rdy
The clock polarity and the clock phase should be identical for the master device and the slave device involved in the communication link. The transfer format from the master may be changed between transfers to adjust to various requirements of a slave device. 10-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 435 SIZE = 0 LSBF = 0. CL OCK CYCLE NUMBER SCK (CPOL=0) SCK (CPOL=1) MOSI (FROM MASTER) MISO (FROM SLAVE) SPISS (TO SLAVE) * = UNDEFINED Figure 10-18. SPI Transfer Protocol for CPHA = 0 ADSP-BF535 Blackfin Processor Hardware Reference 10-29...
Page 436: Spi General Operation
If MISO the transmit or receive is not needed, it can simply be ignored. This sec- tion describes the clock signals, SPI operation as a master and as a slave, and the error generation. 10-30 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 437: Clock Signals
When the SPI device is a master, is an output SPIx_BAUD signal. When the SPI is a slave, is an input signal. Slave devices ignore the serial clock if the slave select input is driven inactive (high). ADSP-BF535 Blackfin Processor Hardware Reference 10-31...
Page 438: Master Mode Operation
At the end of the transfer, the contents of the SPIx_TDBR shift register are loaded into SPIx_RDBR • With each new transfer initiate command, the SPI continues to send and receive words, according to the SPI transfer initiate mode. 10-32 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 439: Transfer Initiation From Master (Transfer Modes)
Read of SPIx_RDBR clears interrupt Transmit and Initiate new single-word trans- Interrupt active when transmit Receive fer upon write to SPIx_TDBR buffer is empty and previous transfer com- pleted Writing to SPIx_TDBR clears interrupt ADSP-BF535 Blackfin Processor Hardware Reference 10-33...
Page 440: Slave Mode Operation
SPISS the slave has received the proper number of clock cycles. • The slave device continues to receive/transmit with each new fall- ing edge transition on and/or active clock edge. SPISS 10-34 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 441: Slave Ready For A Transfer
Writing 1 to SPI_DMA_INT clears interrupt Reserved Error Signals and Flags The status of a device is indicated by the register. See “SPIx Sta- SPIx_ST tus Register (SPIx_ST)” on page 10-15 for more information. ADSP-BF535 Blackfin Processor Hardware Reference 10-35...
Page 442: Mode Fault Error (Modf)
ADSP-BF535 processor. To ensure that the slave select output drivers are disabled once a error occurs, the program must configure the pro- MODF grammable flag registers appropriately. 10-36 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 443: Transmission Error (Txe)
The bit is sticky (W1C). TXCOL  bit is never set when the SPI is configured as a slave with TXCOL . A collision may occur, but it cannot be detected. CPHA = 0 ADSP-BF535 Blackfin Processor Hardware Reference 10-37...
Page 444: Beginning And Ending An Spi Transfer
In general, SPIF is set after , but at the lowest baud rate settings ( SPIF SPIx_BAUD < 4 is set before is set, and consequently before new data is latched SPIF 10-38 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 445 , because of the latency. Therefore, for SPIx_RDBR SPIx_BAUD = 2 must be set before to read . For larger SPIx_BAUD = 3 SPIF SPIx_RDBR settings, is guaranteed to be set before is set. SPIx_BAUD SPIF ADSP-BF535 Blackfin Processor Hardware Reference 10-39...
Page 446 Beginning and Ending an SPI Transfer 10-40 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 447: 11 Serial Port Controllers
The SPORTs use frame sync pulses to indicate the beginning of each word or packet, and the bit clock marks the beginning of each data bit. External bit clock and frame sync are available for the buffers. ADSP-BF535 Blackfin Processor Hardware Reference 11-1...
Page 448 (See “Companding” on page 11-52 for more information.) • Internally generates serial clock and frame sync signals in a wide range of frequencies or accepts clock and frame sync input from an external source. 11-2 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 449 Table 11-1 shows the pins for each SPORT. Table 11-1. Serial Port (SPORT) Pins Description Transmit Data Receive Data TCLKx Transmit Clock RCLKx Receive Clock TFSx Transmit Frame Sync RFSx Receive Frame Sync ADSP-BF535 Blackfin Processor Hardware Reference 11-3...
Page 450 When an entire word is received, the data is optionally expanded, then automatically transferred to the SPORT’s memory-mapped register, where it is available to the processor. SPORTx_RX 11-4 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 451 S C L K G e n e r a to r R F S S C L K T F S T C L K R C L K Figure 11-1. SPORT Block Diagram ADSP-BF535 Blackfin Processor Hardware Reference 11-5...
Page 452: Sport Operation
The bits are then sent, beginning with either the MSB or the LSB as specified. Each bit is shifted out on the rising edge of . After the first bit of a word has been trans- 11-6 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 453: Sport Disable
The SPORTs are ready to start transmitting or receiving data three serial clock cycles after they are enabled in the SPORTx_TX_CONFIG control register. No serial clock cycles are lost from this SPORTx_RX_CONFIG point on. ADSP-BF535 Blackfin Processor Hardware Reference 11-7...
Page 454: Setting Sport Modes
SPORT is disabled ( ). Changes take effect after the TSPEN/RSPEN=0 SPORT is re-enabled. The only exceptions to this rule are the registers and multichannel configuration TSCLKDIV/RSCLKDIV registers. SPORT Registers The following sections describe the SPORT registers. 11-8 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 455: Transmit And Receive Configuration Registers
(the default), the internal transmit frame sync signal ( DITFS is dependent upon new data being present in the buffer; the SPORTx_TX signal is only generated for new data. Setting to 1 selects data DITFS ADSP-BF535 Blackfin Processor Hardware Reference 11-9...
Page 456 ITFS (Internal Transmit 0001 - Illegal value Frame Sync Select) Serial word length is value in 0 - External TFS used this field plus 1 1 - Internal TFS used Figure 11-3. SPORTx Transmit Configuration Register 11-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 457 (00=right justify and zero fill unused most significant bits, 01=right justify and sign extend into unused most significant bits, 10=compand using -law, 11=compand using A-law). ADSP-BF535 Blackfin Processor Hardware Reference 11-11...
Page 458 (if cleared). • Transmit Frame Sync Required Select. SPORTx_TX_CONFIG[10] ). This bit selects whether the SPORT requires (if set) or does TFSR not require (if cleared) a transfer frame sync for every data word. 11-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 459 If set, data and inter- nally generated frame syncs are driven on the falling edge and externally generated frame syncs are sampled on the rising edge. ADSP-BF535 Blackfin Processor Hardware Reference 11-13...
Page 460 Serial word length is value in this field plus 1 Figure 11-4. SPORTx Receive Configuration Register Table 11-3. SPORTx Receive Configuration Register MMR Assignments Register Name Memory-Mapped Address SPORT0_RX_CONFIG 0xFFC0 2802 SPORT1_RX_CONFIG 0xFFC0 2C02 11-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 461 DTYPE , and bits configure the format of the data DTYPE SENDN SLEN words received over the SPORTs. The two bits specify one DTYPE of four data formats used for single and multichannel operation ADSP-BF535 Blackfin Processor Hardware Reference 11-15...
Page 462 SPORT RCLK uses for sampling data, for sampling externally generated frame syncs, and for driving internally generated frame syncs. If set, inter- nally generated frame syncs are driven on the falling edge, and data 11-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 463: Sportx Transmit (Sportx_Tx) Registers
SPORT is re-enabled (dis- abled and then enabled again). Once the SPORT is enabled, it takes at least 4 transmit clock cycles to clear the bit. TUVF ADSP-BF535 Blackfin Processor Hardware Reference 11-17...
Page 464 SPORT is enabled. SPORTx_TX SPORTx Transmit Registers (SPORTx_TX) For MMR 15 14 13 12 11 10 assignments, see Reset = 0x0000 Table 11-4. Transmit Data[15:0] Figure 11-5. SPORTx Transmit Registers 11-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 465: Sportx Receive (Sportx_Rx) Registers
SPORTx_RX error, the register’s full or empty status should be read first (in the SPORT Status register) to determine if the access can be made. ADSP-BF535 Blackfin Processor Hardware Reference 11-19...
Page 466: Sportx Transmit (Sportx_Tsclkdiv) And Receive (Sportx_Rsclkdiv) Serial Clock Divider Registers
(as determined by , and ) and the value of the SSEL MSEL 16-bit serial clock divide modulus registers: SPORTx_TSCLKDIV . These registers are shown in Figure 11-7 SPORTx_RSCLKDIV Figure 11-8, respectively. 11-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 467 Table 11-7. Serial Clock Divide Modulus[15:0] Figure 11-8. SPORTx Receive Serial Clock Divider Register Table 11-7. SPORTx Receive Serial Clock Divider Register MMR Assignments Register Name Memory-Mapped Address SPORT0_RSCLKDIV 0xFFC0 280A SPORT1_RSCLKDIV 0xFFC0 2C0A ADSP-BF535 Blackfin Processor Hardware Reference 11-21...
Page 468: Sportx Transmit (Sportx_Tfsdiv) And Receive (Sportx_Rfsdiv) Frame Sync Divider Registers
TFS pulse Figure 11-9. SPORTx Transmit Frame Sync Divider Register Table 11-8. SPORTx Transmit Frame Sync Divider Register MMR Assignments Register Name Memory-Mapped Address SPORT0_TFSDIV 0xFFC0 280C SPORT1_TFSDIV 0xFFC0 2C0C 11-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 469: Sportx Status (Sportx_Stat) Registers
TUVF ter when a transmit frame sync occurs and no new data has been loaded into the register. The status bit is sticky and is only SPORTx_TX TUVF cleared by disabling the serial port. ADSP-BF535 Blackfin Processor Hardware Reference 11-23...
Page 470 0 - Disabled Status) 1 - Enabled 0 - Disabled RXS (Receive Status) 1 - Enabled 0 - Empty 1 - Full TXS (Transmit Status) 0 - Empty 1 - Full Figure 11-11. SPORTx Status Register 11-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 471: Sportx Multichannel Transmit Select (Sportx_Mtcsx)
16 channels. Setting a bit enables that channel so that the serial port selects that word for transmit from the multiple word block of data. For example, setting bit 0 selects word 0, setting bit 12 selects word 12, and so on. ADSP-BF535 Blackfin Processor Hardware Reference 11-25...
Page 472 0xFFC0 2816 SPORT1_MTCS2 0xFFC0 2C16 SPORT0_MTCS3 0xFFC0 2818 SPORT1_MTCS3 0xFFC0 2C18 SPORT0_MTCS4 0xFFC0 281A SPORT1_MTCS4 0xFFC0 2C1A SPORT0_MTCS5 0xFFC0 281C SPORT1_MTCS5 0xFFC0 2C1C SPORT0_MTCS6 0xFFC0 281E SPORT1_MTCS6 0xFFC0 2C1E SPORT0_MTCS7 0xFFC0 2820 SPORT1_MTCS7 0xFFC0 2C20 11-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 473: Sportx Multichannel Receive Select (Sportx_Mrcsx Registers
Clearing the bit in the register causes the serial port to ignore the data. SPORTx_MRCSx ADSP-BF535 Blackfin Processor Hardware Reference 11-27...
Page 474 0xFFC0 2826 SPORT1_MRCS2 0xFFC0 2C26 SPORT0_MRCS3 0xFFC0 2828 SPORT1_MRCS3 0xFFC0 2C28 SPORT0_MRCS4 0xFFC0 282A SPORT1_MRCS4 0xFFC0 2C2A SPORT0_MRCS5 0xFFC0 282C SPORT1_MRCS5 0xFFC0 2C2C SPORT0_MRCS6 0xFFC0 282E SPORT1_MRCS6 0xFFC0 2C2E SPORT0_MRCS7 0xFFC0 2830 SPORT1_MRCS7 0xFFC0 2C30 11-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 475: Sportx Multichannel Configuration (Sportx_Mcmcx)
Frame Delay) Other value 8 to 128 in incre- ments of 8 - window size Delay between frame sync pulse and first data bit in multichannel mode Figure 11-14. SPORTx Multichannel Configuration 1 Registers ADSP-BF535 Blackfin Processor Hardware Reference 11-29...
Page 476 DMA Receive Packing) 0 - Disabled 1 - Enabled Figure 11-15. SPORTx Multichannel Configuration 2 Registers Table 11-14. SPORTx Multichannel Configuration 2 Register MMR Assignments Register Name Memory-Mapped Address SPORT0_MCMC2 0xFFC0 2834 SPORT1_MCMC2 0xFFC0 2C34 11-30 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 477: Registers
During SPORT initialization, the program can write the head address of the first DMA descriptor block to the Receive DMA Next Descriptor Pointer register and then set the DMA Enable bit in the Receive DMA ADSP-BF535 Blackfin Processor Hardware Reference 11-31...
Page 478 When the current descriptor work block completes (DMA count = 0), the value of this bit is written to memory as a record of the completion result, and the bit is cleared for the next data transfer. 11-32 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 479 0 - Normal buffer operation 1 - Clear buffer Figure 11-17. SPORTx Receive DMA Configuration Registers Table 11-16. SPORTx Receive DMA Configuration Register MMR Assignments Register Name Memory-Mapped Address SPORT0_CONFIG_DMA_RX 0xFFC0 2A02 SPORT1_CONFIG_DMA_RX 0xFFC0 2E02 ADSP-BF535 Blackfin Processor Hardware Reference 11-33...
Page 480: Sportx Receive Dma Start Address High
DMA Start Address [31:16] Figure 11-18. SPORTx Receive DMA Start Address High Registers Table 11-17. SPORTx Receive DMA Start Address High Register MMR Assignments Register Name Memory-Mapped Address SPORT0_START_ADDR_HI_RX 0xFFC0 2A04 SPORT1_START_ADDR_HI_RX 0xFFC0 2E04 11-34 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 481: Sportx Receive Dma Start Address Low
It is a read-only register. It can be written in autobuffer mode. Together, form the 32-bit SPORTx_START_ADDR_HI_RX SPORTx_START_ADDR_LO_RX address for data access. Table 11-18. SPORTx Receive DMA Start Address Low Register MMR Assignments Register Name Memory-Mapped Address SPORT0_START_ADDR_LO_RX 0xFFC0 2A06 SPORT1_START_ADDR_LO_RX 0xFFC0 2E06 ADSP-BF535 Blackfin Processor Hardware Reference 11-35...
Page 482: Sportx Receive Dma Count (Sportx_Count_Rx)
SPORT initialization, the programmer writes the head address of the first DMA descriptor block to the Receive DMA Next Descriptor Pointer reg- ister and then sets the bit in the Transmit or Receive DMA Configuration Registers. 11-36 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 483: Sportx Receive Dma Descriptor Ready (Sportx_Descr_Rdy_Rx) Registers
The DMA engine stalls if a low level ownership bit is detected during a descriptor block access. Writing a 1 to bit 0 of the SPORT Receive DMA Descriptor Ready register reactivates the processing of the descriptor ADSP-BF535 Blackfin Processor Hardware Reference 11-37...
Page 484: Sportx Receive Dma Irq Status (Sportx_Irqstat_Rx) Registers
Interrupt On Error and Interrupt On Completion bits within the configuration register. The third SPORTx_CONFIG_DMA_RX source, bus error, is not maskable at the DMA level. All three interrupt status bits contained within the register are sticky. SPORTx_IRQSTAT_RX 11-38 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 485 0 - Inactive 1 - Bus error Figure 11-23. SPORTx Receive DMA IRQ Status Registers Table 11-22. SPORTx Receive DMA IRQ Status Register MMR Assignments Register Name Memory-Mapped Address SPORT0_IRQSTAT_RX 0xFFC0 2A0E SPORT1_IRQSTAT_RX 0xFFC0 2E0E ADSP-BF535 Blackfin Processor Hardware Reference 11-39...
Page 486: Sportx Transmit Dma Current Descriptor Pointer (Sportx_Curr_Ptr_Tx) Registers
During SPORT initialization, the program can write the head address of the first DMA descriptor block to the Transmit DMA Next Descriptor Pointer register, shown in Figure 11-29 on page 11-46, and then set the 11-40 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 487 DMA interrupt SPORTx_IRQSTAT_TX being generated. The Transmit Underflow Error bit is set if an underflow condition occurs. This bit is sticky only during the current work block. It is cleared on the next descriptor fetch. ADSP-BF535 Blackfin Processor Hardware Reference 11-41...
Page 488: Data Transfer
1 - Autobuffer mode enabled 0 - Disabled 1 - Enabled FLSH (Buffer Clear Enable) - RW Writable if DAUTO = 1 0 - Normal buffer operation 1 - Clear buffer Figure 11-25. SPORTx Transmit DMA Configuration Registers 11-42 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 489: Sportx Transmit Dma Start Address High (Sportx_Start_Addr_Hi_Tx) Registers
11-25. DMA Start Address[31:16] Figure 11-26. SPORTx Transmit DMA Start Address High Registers Table 11-25. SPORTx Transmit DMA Start Address High Register MMR Assignments Register Name Memory-Mapped Address SPORT0_START_ADDR_HI_TX 0xFFC0 2B04 SPORT1_START_ADDR_HI_TX 0xFFC0 2F04 ADSP-BF535 Blackfin Processor Hardware Reference 11-43...
Page 490: Sportx Transmit Dma Start Address Low (Sportx_Start_Addr_Lo_Tx) Registers
It is a read-only register. It can be written in autobuffer mode. Together, form the 32-bit SPORTx_START_ADDR_HI_TX SPORTx_START_ADDR_LO_TX address for data access. Table 11-26. SPORTx Transmit DMA Start Address Low Register MMR Assignments Register Name Memory-Mapped Address SPORT0_START_ADDR_LO_TX 0xFFC0 2B06 SPORT1_START_ADDR_LO_TX 0xFFC0 2F06 11-44 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 491: Sportx Transmit Dma Count (Sportx_Count_Tx)
SPORT initialization, the programmer writes the head address of the first DMA descriptor block to the Transmit DMA Next Descriptor Pointer register and then sets the bit in the Transmit or Receive DMA Config- uration Registers. ADSP-BF535 Blackfin Processor Hardware Reference 11-45...
Page 492: Sportx Transmit Dma Descriptor Ready
The DMA engine stalls if a low level ownership bit is detected during a descriptor block access. Writing a 1 to bit 0 of the SPORT Transmit DMA Descriptor Ready register reactivates the processing of the descrip- 11-46 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 493: Sportx Transmit Dma Irq Status
Interrupt On Error and Interrupt On Completion bits within the configuration register. The third SPORTx_CONFIG_DMA_TX source, bus error, is not maskable at the DMA level. All three interrupt status bits contained within the register are sticky. SPORTx_IRQSTAT_TX ADSP-BF535 Blackfin Processor Hardware Reference 11-47...
Page 494: Register Writes And Effect Latency
SPORT register TSPEN RSPEN writes are internally completed at the end of the next cycle after SCLK which they occurred and the register reads back the newly written value on the next cycle after that. 11-48 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 495: Clock And Frame Sync Frequencies
The formula for the number of cycles between frame sync pulses is: # of serial clocks between frame sync assertions = xFSDIV + 1 ADSP-BF535 Blackfin Processor Hardware Reference 11-49...
Page 496: Maximum Clock Rate Restrictions
Maximum Clock Rate Restrictions Externally generated late transmit frame syncs also experience a delay from arrival to data output, and this can limit the maximum serial clock speed. See ADSP-BF535 Blackfin Embedded Processor Data Sheet for exact timing specifications. ...
Page 497: Data Word Formats
(MSB) first or least significant bit (LSB) first. Endian format is selected by the bit in the SENDN SPORTx_TX_CONFIG registers. When , serial words are transmitted SPORTx_RX_CONFIG SENDN (or received) MSB first. When , serial words are transmitted (or SENDN received) LSB first. ADSP-BF535 Blackfin Processor Hardware Reference 11-51...
Page 498: Data Type
The ADSP-BF535 processor’s SPORTs  support the two most widely used companding algorithms, -law and A-law. The processor compands data according to the CCITT G.711 specification. The type of companding can be selected independently for each SPORT. 11-52 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 499: Clock Signal Options
, the clock signal is accepted as an input on the ICLK TCLK RCLK pins, and the serial clock divisors in the registers are ignored. The externally SPORTx_TSCLKDIV SPORTx_RSCLKDIV generated serial clock need not be synchronous with the core system clock. ADSP-BF535 Blackfin Processor Hardware Reference 11-53...
Page 500: Frame Sync Options
 When DMA is enabled in this mode, with frame syncs not required, DMA requests may be held off by chaining or may not be serviced frequently enough to guarantee continuous unframed data flow. 11-54 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 501: Internal Versus External Frame Syncs
Internal Versus External Frame Syncs Both transmit and receive frame syncs can be independently generated internally or can be input from an external source. The bits ITFS IRFS of the registers determine the SPORTx_TX_CONFIG SPORTx_RX_CONFIG frame sync source. ADSP-BF535 Blackfin Processor Hardware Reference 11-55...
Page 502: Active Low Versus Active High Frame Syncs
Data and frame syncs can be sampled on either the rising or falling edges of the SPORT clock signals. The bit of the CKFE SPORTx_TX_CONFIG registers selects the driving and sampling edges for the SPORTx_RX_CONFIG serial data and frame syncs. 11-56 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 503: Early Versus Late Frame Syncs (Normal Versus Alternate Timing)
Frame sync signals can occur during the first bit of each data word (late) or during the serial clock cycle immediately preceding the first bit (early). bits of the LATFS LARFS SPORTx_TX_CONFIG SPORTx_RX_CONFIG registers configure this option. ADSP-BF535 Blackfin Processor Hardware Reference 11-57...
Page 504 LARFS is used for late frame syncs. LATFS=1 LARFS • With early framing, the frame sync precedes data by one cycle. With late framing, the frame sync is checked on the first bit only. 11-58 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 505: Data Independent Transmit Frame Sync
When , the internally generated is output at its programmed DITFS interval regardless of whether new data is available in the buf- SPORTx_TX fer. Whatever data is present in is retransmitted with each SPORTx_TX ADSP-BF535 Blackfin Processor Hardware Reference 11-59...
Page 506: Multichannel Operation
128 channels. In other words, the SPORT can do any of these on each channel: • transmit data • receive data • transmit and receive data • do nothing Data companding and DMA transfers can also be used in multichannel mode. 11-60 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 507 • Can independently select transmit and receive channels. • signals start of frame. • is used as “Transmit Data Valid” for external logic, true only during transmit channels. “Timing Examples” on page 11-69 for more timing examples. ADSP-BF535 Blackfin Processor Hardware Reference 11-61...
Page 508: Frame Syncs In Multichannel Mode
SPORTx_TX SPORTx_RX SPORT in MCM configuration, both configuration registers SPORTx_RX should always be programmed the same way as the configura- SPORTx_TX tion register, even if operation is not enabled. SPORTx_RX 11-62 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 509: Multichannel Frame Delay
The maximum value allowed for is 15. A new frame sync may occur before data from the last frame has been received, because blocks of data occur back-to-back. ADSP-BF535 Blackfin Processor Hardware Reference 11-63...
Page 510: Window Size
The total number of channels in the frame is calculated by adding the window size to the window offset. 11-64 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 511: Channel Selection Registers
A channel is a multibit word from 3 to 16 bits in length that belongs to one of the TDM channels. Specific channels can be individually enabled or disabled to select which words are received and transmitted during mul- tichannel communications. Data words from the enabled channels are ADSP-BF535 Blackfin Processor Hardware Reference 11-65...
Page 512: Multichannel Enable
Multichannel Enable Setting the bit in the multichannel mode configuration control regis- ter 1 enables multichannel mode. When , multichannel operation is MCM=1 enabled; when , all multichannel operations are disabled. MCM=0 11-66 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 513: Multichannel Dma Data Packing
1 and 10 of the buffer, and the rest of the words in the DMA buffer would be ignored. This mode has no restrictions on changing the number of enabled channels while the SPORT is enabled. ADSP-BF535 Blackfin Processor Hardware Reference 11-67...
Page 514: Moving Data Between Sports And Memory
122 ns wide, 125 s period frame sync) • set (FS required) TFSR/RFSR • set (active low FS) LTFS/LRFS • = 8 (for 8.192 MHz (+/- 2%) bit clock) TSCLKDIV RSCLKDIV • set (multichannel mode selected) 11-68 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 515: 2X Clock Recovery Control
“Early Versus Late Frame Syncs (Normal Versus Alternate Timing)” on page 11-57, and “Frame Syncs In Multichannel Mode” on page 11-62). This section con- tains additional examples to illustrate more possible combinations of the framing options. ADSP-BF535 Blackfin Processor Hardware Reference 11-69...
Page 516 These timing examples show the relationships between the signals but are not scaled to show the actual timing parameters of the processor. Consult the ADSP-BF535 Blackfin Embedded Processor Data Sheet for actual timing parameters and values. These examples assume a word length of four bits ( ).
Page 517 Figure 11-35. SPORT Receive, Normal Framing SC K OU TPUT RFS IN PUT SPORT Control Register: Both Inter nal Framing Option and Externa l Framing Opti on Shown Figure 11-36. SPORT Continuous Receive, Normal Framing ADSP-BF535 Blackfin Processor Hardware Reference 11-71...
Page 518 RFS I NPUT SPORT Control R egister: Both Interna l Framing Option and Ex ternal Frami ng Option Shown Figure 11-38. SPORT Continuous Receive, Alternate Framing Figure 11-39. SPORT Receive, Unframed Mode, Normal Framing 11-72 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 519 Figure 11-41. SPORT Transmit, Normal Framing OUTPU T TFS INP UT S PORT Control Registe r: Both Inter nal Fr aming Option and Externa l Fra ming Option Shown Figure 11-42. SPORT Continuous Transmit, Normal Framing ADSP-BF535 Blackfin Processor Hardware Reference 11-73...
Page 520 Note: The re is an asynchronous delay be tween TFS i nput and DT. See the appro- priate datasheet for specificati ons. Figure 11-44. SPORT Continuous Transmit, Alternate Framing Figure 11-45. SPORT Transmit, Unframed Mode, Normal Framing 11-74 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 521 Serial Port Controllers Note: There is an asynchronous delay between TFS input and DT. See the appropriate datasheet for specifications. Figure 11-46. SPORT Transmit, Unframed Mode, Alternate Framing ADSP-BF535 Blackfin Processor Hardware Reference 11-75...
Page 522 Timing Examples 11-76 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 523: 12 Uart Port Controller
See Chapter 9, “Direct Memory Access” for more information on DMA. Timers 0, 1, and 2 can be used to provide a hardware assisted autobaud detection mechanism for use with the UART. See “Timers” on page 16-1 for more information. ADSP-BF535 Blackfin Processor Hardware Reference 12-1...
Page 524: Serial Communications
The ADSP-BF535 processor provides a set of PC-style industry standard control and status registers for each UART. These MMRs are byte-wide registers that are accessed as 16-bit words with the most significant byte zero filled. 12-2 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 525: Uartx Line Control Registers (Uartx_Lcr)
EPS = 0, parity transmitted and checked as 1 0 - Parity not transmitted or checked EPS (Even Parity Select) 1 - Even parity 0 - Odd parity when PEN = 1 and SP = 0 Figure 12-2. UARTx Line Control Registers ADSP-BF535 Blackfin Processor Hardware Reference 12-3...
Page 526: Uartx Line Status Registers (Uartx_Lsr)
0 - No error 1 - Invalid stop bit error Figure 12-3. UARTx Line Status Registers Table 12-2. UARTx Line Status Register MMR Assignments Register Name Memory-Mapped Address UART0_LSR 0xFFC0 180A UART1_LSR 0xFFC0 1C0A 12-4 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 527: Uartx Transmit Holding Registers (Uartx_Thr)
Note that data is transmitted and received least significant bit first (bit 0) followed by the most significant bits. UARTx Transmit Holding Registers (UARTx_THR) For MMR assignments, Reset = 0x00 Table 12-3. Transmit Hold[7:0] Figure 12-4. UARTx Transmit Holding Registers ADSP-BF535 Blackfin Processor Hardware Reference 12-5...
Page 528: Uartx Receive Buffer Registers (Uartx_Rbr)
, the bit in must be UARTx_DLL UARTx_RBR DLAB UARTx_LCR cleared. When the bit is cleared, writes to this address target the DLAB register, while reads from this address return the UARTx_THR UARTx_RBR register. 12-6 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 529: Uartx Interrupt Enable Registers (Uartx_Ier)
Interrupt Service Routine (ISR) evaluates the register to deter- UARTx_IIR mine the signaling interrupt source. register is mapped to the same address as . To UARTx_IER UARTx_DLH access , the bit in must be cleared. UARTx_IER DLAB UARTx_LCR ADSP-BF535 Blackfin Processor Hardware Reference 12-7...
Page 530 ELSI ditions are raised by the respective bit in the UARTx Line Status register UARTx_LSR • Receive Overrun Error ( • Receive Parity Error ( • Receive Framing Error ( • Break Interrupt ( 12-8 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 531: Uartx Interrupt Identification Registers (Uartx_Iir)
UARTx_IER When cleared, the Pending Interrupt bit ( ) signals that an interrupt is NINT pending. The field indicates the highest priority pending interrupt STATUS (see Figure 12-7). ADSP-BF535 Blackfin Processor Hardware Reference 12-9...
Page 532: Uartx Divisor Latch Registers
UARTx_DLH shown in Figure 12-8. These registers form a 16-bit divisor. The baud clock is divided by 16 so that:  BAUD RATE = SCLK/(16 Divisor) when Divisor = 65,536 UARTx_DLL UARTx_DLH = 0 12-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 533 Table 12-7. UARTx Divisor Latch Low Byte Register MMR Assignments Register Name Memory-Mapped Address UART0_DLL 0xFFC0 1800 UART1_DLL 0xFFC0 1C00 Table 12-8. UARTx Divisor Latch High Byte Register MMR Assignments Register Name Memory-Mapped Address UART0_DLH 0xFFC0 1802 UART1_DLH 0xFFC0 1C02 ADSP-BF535 Blackfin Processor Hardware Reference 12-11...
Page 534 Receive Shift register ( ), so the input is directly connected to the Transmit Shift register ( ) output. When Loopback mode is enabled, modem control signals in the UARTx Modem Control Register 12-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 535: Uartx Modem Control Registers (Uartx_Mcr)
1 - Loopback enabled OUT1 (General-purpose Output Function) OUT2 (General-purpose Output Function) Figure 12-9. UARTx Modem Control Registers Table 12-10. UARTx Modem Control Register MMR Assignments Register Name Memory-Mapped Address UART0_MCR 0xFFC0 1808 UART1_MCR 0xFFC0 1C08 ADSP-BF535 Blackfin Processor Hardware Reference 12-13...
Page 536: Uartx Modem Status Registers (Uartx_Msr)
UARTx_MSR last read 1 - DCD changed state since UARTx_MSR last read Figure 12-10. UARTx Modem Status Registers Table 12-11. UARTx Modem Status Register MMR Assignments Register Name Memory-Mapped Address UART0_MSR 0xFFC0 180C UART1_MSR 0xFFC0 1C0C 12-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 537: Non-Dma Mode
The ADSP-BF535 processor must write and read one character at time. To prevent any loss of data and misalignments of the serial data stream, the UARTx Line Status Register ( ) provides two status flags for UARTx_LSR handshaking: THRE ADSP-BF535 Blackfin Processor Hardware Reference 12-15...
Page 538 The ISR can evaluate the Status bit field within the UARTx Interrupt Identification register ( ) to determine the exact interrupt UARTx_IIR source. Interrupts also must be assigned and unmasked by the ADSP-BF535 processor’s interrupt controller. 12-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 539: Dma Mode
. Other- THRE TEMT UARTx_LSR wise, the processor must wait until the 2-bit DMA Buffer Status field within the appropriate UARTx Transmit DMA Configuration register ) is clear. UARTx_CONFIG_TX ADSP-BF535 Blackfin Processor Hardware Reference 12-17...
Page 540: Uart Dma Receive Registers
DMA channels. The transmit channel reads from memory and the receive channel writes to memory. Every DMA channel features its own set of control registers. For more information on DMA registers, see “Direct Memory Access” on page 9-1. 12-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 541: Uartx Receive Dma Current Descriptor Pointer Registers
Pointer. The complete 32-bit address is created by combining this value with the upper 16 bits from the DMA Descriptor Base Pointer Register ( ). For more information on the DMA DMA_DBP Descriptor Base Pointer Register, see “Direct Memory Access” on page 9-1. ADSP-BF535 Blackfin Processor Hardware Reference 12-19...
Page 542: Uartx Receive Dma Configuration Registers (Uartx_Config_Rx)
1 - Parity error 1 - Generate interrupt This bit is writable if autobuffering UAROE - RO mode is enabled. 0 - No error 1 - Overrun error Figure 12-13. UARTx Receive DMA Configuration Registers 12-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 543 UART’s interrupt request. Since UARTx_LSR the error request has also been latched in the DMA engine, the error handler must also write a 1 to bit 1 of the UARTx_IRQSTAT_RX afterward. ADSP-BF535 Blackfin Processor Hardware Reference 12-21...
Page 544: Uartx Receive Dma Start Address High Registers
12-16. DMA Start Address[31:16] Figure 12-14. UARTx Receive DMA Start Address High Registers Table 12-16. UARTx Receive DMA Start Address High Register MMR Assignments Register Name Memory-Mapped Address UART0_START_ADDR_HI_RX 0xFFC0 1A04 UART1_START_ADDR_HI_RX 0xFFC0 1E04 12-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 545: Uartx Receive Dma Start Address Low Registers
12-17. DMA Start Address[15:0] Figure 12-15. UARTx Receive DMA Start Address Low Registers Table 12-17. UARTx Receive DMA Start Address Low Register MMR Assignments Register Name Memory-Mapped Address UART0_START_ADDR_LO_RX 0xFFC0 1A06 UART1_START_ADDR_LO_RX 0xFFC0 1E06 ADSP-BF535 Blackfin Processor Hardware Reference 12-23...
Page 546: Uartx Receive Dma Count Registers
For MMR assignments, Reset 0x0000 Table 12-18. DMA Transfer Count[15:0] Figure 12-16. UARTx Receive DMA Count Registers Table 12-18. UARTx Receive DMA Count Register MMR Assignments Register Name Memory-Mapped Address UART0_COUNT_RX 0xFFC0 1A08 UART1_COUNT_RX 0xFFC0 1E08 12-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 547: Uartx Receive Dma Next Descriptor Pointer Registers
Pointer. The complete 32-bit address is created by combining this value with the upper 16 bits from the DMA Descriptor Base Pointer Register ( ). For more information on the DMA DMA_DBP Descriptor Base Pointer Register, see “Direct Memory Access” on page 9-1. ADSP-BF535 Blackfin Processor Hardware Reference 12-25...
Page 548: Uartx Receive Dma Descriptor Ready Registers
0 - Not ready 1 - Ready Figure 12-18. UARTx Receive DMA Descriptor Ready Registers Table 12-20. UARTx Receive DMA Descriptor Ready Register MMR Assignments Register Name Memory-Mapped Address UART0_DESCR_RDY_RX 0xFFC0 1A0C UART1_DESCR_RDY_RX 0xFFC0 1E0C 12-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 549: Uartx Receive Dma Irq Status Registers
Table 12-21. UARTx Receive DMA IRQ Status Register MMR Assignments Register Name Memory-Mapped Address UART0_IRQSTAT_RX 0xFFC0 1A0E UART1_IRQSTAT_RX 0xFFC0 1E0E UART DMA Transmit Registers For more information on DMA registers, see “Direct Memory Access” on page 9-1. ADSP-BF535 Blackfin Processor Hardware Reference 12-27...
Page 550: Uartx Transmit Dma Current Descriptor Pointer Registers
Pointer. The complete 32-bit address is created by combining this value with the upper 16 bits from the DMA Descriptor Base Pointer Register ( ). For more information on the DMA DMA_DBP Descriptor Base Pointer Register, see “Direct Memory Access” on page 9-1. 12-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 551: Uartx Transmit Dma Configuration Registers
This bit is writable if autobuffering mode is enabled. Figure 12-21. UARTx Transmit DMA Configuration Registers Table 12-23. UARTx Transmit DMA Configuration Register MMR Assignments Register Name Memory-Mapped Address UART0_CONFIG_TX 0xFFC0 1B02 UART1_CONFIG_TX 0xFFC0 1F02 ADSP-BF535 Blackfin Processor Hardware Reference 12-29...
Page 552: Uartx Transmit Dma Start Address High Registers
UARTx Transmit DMA Start Address High Registers (UARTx_START_ADDR_HI_TX) Writable if autobuffering mode is enabled, otherwise RO. 15 14 13 12 11 10 For MMR assignments, Reset 0x0000 Table 12-25. DMA Start Address[31:16] Figure 12-22. UARTx Transmit DMA Start Address High Registers 12-30 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 553: Uartx Transmit Dma Start Address Low Registers
12-26. DMA Start Address[15:0] Figure 12-23. UARTx Transmit DMA Start Address Low Registers Table 12-26. UARTx Transmit DMA Start Address Low Register MMR Assignments Register Name Memory-Mapped Address UART0_START_ADDR_LO_TX 0xFFC0 1B06 UART1_START_ADDR_LO_TX 0xFFC0 1F06 ADSP-BF535 Blackfin Processor Hardware Reference 12-31...
Page 554: Uartx Transmit Dma Count Registers
For MMR assignments, Reset 0x0000 Table 12-27. DMA Transfer Count[15:0] Figure 12-24. UARTx Transmit DMA Count Registers Table 12-27. UARTx Transmit DMA Count Register MMR Assignments Register Name Memory-Mapped Address UART0_COUNT_TX 0xFFC0 1B08 UART1_COUNT_TX 0xFFC0 1F08 12-32 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 555: Uartx Transmit Dma Next Descriptor Pointer Registers
Pointer. The complete 32-bit address is created by combining this value with the upper 16 bits from the DMA Descriptor Base Pointer Register ( ). For more information on the DMA DMA_DBP Descriptor Base Pointer Register, see “Direct Memory Access” on page 9-1. ADSP-BF535 Blackfin Processor Hardware Reference 12-33...
Page 556: Uartx Transmit Dma Descriptor Ready Registers
Reset 0x0000 Table 12-29. Descriptor Ready Figure 12-26. UARTx Transmit DMA Descriptor Ready Registers Table 12-29. UARTx Transmit DMA Descriptor Ready Register MMR Assignments Register Name Memory-Mapped Address UART0_DESCR_RDY_TX 0xFFC0 1B0C UART1_DESCR_RDY_TX 0xFFC0 1F0C 12-34 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 557: Uartx Transmit Dma Irq Status Registers
UART1_IRQSTAT_TX 0xFFC0 1F0E IrDA Support Aside from the standard UART functionality, UART0 also supports half duplex serial data communication via infrared signals, according to the recommendations of the Infrared Data Association (IrDA). The physical ADSP-BF535 Blackfin Processor Hardware Reference 12-35...
Page 558: Uart0 Infrared Control Register (Uart0_Ircr)
Minimum number of Serial Data 0 = negative pulse In samples required for a Data 1 = no pulse valid pulse to be detected. IRPD= ((Pulse width(sec) xSCLK freq)–2). Figure 12-28. UART0 Infrared Control Register 12-36 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 559: Irda Transmitter Description
16 UART clock cycles. As shown in Table 12-9 on page 12-12, the error terms associated with the baud rate generator are very small and well within the tolerance of most infrared transceiver specifications. ADSP-BF535 Blackfin Processor Hardware Reference 12-37...
Page 560: Irda Receiver Description
0x8b. In this example, receive IRPD data during the sampling window, whose duration is greater than 141 cycles, is treated as valid data. Figure 12-30 shows the receiver SCLK functionality. 12-38 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 561 1 transition corresponds to a UART NRZ value of 0. • = 1 assumes that the receive data input idles 1 and each IRPOL active 0 transition corresponds to a UART NRZ value of 0. ADSP-BF535 Blackfin Processor Hardware Reference 12-39...
Page 562 IrDA Support 12-40 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 563: 13 Pci Bus Interface
(master) or the PCI target (slave) for a PCI bus transaction. The PCI bus interface consists of a PCI controller, interfaces to internal buses, and drivers for the external PCI bus (see the block diagram in Figure 13-1). ADSP-BF535 Blackfin Processor Hardware Reference 13-1...
Page 564: Pci Specification
132 MB/second. PCI Specification The PCI bus interface conforms to PCI Local Bus Specification Rev. 2.2. The specification is maintained by the PCI Special Interest Group and can be obtained from http://www.pcisig.com 13-2 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 565: Pci Device Function
32-bit core memory space. Since the PCI memory space is as large as the full memory address space of the ADSP-BF535 processor, a segmented, or windowed, approach must be employed, so that only portions of the PCI ADSP-BF535 Blackfin Processor Hardware Reference 13-3...
Page 566: External Pci Requirements
0 (the ADSP-BF535 processor device) results in a master abort. Device Mode Operation The ADSP-BF535 processor is in device mode when the Host/device bit in the PCI Bridge Control register is cleared (its default setting). 13-4 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 567 * This reserved block does not exist if all four blocks of SDRAM are configured to their full 128 MByte size. Figure 13-2. PCI Memory Map ADSP-BF535 Blackfin Processor Hardware Reference 13-5...
Page 568: Outbound Transactions (Adsp-Bf535 Processor As Pci Initiator)
For all outbound read and write transactions, the control signals of the transactions are placed into a FIFO that is written in the domain and SCLK read by the PCI core in the PCI clock domain. For writes, the data written 13-6 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 569: Outbound Error Detection And Reporting
The Unsupported EAB Access sticky bit in the register PCI_STAT is set, and causes an interrupt if masked to do so in the register. PCI_ICTL ADSP-BF535 Blackfin Processor Hardware Reference 13-7...
Page 570: Supported Transactions To Pci
Supported Transactions to PCI The PCI interface is capable of handling these types of transactions: • Single 8-bit, 16-bit, and 32-bit • 4-beat incrementing 8-bit, 16-bit, and 32-bit bursts • 8-beat incrementing 8-bit, 16-bit, and 32-bit bursts 13-8 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 571 8-beat incrementing 8-bit Two 32-bit word bursts 4-beat incrementing 16-bit Two 32-bit word bursts 8-beat incrementing 16-bit Four 32-bit word bursts 4-beat incrementing 32-bit Four 32-bit word bursts 8-beat incrementing 32-bit Eight 32-bit word bursts ADSP-BF535 Blackfin Processor Hardware Reference 13-9...
Page 572: Inbound Transactions
0s exist in the mask are ignored, but the write to the BAP completes successfully. If memory or I/O transactions are not needed, then the corresponding BAP register is ignored and does not need to be programmed. When the processor core has completed writing to 13-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 573 Fast Back-to-Back Enable bit in the register. This bit may be set and PCI_CTL cleared at any time during operation to enable and disable fast back-to-back transfers whenever necessary. ADSP-BF535 Blackfin Processor Hardware Reference 13-11...
Page 574: Inbound Error Detection And Reporting
0 and 2 of a word. On reads, this is not a problem because the whole word can be read and the master of the trans- action can take the data it wants. 13-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 575: Host Mode Operation
Outbound transactions in host mode are accomplished by the same method as in device mode. The only difference is that the ADSP-BF535 processor is responsible for configuring the devices on the PCI bus for cer- tain memory ranges. ADSP-BF535 Blackfin Processor Hardware Reference 13-13...
Page 576: Inbound Transactions
PCI devices during configuration. Any space made available by disabling one of these regions or by sizing down one of the RAM regions is also available for assignment to PCI 13-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 577: Outbound Configuration Transactions
Type 1 transaction into a Type 0 transaction if the bus number connected to the PCI core matches the bus number in the config- uration address. The PCI core behavior is consistent with that of the host-to-PCI-bridge behavior. ADSP-BF535 Blackfin Processor Hardware Reference 13-15...
Page 578: Reset Behavior And Control
PCI core logic to be reset during the reset of either sys- tem. It also allows the surrounding logic to return to a known state but register the and only completely reset during an ADSP-BF535 PCI_RST processor reset. 13-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 579: Interrupt Behavior And Control
Note all PCI signals are active low, but the bits in the and the PCI_CTL registers are active high. So setting the INTA to PCI bit asserts PCI_STAT signal and the bits are set when the corresponding line INTA INTA-INTD is asserted. ADSP-BF535 Blackfin Processor Hardware Reference 13-17...
Page 580: Pci Programming Model
Shared resources should be protected by software locks. With respect to program order, EAB reads and PAB accesses are always completed in order, since the core is stalled until they complete. 13-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 581: System Mmr Control And Status Registers
“Configuration Space Control and Status Registers” on page 13-26 a description of the configuration space MMRs. Also see “System MMR Assignments” on page B-1 for the PCI MMRs mapped into the PAB sys- tem MMR space. ADSP-BF535 Blackfin Processor Hardware Reference 13-19...
Page 582: Pci Bridge Control Register (Pci_Ctl)
It is used to put the interface in host or device mode. This register includes the PCI Enable bit used to enable PCI access after the configura- tion registers have been set up, and it includes the enable bit for outbound fast back-to-back transactions. 13-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 583: Pci Status Register (Pci_Stat)
PCI Master TX FIFO Full PCI Master TX FIFO Empty 0 - Not full 0 - Not empty 1 - Transmit FIFO full for master 1 - Transmit FIFO empty operation Figure 13-4. PCI Status Register ADSP-BF535 Blackfin Processor Hardware Reference 13-21...
Page 584: Pci Interrupt Controller Register (Pci_Ictl)
INTD Enable Error on Inbound Read Enable PCI Parity Error Enable PCI Fatal Error Enable Memory Write Invalidate Enable PCI Reset Enable PCI Master TX FIFO Empty Enable Figure 13-5. PCI Interrupt Controller Register 13-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 585: Pci Outbound Memory Base Address Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 4010 Reset = 0x0000 0000 16-bit PCI Space Base Address 15 14 13 12 11 10 Figure 13-7. PCI Outbound I/O Base Address Register ADSP-BF535 Blackfin Processor Hardware Reference 13-23...
Page 586: Pci Outbound I/O Configuration Address Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 4014 Reset = 0x0000 0000 I/O Configuration Address [31:16] 15 14 13 12 11 10 I/O Configuration Address [15:0] Figure 13-8. PCI Outbound I/O Configuration Address Register 13-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 587: Pci Inbound Memory Base Address Register
PCI_TIBAP ger multiple of this size. The MMR address for this register is 0xFFC0 401C. Its reset value is 0x0000 0000. ADSP-BF535 Blackfin Processor Hardware Reference 13-25...
Page 588: Configuration Space Control And Status Registers
1s and bits 0 through 23 would contain 0s. Bits 0 through 3 of this register are not writable and always contain 0s. As a result, the small- est non zero window that can be specified is 16 bytes long. Similarly, bit 13-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 589: Pci Device I/O Bar Mask Register (Pci_Dibarm)
For example, if a 64 byte window is available for the host to use as an I/O win- dow in the Blackfin processor’s memory space, bits 31 through 6 would ADSP-BF535 Blackfin Processor Hardware Reference 13-27...
Page 590 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = Never Reset 0xEEFF FF04 on PCI Reset Size of I/O Window[31:16] 15 14 13 12 11 10 Size of I/O Window[15:2] Figure 13-10. PCI Device I/O BAR Mask Register 13-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 591: Pci Configuration Device Id Register (Pci_Cfg_Dic)
Figure 13-11. PCI Configuration Device ID Register It is not used in host mode. Program this register before enabling the PCI in device mode. For more information, see the PCI Local Bus Specifica- tion Rev. 2.2. ADSP-BF535 Blackfin Processor Hardware Reference 13-29...
Page 592: Pci Configuration Vendor Id Register (Pci_Cfg_Vic)
Figure 13-12. PCI Configuration Vendor ID Register It is not used in host mode. Program this register before enabling the PCI in device mode. For more information, see the PCI Local Bus Specifica- tion Rev. 2.2. 13-30 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 593: Pci Configuration Status Register (Pci_Cfg_Stat)
1 - Target abort signaled Figure 13-13. PCI Configuration Status Register The information in this register applies to both host mode and device mode. For more information, see the PCI Local Bus Specification Rev. 2.2. ADSP-BF535 Blackfin Processor Hardware Reference 13-31...
Page 594: Pci Configuration Command Register (Pci_Cfg_Cmd)
Memory Write and Invalidate - 0 - Device uses memory write command instead of memory write and invalidate command 1 - Device enabled for memory write and invalidate command Figure 13-14. PCI Configuration Command Register 13-32 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 595: Pci Configuration Class Code Register (Pci_Cfg_Cc)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xEEFF FF18 Reset = 0x0000 0000 Class Code[23:16] 15 14 13 12 11 10 Class Code[15:0] Figure 13-15. PCI Configuration Class Code Register ADSP-BF535 Blackfin Processor Hardware Reference 13-33...
Page 596: Pci Configuration Revision Id Register (Pci_Cfg_Rid)
Figure 13-16. PCI Configuration Revision ID Register It is not used in host mode. Program this register before enabling the PCI in device mode. For more information, see the PCI Local Bus Specifica- tion Rev. 2.2. 13-34 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 597: Pci Configuration Bist Register (Pci_Cfg_Bist)
Reset = 0x0000 0000 15 14 13 12 11 10 BIST[7:0] Figure 13-17. PCI Configuration BIST Register The PCI core does not support BIST. For more information, see the PCI Local Bus Specification Rev. 2.2. ADSP-BF535 Blackfin Processor Hardware Reference 13-35...
Page 598: Pci Configuration Header Type Register (Pci_Cfg_Ht)
PCI system configuration in host mode. In device mode, the system processor writes to this register. The lowest two bits are read only and hardwired to 0 so that latency values are always in increments of four PCI clock cycles. 13-36 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 599: Pci Configuration Cache Line Size Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 0xEEFF FF2C 15 14 13 12 11 10 Cache Line Size[7:0] Figure 13-20. PCI Configuration Cache Line Size Register ADSP-BF535 Blackfin Processor Hardware Reference 13-37...
Page 600: Pci Configuration Memory Base Address Register
Type[1:0] - RO 0 - Not prefetchable 1 - Prefetchable 00 - Lower 4 GB 01 - Below 1 MB 10 - Over 4 GB 11 - Reserved Figure 13-21. PCI Configuration Memory Base Address Register 13-38 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 601: Pci Configuration I/O Base Address Register
This register is unused in Host mode. For more information, see the PCI Local Bus Specification Rev. 2.2. ADSP-BF535 Blackfin Processor Hardware Reference 13-39...
Page 602: Pci Configuration Subsystem Id Register
ID from the PCI configuration registers. Program this register before enabling the PCI in device mode. This register is not used in host mode. For more information, see the PCI Local Bus Specification Rev. 2.2. 13-40 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 603: Pci Configuration Maximum Latency Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xEEFF FF40 Reset = 0x0000 0000 15 14 13 12 11 10 Maximum Latency Cycles[15:0] Figure 13-25. PCI Configuration Maximum Latency Register ADSP-BF535 Blackfin Processor Hardware Reference 13-41...
Page 604: Pci Configuration Minimum Grant Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xEEFF FF48 Reset = 0x0000 0000 15 14 13 12 11 10 Interrupt Pin[7:0] Figure 13-27. PCI Configuration Interrupt Pin Register 13-42 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 605: Pci Configuration Interrupt Line Register (Pci_Cfg_Il)
Mem window in 64-MB blocks. The SDRAM access size is valid only if the SDRAM Access Enable bit is set. It specifies the size of the accessible SDRAM window in 32-MB blocks. This register is valid only in host mode. ADSP-BF535 Blackfin Processor Hardware Reference 13-43...
Page 606: Pci I/O Issues
PCI clock. This approach minimizes noise and termination issues at the board level, and lowers overall system power consumption. 13-44 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 607: Power Sequencing
<= 2 ns across all PCI component clock inputs. The clock may be stopped, but only in the low state. This clock can be driven com- pletely asynchronously with respect to the internal ADSP-BF535 processor’s clocks and CLKIN ADSP-BF535 Blackfin Processor Hardware Reference 13-45...
Page 608 PCI I/O Issues 13-46 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 609: 14 Usb Device
A list of references is provided at the end of the chapter. Convention All transfer directions use the USB host as the point of reference. An IN transfer indicates the host is receiving data, and an OUT transfer indicates the host is transmitting data. ADSP-BF535 Blackfin Processor Hardware Reference 14-1...
Page 610: Requirements
• Connection to the PAB as a slave only for system access to registers • Connection to the DAB as a master only for access to L2 memory, through a DMA Master module 14-2 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 611: Usb Requirements
The bus master is referred to as the USB host, and the bus slaves are referred to as USB devices. Each USB device implements one or more USB endpoints, which are similar to virtual data channels. Each endpoint on a USB device operates independently of all the others. ADSP-BF535 Blackfin Processor Hardware Reference 14-3...
Page 612: Usb Implementation
• System software is responsible for managing interrupt priority and requeueing low priority events as software interrupts. • Memory access for the USB endpoints is by means of the DAB as a bus master. 14-4 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 613 The USBD has multiple clock domains. Although the PLL_IOCK register allows shutting down the system clock for the front-end interface in USBD, the suspend capabilities allow for a software management scheme of the UDC’s clocks. ADSP-BF535 Blackfin Processor Hardware Reference 14-5...
Page 614: Block Diagram
The UDC module implements the low-level USB protocol. It manages interaction with the USB host using the USB serial link, and presents data and command transactions to the application by means of a simple appli- cation bus. 14-6 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 615: Front-End Interface Block
It also decodes transactions that occur on the UDC’s application bus for presentation to the other submodules. This module routes endpoint trans- actions to and from the Memory Interface module, and control, configuration, and status functions to and from the Registers and Control module. ADSP-BF535 Blackfin Processor Hardware Reference 14-7...
Page 616: Registers And Control Block
USBD. Software uses the endpoint registers to route USB endpoint data transfers to specific regions within the module’s memory space. This module is connected to the PAB interface by a simple internal peripheral bus. 14-8 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 617: Dma Master Block
DAB. Device software is responsible for allocating the 2 KB buffer space among all active endpoints. The DMA address, transfer count, direction, and interrupt status are available for monitoring. ADSP-BF535 Blackfin Processor Hardware Reference 14-9...
Page 618: Pab Interface Block
From the point of view of the USB device, Bulk and Interrupt transfers function identically on the device. The differences between these transfer types are implemented in the USB host controller, the USB device’s descriptor tables, and in the software. 14-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 619: Data Transfers
Each DATA trans- fer within this sequence consists of bulk data; that is, error checking/retry is included, and the range of packet sizes is limited. ADSP-BF535 Blackfin Processor Hardware Reference 14-11...
Page 620: Udc Configuration Control
Each endpoint can have a different definition depending on the interface and alternate interface used. For communications to occur, the specific device configuration must be downloaded into the module after system startup. See “Configuration of the UDC Module” on page 14-44. 14-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 621: Suspend Operation
A USB buffer chip, such as the Philips PDI USB P11A, must be added in order to use the USB device functionality of the ADSP-BF535 processor. The diagram in Figure 14-2 shows how to connect a Philips PDI USB P11A transceiver to the ADSP-BF535 processor. ADSP-BF535 Blackfin Processor Hardware Reference 14-13...
Page 622: Registers
This section describes the register set for the USBD module. All USBD memory-mapped registers are 16 bits wide, and 16-bit aligned. The registers are grouped into three categories: general registers, DMA registers, and endpoint registers. 14-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 623: Current Usb Frame Number Register (Usbd_Frm)
USBD_DMAIRQ The USB Endpoint registers handle endpoint specific interrupts and con- trol of the datapath. The number of endpoint specific registers is dependent on the number of endpoints with which the design is compiled. ADSP-BF535 Blackfin Processor Hardware Reference 14-15...
Page 624 Use this value to allow software drivers to adapt to different hardware revisions.  The specific vendor ID (for example, 0x0456 for Analog Devices, Inc.) and the product ID (for example, 0x2153 for the ADSP-BF535 processor) should not be programmed using this reg- ister.
Page 625 This register, shown in Figure 14-5, provides a mechanism for software to wait for the arrival of a specific USB frame number. This feature is typi- cally used with isochronous endpoints for synchronization between the ADSP-BF535 Blackfin Processor Hardware Reference 14-17...
Page 626 The total number of physical endpoints on the device is hardwired, but the specific configuration of each endpoint is downloaded into the device by the firmware. 14-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 627 USBD_AIF field contains the alternate interface number. This field is USBD_AIF updated when the USB host sends a request to the device. SET_INTERFACE It changes along with the field. USBD_IF ADSP-BF535 Blackfin Processor Hardware Reference 14-19...
Page 628 Currently accessed endpoint 0 - Setup packet not in USBD_PIP progress 0 - Packet not in progress 1 - Setup packet in progress 1 - Packet in progress Figure 14-7. USBD Module Status Register 14-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 629: Usbd Module Configuration And Control Register
0 - Stall request completed 0 - Stall request completed or no stall pending or no stall pending 1 - Assert a stall request 1 - Assert a stall request Figure 14-8. USBD Module Configuration and Control Register ADSP-BF535 Blackfin Processor Hardware Reference 14-21...
Page 630 All the interrupts are edge triggered. Modifying the mask bit in an end- point interrupt register may trigger an interrupt from an earlier endpoint interrupt. “Interrupt Descriptions” on page 14-37 for detailed explanations of each interrupt. 14-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 631: Global Interrupt Register (Usbd_Gintr)
0 - No interrupt pending 0 - No interrupt pending for DMA master channel for endpoint 0 1 - Interrupt pending for 1 - Interrupt pending for DMA master channel endpoint 0 Figure 14-9. Global Interrupt Register ADSP-BF535 Blackfin Processor Hardware Reference 14-23...
Page 632: Dma Master Channel Configuration Register
Writing a 1 initiates and holds the buffer in a clear state. A write of 0 must follow before normal operation can resume. It is recom- mended that the DMA be disabled and the USB be prevented from accessing the FIFO before is set. USBD_DMABC 14-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 633: Dma Master Channel Base Address Low Register
Figure 14-12. DMA Master Channel Base Address Low Register To produce a physical address on a per-transfer basis, the DMA master channel replaces bits [10:0] with an endpoint specific offset value. Bits [10:0] always read back 0. ADSP-BF535 Blackfin Processor Hardware Reference 14-25...
Page 634: Dma Master Channel Base Address High Register
0 to 4 words (16 bytes). DMA Master Channel Count Register (USBD_DMACT) 15 14 13 12 11 10 0xFFC0 4446 Reset = 0x0004 USBD_CT[2:0] - RO Figure 14-14. DMA Master Channel Count Register 14-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 635: Dma Master Channel Dma Interrupt Register
USBD_MSETUP USBD_SETUP bit is set when a setup packet is received on the current USBD_SETUP endpoint. ADSP-BF535 Blackfin Processor Hardware Reference 14-27...
Page 636 For Isochronous endpoints, this interrupt asserts at the end of every packet. The error detection mechanism used for isochronous transfers requires the software to examine the endpoint configuration reg- isters and determine how much data was actually transferred. 14-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 637: Usb Endpoint X Interrupt Registers (Usbd_Intrx)
The USB Endpoint x Mask registers, shown in Figure 14-17, can be used to mask the interrupts in the USB Endpoint x Interrupt registers ). Setting a bit in the USB Endpoint x Mask registers masks USBD_INTRx ADSP-BF535 Blackfin Processor Hardware Reference 14-29...
Page 638: Usb Endpoint X Mask Registers (Usbd_Maskx)
Table 14-2. USB Endpoint x Mask Register MMR Assignments Register Name Memory-Mapped Address USBD_MASK0 0xFFC0 4482 USBD_MASK1 0xFFC0 448C USBD_MASK2 0xFFC0 4496 USBD_MASK3 0xFFC0 44A0 USBD_MASK4 0xFFC0 44AA USBD_MASK5 0xFFC0 44B4 USBD_MASK6 0xFFC0 44BE USBD_MASK7 0xFFC0 44C8 14-30 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 639 NAKs the current packet. This can occur on USB control transfers when the endpoint is set to OUT for the setup packet and the USB host requests an IN data-phase packet before the device has recog- nized the presence of the setup packet. ADSP-BF535 Blackfin Processor Hardware Reference 14-31...
Page 640: Usb Endpoint X Control Registers (Usbd_Epcfgx)
Table 14-3. USB Endpoint x Mask Register MMR Assignments Register Name Memory-Mapped Address USBD_EPCFG0 0xFFC0 4484 USBD_EPCFG1 0xFFC0 448E USBD_EPCFG2 0xFFC0 4498 USBD_EPCFG3 0xFFC0 44A2 USBD_EPCFG4 0xFFC0 44AC USBD_EPCFG5 0xFFC0 44B6 USBD_EPCFG6 0xFFC0 44C0 USBD_EPCFG7 0xFFC0 44CA 14-32 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 641: Usb Endpoint X Address Offset Registers (Usbd_Epadrx)
USBD_EPLENx ware is keeping track of the original buffer addresses and can calculate the bytes transferred and the end of valid data based on reading back these registers at the end of a transfer. ADSP-BF535 Blackfin Processor Hardware Reference 14-33...
Page 642: Usb Endpoint X Buffer Length Registers (Usbd_Eplenx)
For non-isochronous endpoints, this field decrements by the packet size as each packet is transferred on the USB. For isochronous endpoints, this field decrements by the DMA burst size (16 bytes) at the end of each DMA burst. 14-34 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 643: Udc Endpoint Buffer Register
, see “Enable Download of USBD_EPBUF Configuration Into UDC Core Register (USBD_EPBUF)” on page 14-18. This register cannot be accessed through the peripheral bus. This register is not a memory-mapped register. ADSP-BF535 Blackfin Processor Hardware Reference 14-35...
Page 644 0 to 1023 with 8, 16, 32, or 64 as the only possible values for physical endpoints defined as Control, Bulk, and Interrupt. field reflects the endpoint being used for the transac- EP_BUFADRPTR tion. For the ADSP-BF535 processor, the should reflect the EP_BUFADRPTR endpoint on bits [0:2]. 14-36 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 645: Interrupt Descriptions
The interrupt subsystem is based on a two-tiered approach. The USBD module presents a single interrupt output to the system, but internally it manages separate interrupt registers for critical module events, the DMA master channel, and each endpoint. ADSP-BF535 Blackfin Processor Hardware Reference 14-37...
Page 646: Usb General Interrupts
To prevent the device’s configuration from becoming out of sync with the intended configuration (from the USB host’s viewpoint), the device refuses all traffic from the USB while the interrupt is pending. Masking the interrupt does not disable the USB activity lockout feature. 14-38 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 647: Usbd_Msof - Missed Start Of Frame
Because internal logic is synchronous, this interrupt may not assert when the module leaves the suspended state, depending on how and when the system restarts the clocks. ADSP-BF535 Blackfin Processor Hardware Reference 14-39...
Page 648: Usbd_Frmat – Frame Match
Each interrupt source is sticky. Thus an enabled interrupt source which asserts an interrupt request by setting the appropriate bit remains set until cleared. Clearing an interrupt source is accomplished by writing a 1 to the corresponding bit. 14-40 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 649: Dma_Comp
DMA engine responds with an error and: • Completes the current burst transfer. • Clears the DMA Enable bit (Bit 0 of the Configuration Word). • Sets bit 2 of the DMA Master Channel DMA Count register. ADSP-BF535 Blackfin Processor Hardware Reference 14-41...
Page 650: Usb Endpoint Interrupts
This interrupt does not assert when a setup packet is received on a control endpoint. USBD_PC – Packet Complete This interrupt asserts when a packet transfer completes on the current endpoint. System software can use this interrupt to monitor the progress of a data transfer. 14-42 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 651: Usbd_Bcstat – Buffer Complete
USB device will accept it. If the USB device is not ready, then this is wasted bus bandwidth that could be given to another device which is ready to complete a packet transfer. ADSP-BF535 Blackfin Processor Hardware Reference 14-43...
Page 652: Usb Programming Model
64 logical endpoint buffers to program.  Note: Even if all 64 endpoint buffers are not used in a specific product, the core expects all 64 logical endpoint buffers to be allo- cated data after each hard reset. 14-44 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 653 Figure 14-21 on page 14-37 for more information about the UDC register format.  For endpoint 0, program the configuration, interface, and alternate values to 0 in the UDC Endpoint Buffer register. ADSP-BF535 Blackfin Processor Hardware Reference 14-45...
Page 654: Usbd Device Initialization
The most likely sequence of events from the USB is that the device comes out of reset and receives a request from the GET_DESCRIPTOR USB host for the first 8 bytes of the device descriptor, potentially followed by additional requests. At that point, the GET_DESCRIPTOR 14-46 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 655: Usb Data Transfers
For isochronous endpoints, the transfer size is irrelevant, because they get the same bandwidth every frame, whether they need it or not. Control transfers specify the length of their ADSP-BF535 Blackfin Processor Hardware Reference 14-47...
Page 656: How To Transfer Data
USBD_MAX mum packet size. • Set to the code for the endpoint type. USBD_TYP • Set to IN or OUT. USBD_DIR • Set to 1. USBD_ARM 4. Wait for interrupts. 14-48 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 657: Bulk Transfers
The best the device can do to ensure maximum bandwidth use of the USB is to be ready for a transfer at all times. This means setting up multiple buffering for the endpoints. ADSP-BF535 Blackfin Processor Hardware Reference 14-49...
Page 658 USBD_TC • = 0. USBD_GMASK USBD_EPxMSK 3. Configure the endpoint: • = 01, = 1, = 11, USBD_EPCFGx USBD_TYP USBD_DIR USBD_MAX = 1. USBD_ARM • = 0x0080. USBD_EPADRx USBD_OFFSET • = 0x0080. USBD_EPLEN0 USBD_BC 14-50 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 659: Bulk Out
L2 memory space, and buffer size 0x80 (four packets). Programming flow 1. Clear interrupt registers: and the USBD_EPINTRx USBD_EPxINTR of the register. USBD_GINTR 2. Unmask interrupts: • = 0, = 0, = 0. USBD_MASKx USBD_BCSTAT USBD_TC USBD_PC • = 0. USBD_GMASK USBD_EPxMSK ADSP-BF535 Blackfin Processor Hardware Reference 14-51...
Page 660 USBD_EPLENx 5. Clear the endpoint interrupts, take the steps required to complete the transfer in software, then go back to step 2 and update the reg- isters for a new data transfer. 14-52 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 661: Isochronous Transfers
USBD_SOF USBD_STAT register to see exactly what is occurring on the bus at any given time. Specific examples of ISO IN and ISO OUT register programming are shown in the following sections. ADSP-BF535 Blackfin Processor Hardware Reference 14-53...
Page 662 = 0. USBD_GMASK USBD_EPxMSK 3. Configure the endpoint: • USBD_EPCFGx • = 11, = 1, = XX, USBD_TYP USBD_DIR USBD_MAX = 1. USBD_ARM • USBD_EPADRx • = 0x0080. USBD_OFFSET • USBD_EPLEN0 • = 0x0080. USBD_BC 14-54 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 663 = 0. USBD_GMASK USBD_EPxMSK 2. Configure the endpoint: • USBD_EPCFGx • = 11, = 0, = XX, USBD_TYP USBD_DIR USBD_MAX = 1. USBD_ARM • USBD_EPADRx • = 0x0080. USBD_OFFSET • USBD_EPLEN0 • = 0x03FF. USBD_BC ADSP-BF535 Blackfin Processor Hardware Reference 14-55...
Page 664: Control Transfers
(if any), the size of the data phase (if any), and the specific command code. After receiving the command, the device can choose to reject the com- mand by stalling the endpoint, or it can process the command and proceed through the data and status phases. 14-56 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 665: Control Transfer, No Data Phase
( ) for USBD_EPCFGx USBD_EPLENx a 0 byte IN transfer, and set the bit to 1. If the command USBD_ARM does not complete successfully, set the bit in the USBD_EPxSTALL register. USBD_CTRL ADSP-BF535 Blackfin Processor Hardware Reference 14-57...
Page 666: Control Transfer With Data Phase
0 bytes, or a STALL handshake. The direction of the status phase is opposite that of the data transfer. For example, for a control transfer with an OUT data phase, set the endpoint registers 14-58 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 667: Control Transfers Gone Bad
USB module is in the process of receiving a new setup packet. Software can check these bits before moving to the DATA or STATUS phase of the control transfer to determine whether the command request that it is processing is about to be invalidated. ADSP-BF535 Blackfin Processor Hardware Reference 14-59...
Page 668: Exception Handling
When software needs to indicate a stall condition, it sets the bit. After the bit has been set, application USBD_EPxSTALL USBD_EPxSTALL behavior is product specific. The application must clear the bit in the register. USBD_EPxSTALL USBD_CTRL 14-60 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 669: Isochronous Transfers Error Detection
USB host. The system does not need to re-download the UDC end- point buffer data, nor does it need to reinitialize the device. ADSP-BF535 Blackfin Processor Hardware Reference 14-61...
Page 670: References
• Universal Serial Bus System Architecture, Don Anderson, Mindshare Inc. • Universal Serial Bus Specification, Rev 1.1, USB Implementers Forum, www.usb.org. Available online. • Open Host Controller Interface Specification, Rev 1.0, USB Imple- menters Forum, www.usb.org. Available online. 14-62 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 671 • USB Device Class Specifications, www.usb.org. The common class specifications provide a framework in which device developers can make use of standardized device drivers on the USB host. Examples are printers, disk drives, and broadband modems. ADSP-BF535 Blackfin Processor Hardware Reference 14-63...
Page 672 References 14-64 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 673: 15 Programmable Flags
) and a Flag Interrupt Mask FIO_MASKx_S Clear register ( ). This flexible mechanism allows each bit to FIO_MASKx_C generate Flag Interrupt A, Flag Interrupt B, both Flag Interrupts A and B, or neither. ADSP-BF535 Blackfin Processor Hardware Reference 15-1...
Page 674: Programmable Flag Memory-Mapped Registers (Mmrs)
Each pin is represented by a bit in each of these registers. 15-2 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 675 ) defined as out- PF[0] puts and driven high, and the present sense of those pins defined as inputs. Input sense is based on settings, as well as FIO_POLAR FIO_EDGE the logic level at each pin. ADSP-BF535 Blackfin Processor Hardware Reference 15-3...
Page 676 Clear PF0 Clear PF14 Clear PF1 Clear PF13 Clear PF2 Clear PF12 Clear PF3 Clear PF11 Clear PF4 Clear PF10 Clear PF5 Clear PF9 Clear PF6 Clear PF8 Clear PF7 Figure 15-3. Flag Clear Register 15-4 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 677: Flag Interrupt Mask Registers
Interrupt B, both Flag Interrupts A and B, or neither. When using either rising or falling edge-triggered interrupts, the interrupt condition must be cleared each time a corresponding interrupt is serviced by writing a 1 to the appropriate bit. FIO_FLAG_C ADSP-BF535 Blackfin Processor Hardware Reference 15-5...
Page 678 Disable PF3 Interrupt Disable PF11 Interrupt Disable PF4 Interrupt Disable PF10 Interrupt Disable PF5 Interrupt Disable PF9 Interrupt Disable PF6 Interrupt Disable PF8 Interrupt Disable PF7 Interrupt Figure 15-5. Flag Interrupt A Mask Clear Register 15-6 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 679 B event can be generated. Note that the flow is shown for only one programmable flag, FlagN. However, a Flag Interrupt is generated by a logical OR of all unmasked pins for that interrupt. For example, if ADSP-BF535 Blackfin Processor Hardware Reference 15-7...
Page 680 FIO_DIR? FIO_DIR? FlagN generating FlagN generating an interrupt an interrupt condition? condition? Is FlagN Is FlagN asserted asserted high? high? FLAG INTERRUPT A OCCURS FLAG INTERRUPT B OCCURS Figure 15-8. Flag Interrupt Generation Flow 15-8 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 681: Flag Polarity Register (Fio_Polar)
PF0 Polarity PF14 Polarity PF1 Polarity PF13 Polarity PF2 Polarity PF12 Polarity PF3 Polarity PF11 Polarity PF4 Polarity PF10 Polarity PF5 Polarity PF9 Polarity PF6 Polarity PF8 Polarity PF7 Polarity Figure 15-9. Flag Polarity Register ADSP-BF535 Blackfin Processor Hardware Reference 15-9...
Page 682: Flag Interrupt Sensitivity Register (Fio_Edge)
The contents of this register are cleared at reset, defaulting to level sensitivity. Flag Set on Both Edges Register (FIO_BOTH) The Flag Set on Both Edges register, shown in Figure 15-11, is used to enable interrupt generation on both rising and falling edges. 15-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 683: Performance/Throughput
4 cycles between SCLK the time the flag is asserted and the time that program flow is interrupted. When configured for edge-sensitive interrupt generation, an additional ADSP-BF535 Blackfin Processor Hardware Reference 15-11...
Page 684 Performance/Throughput cycle of latency is introduced, giving a total latency of 5 cycles SCLK SCLK between the time the edge is asserted and the time that the core program flow is interrupted. 15-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 685: General-Purpose Timers
. This pin functions as an output pin in PWM_OUT mode and TMRx as an input pin in WDTH_CAP and EXT_CLK modes. When clocked internally, the clock source is the ADSP-BF535 processor’s system clock SCLK ADSP-BF535 Blackfin Processor Hardware Reference 16-1...
Page 686: General-Purpose Timer Registers
Timer0 Configuration register TIMER0_COUNTER_LO 0xFFC0 2004 Timer0 Counter register, Low Word TIMER0_COUNTER_HI 0xFFC0 2006 Timer0 Counter register, High Word TIMER0_PERIOD_LO 0xFFC0 2008 Timer0 Period register, Low Word TIMER0_PERIOD_HI 0xFFC0 200A Timer0 Period register, High Word 16-2 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 687 Table 16-2. Abbreviated MMR References from Table 16-1 Register Name Memory-Mapped Description Address TIMER0_COUNTER 0xFFC0 2004 Timer0 Counter register TIMER0_PERIOD 0xFFC0 2008 Timer0 Period register TIMER0_WIDTH 0xFFC0 200C Timer0 Width register TIMER1_COUNTER 0xFFC0 2014 Timer1 Counter register ADSP-BF535 Blackfin Processor Hardware Reference 16-3...
Page 688: Timer Status Registers (Timerx_Status)
They need to be cleared in for each timer explicitly. To clear, write a TIMERx_STATUS 1 to the bit.  Interrupt and overflow bits may be cleared at the same time as timer disable bits. 16-4 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 689 TIMEN0 (Timer0 Enable) - W1S 1 - Timer1 overflow occurred 1 - Enable Timer0 OVF_ERR2 (Timer2 Counter Overflow) - RO 0 - No Timer2 overflow occurred 1 - Timer2 overflow occurred Figure 16-1. Timer0 Status Register ADSP-BF535 Blackfin Processor Hardware Reference 16-5...
Page 690 1 - Clear Timer1 overflow flag 1 - Timer0 enabled (if TIMDIS0 = 1) OVF_ERR2 (Timer2 Counter Overflow) - RO 0 - No Timer2 overflow occurred 1 - Timer2 overflow occurred Figure 16-2. Timer1 Status Register 16-6 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 691: Timer Configuration Registers (Timerx_Config)
IRQx TIMERx_STATUS instruction executes. This ensures that the interrupt is not reissued. Remember that writes to system registers are delayed. If only a few instructions separate the clear command from the instruction, an IRQx ADSP-BF535 Blackfin Processor Hardware Reference 16-7...
Page 692 , Timer TMRx UART0 1 alternatively captures , and Timer 2 alternatively captures UART1 UART1 Table 16-3. Timer Configuration Register MMR Assignments Register Name Memory-Mapped Address TIMER0_CONFIG 0xFFC0 2002 TIMER1_CONFIG 0xFFC0 2012 TIMER2_CONFIG 0xFFC0 2022 16-8 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 693 T i me r T I MEN x Di sab led SCLK COUN T C OUN T COUN T C OUN T =M+ 1 = M+1 =M+ 1 Figure 16-5. Timer Enable and Disable Timing ADSP-BF535 Blackfin Processor Hardware Reference 16-9...
Page 694: Timer Period Registers (Timerx_Period)
15 14 13 12 11 10 assignments, see Reset = 0x0000 0000 Table 16-1 on page 16-2. Timer Period Hi[15:0] 15 14 13 12 11 10 Timer Period Lo[15:0] Figure 16-6. Timer Period Registers 16-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 695: Timer Width Registers (Timerx_Width)
Timer Counter Registers (TIMERx_COUNTER) These read-only registers retain their state when disabled. When enabled, the counter is reinitialized from the Timer Period and Timer Width regis- ters based on the mode selected in TIMERx_CONFIG ADSP-BF535 Blackfin Processor Hardware Reference 16-11...
Page 696 15 14 13 12 11 10 For MMR Reset = 0x0000 0000 assignments, see Table 16-1 on page 16-2. Timer Counter Hi[31:16] 15 14 13 12 11 10 Timer Counter Lo[15:0] Figure 16-8. Timer Counter Registers 16-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 697: Timer Modes
IRQx OVF_ERRx after two cycles. The Timer Counter register is not TIMERx_STATUS SCLK altered. Note that after reset, the timer registers are all 0. ADSP-BF535 Blackfin Processor Hardware Reference 16-13...
Page 698: Pulse Width Modulation (Pwm) Waveform Generation
Therefore, must always be written after TIMERx_WIDTH_LO changing . When the value is not TIMERx_PERIOD TIMERx_WIDTH_LO subject to change, the ISR may read back the current value of and write it again. TIMERx_WIDTH_LO 16-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 699 In PWM applications, the software may need to update period and width values while the timer is running. To guarantee coherency between Timer Period and Timer Width registers, a buffer mechanism is used. ADSP-BF535 Blackfin Processor Hardware Reference 16-15...
Page 700 If an application forbids single misaligned PWM patterns, the procedure illustrated in Figure 16-10 can be used. It alters the period value tempo- rarily and restores the original period value the very next PWM cycle in order to obtain constant PWM periods. 16-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 701: Single Pulse Generation
TMRx PULSE_HI  The active low pulse configuration is not recommended, since the pin is always driven low when the timer is not running, TMRx regardless of the bit. PULSE_HI ADSP-BF535 Blackfin Processor Hardware Reference 16-17...
Page 702: Pulse Width Count And Capture Mode (Wdth_Cap)
WDTH_CAP mode. Once a pulse width event (trailing edge) has been detected and properly latched, the width registers do not update anymore unless the bit is cleared by software. The IRQx period registers still update every time a leading edge is detected. 16-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 703: Autobaud Detection
UART operation (all are derived from the phase-locked loop (PLL) clock), the pulse widths can be used to calculate the baud-rate divider for the UART. To determine the UART baud rate, use this equation: DIVISOR = TIMERx_WIDTH/(16 x (Number of captured UART bits)) ADSP-BF535 Blackfin Processor Hardware Reference 16-19...
Page 704 6, as shown in Figure 16-12. Since this period enclosed 8 bits, apply the formula:  DIVISOR = TIMERx_PERIOD/(16 STO P P er io d Figure 16-12. Autobaud Detection Character 0x40 16-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 705: External Event Counter Mode (Ext_Clk)
MMRs, the Timer Control register ( ), the TCNTL Timer Count register ( ), the Timer Period register ( ), and TCOUNT TPERIOD the Timer Scale register ( TSCALE Figure 16-13 provides a block diagram of the core timer. ADSP-BF535 Blackfin Processor Hardware Reference 16-21...
Page 706: Core Timer Control Register (Tcntl)
When is set, the core timer may TMPWR then be enabled by setting the bit in the register. TMREN TCNTL  Hardware behavior is undefined if is set when = 0. TMREN TMPWR 16-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 707: Core Timer Count Register (Tcount)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFE0 300C Reset = Undefined Count Value[31:16] 15 14 13 12 11 10 Count Value[15:0] Figure 16-15. Core Timer Count Register ADSP-BF535 Blackfin Processor Hardware Reference 16-23...
Page 708: Core Timer Period Register (Tperiod)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFE0 3008 Reset = Undefined 15 14 13 12 11 10 Scale Value Figure 16-17. Core Timer Scale Register 16-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 709: Watchdog Timer
To prevent the event from being generated, software must reload the count value from WDOG_CNT by executing a write (of any value) to , or WDOG_STAT WDOG_STAT must disable the watchdog timer in before the watchdog WDOG_CTL timer expires. ADSP-BF535 Blackfin Processor Hardware Reference 16-25...
Page 710: Watchdog Count Register (Wdog_Cnt)
WDOG_STAT software sets the value of at initialization, then periodically WDOG_CNT writes to before the timer expires. This reloads the timer with WDOG_STAT the value from and prevents generation of the selected event. WDOG_CNT 16-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 711: Watchdog Control Register (Wdog_Ctl)
TMR_EN[3:0] Writing any value other than the disable value into this field enables the watchdog timer. This multibit disable key minimizes the chance of inad- vertently disabling the watchdog timer. ADSP-BF535 Blackfin Processor Hardware Reference 16-27...
Page 712 TMR_EN[3:0] 0000-1000, 1110-1111 - Counter enabled 1101 - Counter disabled Figure 16-20. Watchdog Control Register  When the processor is in Emulation mode, the watchdog timer will not decrement even if it is enabled. 16-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 713 The 255-day counter is incremented each day at midnight (0 hours, 0 minutes, 0 seconds). The RTC can generate an interrupt once per second, once per minute, and once per day. ADSP-BF535 Blackfin Processor Hardware Reference 17-1...
Page 714: Rtc Programming Model
RTC interrupt management capability. Note that software cannot disable the RTC counting function. However, all RTC interrupts can be disabled, or masked. The RTC state can be read via the system MMR status registers at any time. 17-2 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 715 RTC clock. Since the value is registered into the actual register on the second clock edge after the write RTC_STAT occurs, adding two seconds to the real time before writing accounts for the synchronization delay. ADSP-BF535 Blackfin Processor Hardware Reference 17-3...
Page 716 RTC_ALARM out of reset is the same as the value written to . Wait RTC_ALARM RTC_STAT for the writes to complete on these registers before using the flags and interrupts associated with their values. 17-4 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 717 • Valid only after the hour field in is valid. Use the RTC_STAT Write Complete and Write Pending Status flags or inter- rupts to validate the value before using this flag RTC_STAT value or enabling the interrupt. ADSP-BF535 Blackfin Processor Hardware Reference 17-5...
Page 718 To avoid these potential errors, initialize the RTC during startup and do not dynamically alter the state of the pres- caler during normal operation. 17-6 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 719: Interrupts
The day counter value is incremented every day at midnight to record how many days have elapsed since it was last modified. Its value does not corre- spond to a particular calendar day. ADSP-BF535 Blackfin Processor Hardware Reference 17-7...
Page 720: Rtc Interrupt Control Register (Rtc_Ictl)
1 Hz clock ticks. The 24-hour interrupt occurs once per 24-hour period (at midnight). Any of these interrupts can generate a wake-up request to the processor. All bits are read/write. This register, shown in Figure 17-2, is cleared at reset. 17-8 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 721: Rtc Interrupt Status Register (Rtc_Istat)
Values are cleared by writing a 1 to the respective bit location, except for the Write Pending Status bit, which is read-only. Writes of 0 to any bit of the register have no effect. This register is cleared at reset. ADSP-BF535 Blackfin Processor Hardware Reference 17-9...
Page 722: Rtc Stopwatch Count Register (Rtc_Swcnt)
0. The counter stops counting at this point and does not resume counting until a new value is written to . The register can be RTC_SWCNT programmed to any value between 0 and 255 minutes. 17-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 723: Rtc Alarm Register (Rtc_Alarm)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 1410 Reset = Undefined Hours (0–23) (0-255) 15 14 13 12 11 10 Seconds (0–59) Minutes (0-59) Figure 17-5. RTC Alarm Register ADSP-BF535 Blackfin Processor Hardware Reference 17-11...
Page 724: Rtc Enable Register (Rtc_Fast)
RTC Enable Register (RTC_FAST) 15 14 13 12 11 10 0xFFC0 1414 Reset = Undefined Prescaler Enable Figure 17-6. RTC Enable Register 17-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 725 The next four regions are dedicated to supporting asynchronous memo- ries. Each asynchronous memory region can be independently programmed to support different memory device characteristics. Each region has its own memory-select output pin from the EBIU. ADSP-BF535 Blackfin Processor Hardware Reference 18-1...
Page 726 SDRAM Memory Bank 0 (16 MB-128 MByte) 0x0000 0000 * This reserved block does not exist if all four blocks of SDRAM are configured to their full 128 MByte size. Figure 18-1. External Memory Map 18-2 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 727: Block Diagram
The Asynchronous Memory Controller (AMC) and the SDRAM Controller (SDC) effectively arbitrate for the shared pin resources. ADSP-BF535 Blackfin Processor Hardware Reference 18-3...
Page 728: Internal Memory Interfaces
DMA bus or mastered by the MemDMA controller. • External Mastered Bus (EMB), mastered by the PCI bridge. • Peripheral Access Bus (PAB), mastered by the SBIU on behalf of system MMR requests from the core or from the PCI master. 18-4 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 729: Ebiu Arbitration
Address Bus ADDR[19:2] AMC Byte Enable 3/SDC Data Mask 3/Address 1 ABE[3]/SDQM[3]/ADDR[1] AMC Byte Enables/SDC Data Masks ABE[2:0]/SDQM[2:0] AMC System Clock Output/SDC Clock 1 CLKOUT/SCLK[1] No other signals are multiplexed between the two controllers. ADSP-BF535 Blackfin Processor Hardware Reference 18-5...
Page 730 Asynchronous Memory Output Enable. In most cases, the pin should be connected to the pin of an external memory-mapped asynchronous device. Refer to ADSP-BF535 Blackfin Embedded Processor Data Sheet for specific timing informa- tion between the signals to deter- mine which interface signal should be used in your system.
Page 731: Ebiu Programming Model
. Connect to the SCLK[0] SDRAM’s pin. EBIU Programming Model This section describes the programming model of the EBIU. This model is based on system memory-mapped registers (MMRs) used to program the EBIU. ADSP-BF535 Blackfin Processor Hardware Reference 18-7...
Page 732: Error Detection
EAB or EMB bus error signal for these error conditions: • Any access to reserved memory space • Any access to a disabled external memory bank 18-8 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 733: Asynchronous Memory Interface
Table 18-4. Asynchronous Memory Bank Address Range Memory Bank Select Address Start Address End 2C00 0000 2FFF FFFF AMS[3] 2800 0000 2BFF FFFF AMS[2] 2400 0000 27FF FFFF AMS[1] 2000 0000 23FF FFFF AMS[0] ADSP-BF535 Blackfin Processor Hardware Reference 18-9...
Page 734: Asynchronous Memory Address Decode
AMC is in use. The register should be the last control EBIU_AMGCTL register written to when configuring the ADSP-BF535 processor to access external memory-mapped asynchronous devices. Figure 18-3 shows the Asynchronous Memory Global Control register. 18-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 735 16-bit accesses on the external bus. All 8-bit and 16-bit requests are still processed with a single external transaction. When 32-bit packing is enabled, all 32-bit transactions are processed with a single transfer. ADSP-BF535 Blackfin Processor Hardware Reference 18-11...
Page 736 Each of these parameters can be programmed in terms of EBIU clock cycles. In addition, there are minimum values for these parameters:  • Setup 1 cycle.  • Read Access 1 cycle.  • Write Access 1 cycle.  • Hold 0 cycles. 18-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 737: Ardy Input Control
ARDY enable is asserted, does not need to be driven by default. For more ARDY information, see “Adding Additional Wait States” on page 18-26. ADSP-BF535 Blackfin Processor Hardware Reference 18-13...
Page 738 01 - 1 cycle 10 - 2 cycles for bank transition 10 - 2 cycles 11 - 3 cycles for bank transition 11 - 3 cycles Figure 18-4. Asynchronous Memory Bank Control 0 Register 18-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 739 01 - 1 cycle. 10 - 2 cycles for bank transition. 10 - 2 cycles. 11 - 3 cycles for bank transition. 11 - 3 cycles. Figure 18-5. Asynchronous Memory Bank Control 1 Register ADSP-BF535 Blackfin Processor Hardware Reference 18-15...
Page 740: Programmable Timing Characteristics
• At the beginning of the read access period and after the setup cycle, asserts. • At the beginning of the hold period, read data is sampled on the rising edge of . The pin deasserts after this rising edge. CLKOUT 18-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 741 Hold 1 cycle 3 cycles 2 cycles 1 cycle 1 cycle 3 cycles 2 cycles 1 cycle SCLK[1]/ CLKOUT AMS [x ] ABE[3:0] ADDR [25:2] DATA [31:0] Figure 18-6. Core-Initiated Asynchronous Read Bus Cycles ADSP-BF535 Blackfin Processor Hardware Reference 18-17...
Page 742: Asynchronous Writes
= 1 cycle, write access = 2 cycles, hold = 0 cycles, and transition time = 1 cycle. 18-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 743 , the address bus, data buses, AMS[x] become valid. ABE[3:0] • At the beginning of the write access period, asserts. • At the beginning of the hold period, deasserts. • After the hold period, deasserts. AMS[x] ADSP-BF535 Blackfin Processor Hardware Reference 18-19...
Page 744 AMS[x] Write Write Access Access Setup Setup 1 cycle 2 cycles 1 cycle 2 cycles SCLK[1]/ CLKOUT AMS [x] ABE[3:0] ADDR [25:2] DATA [31:0] Figure 18-8. High Speed Core-Initiated Asynchronous Write Bus Cycles 18-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 745: Asynchronous Writes Followed By Reads
The second asynchronous read bus cycle proceeds as: • At the start of the setup period, , the address bus, and AMS[x] become valid, and asserts. ABE[3:0] • At the beginning of the read access period, asserts again. ADSP-BF535 Blackfin Processor Hardware Reference 18-21...
Page 746 • At the end of the hold period, deassert. AMS[x] • Unless another read of the same memory bank is queued internally, the AMC appends the programmed number of memory transition time cycles. 18-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 747: Asynchronous Accesses By Memdma
Asynchronous Accesses by MemDMA External memory accesses are also caused by MemDMA. MemDMA transfers to external memory space occur in bursts of 8 accesses. There are cycles inserted between bursts due to internal bus transactions. SCLK ADSP-BF535 Blackfin Processor Hardware Reference 18-23...
Page 748: Asynchronous Reads
AMS[x] action is the last in the burst, otherwise remain AMS[x] asserted for the setup period of the next read. AMS [x ] Figure 18-10. MemDMA Read With 3-Cycle Hold 18-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 749 EBIU clock. The pin deasserts after this ris- ing edge. • At the end of the hold period, deassert. AMS[x] AMS [x ] Figure 18-11. MemDMA Read With 1-Cycle Hold ADSP-BF535 Blackfin Processor Hardware Reference 18-25...
Page 750: Asynchronous Writes
Read data is latched on the clock edge after is sampled asserted. The read- or write-enable ARDY remains asserted for one clock cycle after is sampled asserted. An ARDY 18-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 751 Programmed Read Access Setup Access Extended Hold 2 cycles 4 cycles 3 cycles 1 cycle Data Ready Sampled Latched CLKOUT [3:0] ADDR [25:2] Address DATA [31:0] Read ARDY Figure 18-13. Inserting Wait States Using ARDY ADSP-BF535 Blackfin Processor Hardware Reference 18-27...
Page 752: Sdram Controller (Sdc)
• Supports up to two x64 DIMM modules, or up to four x32 DIMM modules. • Supports up to 512 MB total array size with 128 MB of SDRAM on each of the four external SDRAM banks. 18-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 753: Definition Of Terms
When the Bank Activate command is issued to the SDRAM, the SDRAM opens a new row address in the dedicated bank. The memory in the open internal bank and row is referred to as the open page. Therefore, only one ADSP-BF535 Blackfin Processor Hardware Reference 18-29...
Page 754 SDRAM during the SDRAM power-up sequence.  Since the SDRAM burst length is always programmed to be 1, the burst type does not matter. However, the SDC always sets the burst type to sequential-accesses-only during the SDRAM power-up sequence. 18-30 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 755 There are several internal memory banks on a given SDRAM row. An internal bank in a specific row cannot be activated (opened) until the pre- vious internal bank in that row has been precharged. ADSP-BF535 Blackfin Processor Hardware Reference 18-31...
Page 756 The page size can be calculated for 32-bit and 16-bit SDRAM banks with these formulas: (CAW + 2) • 32-bit SDRAM banks: page size = 2 18-32 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 757 SDRAM devices on one or both sides. DIMMs are populated with sufficient SDRAM to provide either 32-bit or 64-bit data paths, with some configurations supporting additional data bits for parity protection. ADSP-BF535 Blackfin Processor Hardware Reference 18-33...
Page 758 SDRAM Memory Global TRAS Control register ( ) is 4 bits wide and can be programmed to EBIU_SDGCTL be 1 to 15 clock cycles long. “Selecting the Bank Activate Command Delay (TRAS)” on page 18-47. 18-34 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 759 Required delay between issuing successive Bank Activate commands to the same SDRAM internal bank. This delay is not directly programmable. The t delay must be satisfied by programming the fields TRAS RP  to ensure that t ADSP-BF535 Blackfin Processor Hardware Reference 18-35...
Page 760 Auto-Refresh command. This delay is not directly programmable and is assumed to be equal to t . The t delay must be satisfied by program- RP  ming the t and t fields to ensure that t 18-36 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 761 External Bus Interface Unit SDRAM Memory Global Control Register (EBIU_SDGCTL) The SDRAM Memory Global Control register includes all programmable parameters associated with the SDRAM access timing and configuration. ADSP-BF535 Blackfin Processor Hardware Reference 18-37...
Page 762 SDRAM Controller (SDC) Figure 18-14 shows the SDRAM Global Control register bit definitions. 18-38 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 763 0 - Prefetch does not have priority SDRAM prefetch enable over AMC requests 0 - Prefetch disabled 1 - Prefetch has priority over AMC 1 - Prefetch enabled requests Figure 18-14. SDRAM Memory Global Control Register ADSP-BF535 Blackfin Processor Hardware Reference 18-39...
Page 764 All timing parameters must be written with valid values based on the clock frequency and the timing specifications of the SDRAM before any access to SDRAM address space, including the power-up sequence. 18-40 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 765 (initialization) sequence. If the bit is set to 1, the SDC does a Precharge All command, followed by a Load Mode Register command, and then does eight Auto-Refresh cycles. If the bit is cleared, the SDC ADSP-BF535 Blackfin Processor Hardware Reference 18-41...
Page 766 1. Using this setting adds a EBUFE cycle of data buffering to read and write accesses. See “Setting the SDRAM Buffering Timing Option (EBUFE)” on page 18-45 for more information about the bit. EBUFE 18-42 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 767 SCTLE SCK1E SCLK[1] enabled independently by the enable in the AMC ( in the CLKOUT AMCKEN register). EBIU_AMGCTL If the system does not use SDRAM, both should be 0. SCTLE SCK1E ADSP-BF535 Blackfin Processor Hardware Reference 18-43...
Page 768: Entering And Exiting Self-Refresh Mode (Srfs)
SDC delays issuing the Self-Refresh command until it completes the pending SDRAM access and any subse- quent pending access requests. Refer to “SDC Commands” on page 18-75 for more information. 18-44 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 769 In read accesses, the SDRAM controller samples data one cycle later to account for the one-cycle delay added by the external buffer regis- ters. When external buffering timing is enabled, the latency of all accesses is increased by one cycle. ADSP-BF535 Blackfin Processor Hardware Reference 18-45...
Page 770: Selecting The Cas Latency Value (Cl)
2 clock cycles CL = 10 3 clock cycles CL = 11 Generally, the frequency of operation determines the value of the CAS latency. For specific information about setting this value, consult the SDRAM device documentation. 18-46 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 771: Sdqm Operation
Self-Refresh mode for a period of time of at least t The t and t values define the t , and t values. See the , and t descriptions on page 18-36 for more information. ADSP-BF535 Blackfin Processor Hardware Reference 18-47...
Page 772: Selecting The Precharge Delay (Trp)
SDRAM Memory Global Control register ) select the t value. Any value between 1 and 7 cycles EBIU_SDGCTL SCLK may be selected. For example: No effect TRP = 000 1 clock cycle TRP = 001 18-48 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 773: Selecting The Write To Precharge Delay (Twr)
SDRAM; however, note that all external banks use the same access timing parameters, as defined in the SDRAM Memory Global Control register ). The register should be programmed before EBIU_SDGCTL EBIU_SDBCTL power-up and should be changed only when the SDC is idle. ADSP-BF535 Blackfin Processor Hardware Reference 18-49...
Page 774 00 - 8 bits SDRAM external bank 1 enable 01 - 9 bits 0 - Disabled 10 - 10 bits 1 - Enabled 11 - 11 bits Figure 18-15. SDRAM Memory Bank Control Register 18-50 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 775 Bank Page SDRAM Config Width Size Addr Size Address Address Column Byte Size Width Bits Mbyte Width kbyte Address Address Mbit Bits Chips (CAW IA[26:15] IA[14:13] IA[12:2] IA[1:0] 128 IA[26:14] IA[13:12] IA[11:2] IA[1:0] 256 ADSP-BF535 Blackfin Processor Hardware Reference 18-51...
Page 776 Not Supported - Reserved IA[24:13] IA[12:11] IA[10:2] IA[1:0] 64 Not Supported - Reserved IA[23:12] IA[11:10] IA[9:2] IA[1:0] 64 IA[26:14] IA[13:12] IA[11:1] IA[0] Not Supported - Reserved IA[25:14] IA[13:12] IA[11:1] IA[0] IA[25:13] IA[12:11] IA[10:1] IA[0] 18-52 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 777: Sdram Control Status Register (Ebiu_Sdstat)
SDC control parameters or as a debug aid. The error bits of this register are sticky. Once an error bit has been set, software must explicitly write a 1 to the bit to clear it. ADSP-BF535 Blackfin Processor Hardware Reference 18-53...
Page 778: Sdram Refresh Rate Control Register (Ebiu_Sdrrc)
Auto-Refresh command to all external SDRAM banks. Write the value to the register before the SDRAM RDIV EBIU_SDRRC power-up sequence is triggered. Change this value only when the SDC is idle. 18-54 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 779 SDRAM cycle is active, the SDRAM refresh rate specification is guaranteed to be met. The result from the equation should always be rounded down to an integer. ADSP-BF535 Blackfin Processor Hardware Reference 18-55...
Page 780: Sdram External Bank Address Decode
18-7. If every SDRAM bank is 128 MB, the SDRAM address space is fully populated. If any bank is less than 128 MB, the address space after bank3 is referred to as “unpopulated/reserved” space. 18-56 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 781 1. bank_x_start_addr[31:29] = 000 and bank_x_start_addr[23:0] = all 0’s 2. If there is a carry out on the reserved space start address, then the SDRAM address space is fully populated and therefore, no bus error from unpopulated/reserved space is possible. ADSP-BF535 Blackfin Processor Hardware Reference 18-57...
Page 782 00101 00000 unpopulated_start_addr[28:24] = bank0 00010 bank1 00010 00001 bank2 00100 bank3 00101 Figure 18-18. Bank Start Address Calculation The start addresses for the SDRAM banks and reserved spaces are calcu- lated as: 18-58 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 783: Sdram Address Mapping
This mapping is based on the parameters programmed into EBxSZ EBxCAW the SDRAM Memory Bank Control register, and the bit in the X16DE register. EBIU_SDGTL ADSP-BF535 Blackfin Processor Hardware Reference 18-59...
Page 784: Bit Wide Sdram Address Muxing
18-67. 32-Bit Wide SDRAM Address Muxing Table 18-9, Table 18-10, Table 18-11, and Table 18-12 show address muxing for 32-bit wide SDRAM banks using SDRAMs with 8, 9, 10, or 11 column address pins. 18-60 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 785 IA[14] IA[4] A[2] ADDR[3] IA[13] IA[3] A[1] ADDR[2] IA[12] IA[2] A[0] ADDR[19] IA[11] IA[11] BA[1] ADDR[18] IA[10] A[10] BA[0] Possible configurations:   2 chips: 64 Mb - 1 M 4 banks (16 MB) ADSP-BF535 Blackfin Processor Hardware Reference 18-61...
Page 786 2 chips: 256 Mb - 4 M 4 banks (64 MB)   2 chips: 128 Mb - 2 M 4 banks (32 MB)   4 chips: 64 Mb - 2 M 4 banks (32 MB) 18-62 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 787 2 chips: 512 Mb - 8 M 4 banks (128 MB)   2 chips: 128 Mb - 4 M 4 banks (64 MB)   2 chips: 64 Mb - 4 M 4 banks (64 MB) ADSP-BF535 Blackfin Processor Hardware Reference 18-63...
Page 788 IA[17] IA[4] A[2] ADDR[3] IA[16] IA[3] A[1] ADDR[2] IA[15] IA[2] A[0] ADDR[19] IA[14] IA[14] BA[1] ADDR[18] IA[13] A[13] BA[0] Possible configurations:   8 chips: 128 Mb - 8 M 4 banks (128 MB) 18-64 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 789: Bit Wide Sdram Address Muxing
1 chip: 256 Mb - 4 M 4 banks (32 MB)   1 chip: 128 Mb - 2 M 4 banks (16 MB)   2 chips: 64 Mb - 2 M 4 banks (16 MB) ADSP-BF535 Blackfin Processor Hardware Reference 18-65...
Page 790 2 chips: 256 Mb - 8 M 4 banks (64 MB)   2 chips: 128 Mb - 4 M 4 banks (32 MB)   4 chips: 64 Mb - 4 M 4 banks (32 MB) 18-66 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 791: Data Mask (Sdqm[3:0]) Encodings
SDQM[3:0] writes to bytes that are not accessed. Table 18-16 shows the SDQM[3:0] encodings for 32-bit wide SDRAM banks based on the internal transfer address bits and the transfer size. IA[1:0] ADSP-BF535 Blackfin Processor Hardware Reference 18-67...
Page 792 SDRAM banks are 16-bit wide). This means for 32-bit SDRAM banks, are all zeros, and for 16-bit SDRAM banks are zeros, SDQM[3:0] SDQM[1:0] is 1, and outputs SDQM[2] SDQM[3] IA[1]. The pin configurations in Table 18-16 are internally set up and not programmable. 18-68 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 793: Sdram Banks
Table 18-17. SDQM[1:0] Encodings During Writes for 16-bit SDRAM Banks Internal Address Internal Transfer Size IA[0] byte 2 bytes 4 bytes SDQM[1]=1 SDQM[1]=0 SDQM[1]=0 SDQM[0]=0 SDQM[0]=0 SDQM[0]=0 SDQM[1]=0 SDQM[0]=1 Note: outputs always outputs 1 for 16-bit SDQM[3] IA[1] SDQM[2] SDRAM banks. ADSP-BF535 Blackfin Processor Hardware Reference 18-69...
Page 794: Sdc Operation
(as specified by the SDRAM). In order to set up the SDC and start the SDRAM power-up sequence for the SDRAMs, the SDRAM Refresh Rate Control register ( ), the SDRAM Memory Bank EBIU_SDRRC Control register ( ), and SDRAM Memory Global Control EBIU_SDBCTL 18-70 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 795 PSSE Note if is disabled, any access to SDRAM address space generates an SCTLE internal bus error and the access does not occur externally. For more infor- mation, see “Error Detection” on page 18-8. ADSP-BF535 Blackfin Processor Hardware Reference 18-71...
Page 796: Read Buffer (Prefetch) Operation
), but the AMC is not requesting use of PFP = 0 the shared external pins. • The successive memory line is in the page which is currently open. • No Auto-Refresh or Self-Refresh request is pending. 18-72 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 797 (a read buffer miss), the read buffer data is invalidated, the accesses required to service the cache line fill are launched, and then prefetches of the next line begin. ADSP-BF535 Blackfin Processor Hardware Reference 18-73...
Page 798 For example, if a cache line fill access starts with word 5, then the next prefetch would be from word 5 in the following line. 18-74 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 799: Sdc Commands
• Self-Refresh: Places the SDRAM in self-refresh mode, in which the SDRAM powers down and controls its refresh operations internally. • NOP/Command Inhibit: No operation. Table 18-18 shows the SDRAM pin state during SDC commands. ADSP-BF535 Blackfin Processor Hardware Reference 18-75...
Page 800: Precharge Command
For page miss reads or writes, only the external bank to be accessed by the read or write is precharged. For Auto-Refresh and Self-Refresh, all external SDRAM banks are precharged at one time. 18-76 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 801: Bank Activate Command
• Bits 14-7, always zero While executing the Load Mode Register command, the unused address pins are set to zero. During the two cycles following Load Mode Reg- SCLK ister, the SDC issues only NOP commands. ADSP-BF535 Blackfin Processor Hardware Reference 18-77...
Page 802: Read/Write Command
Auto-Refresh command is given. The SDC generates an Auto-Refresh command after the SDC refresh counter times out. The value in the RDIV SDRAM Refresh Rate Control register must be set so that all addresses are 18-78 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 803: Self-Refresh Command
Self-Refresh mode. However, software may disable the clocks by clearing bits in . The application software should SCTLE SCK1E EBIU_SDGCTL ensure that all applicable clock timing specifications are met before the transfer to SDRAM address space which causes the controller to exit ADSP-BF535 Blackfin Processor Hardware Reference 18-79...
Page 804: No Operation/Command Inhibit Commands
For other parameters, the SDC assumes: • Bank Cycle Time: t • Refresh Cycle Time: t • Exit Self-Refresh Time: t • Load Mode Register to Activate Time: t cycles SCLK 18-80 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 805: Sdram Performance
) = 2 cycles ( TRP = 2 • RAS to CAS delay (t ) = 2 cycles ( TRCD = 2 • Active command time (t ) = 5 cycles ( TRAS = 5 ADSP-BF535 Blackfin Processor Hardware Reference 18-81...
Page 806 8 words/17 cycles DMA Burst Write (8 words) Write Page Miss 8 words/20 cycles Single Read Read Page Miss 1 word/10 cycles Single Write Write Page Miss 1 word/6 cycles 1 Page Miss Penalty = t 18-82 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 807 ) = 2 cycles ( TRP = 2 • RAS to CAS delay (t ) = 2 cycles ( TRCD = 2 • Active command time (t ) = 5 cycles ( TRAS = 5 ADSP-BF535 Blackfin Processor Hardware Reference 18-83...
Page 808 8 words/25 cycles DMA Burst Write (8 words) Write Page Miss 8 words/24 cycles Single Read Read Page Miss 1 words/11 cycles Single Write Write Page Miss 1 words/7 cycles 1 Page-Miss Penalty = t 18-84 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 809 EBUFE = 1 CL = 11 • For N = 16 to 14, N half word hit: 8 words/8 cycles • For N = 13 to 0, N half word hit: 8 words/(23 – N) cycles ADSP-BF535 Blackfin Processor Hardware Reference 18-85...
Page 810 SDRAM Controller (SDC) 18-86 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 811 External Bus Interface Unit ADSP-BF535 Blackfin Processor Hardware Reference 18-87...
Page 812 SDRAM Controller (SDC) 18-88 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 813: Pin Descriptions
Pin Descriptions Refer to ADSP-BF535 Blackfin Embedded Processor Data Sheet for pin information, including pin numbers for the 260-Lead PBGA package. Recommendations for Unused Pins Refer to ADSP-BF535 Blackfin Embedded Processor Data Sheet for detailed pin descriptions.
Page 814: Resetting The Processor
CLKIN during normal operation. The processor uses the clock input ( ) to CLKIN generate on-chip clocks. These include the core clock ( ) and the CCLK peripheral clock ( SCLK 19-2 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 815: Managing Core And System Clocks
Ensure that the system permits the MSELx MSELx pins to stabilize to a valid multiplier value in compli- SSELx ance with the timing for in the data sheet. RESET ADSP-BF535 Blackfin Processor Hardware Reference 19-3...
Page 816 To avoid this condi- tion, use the pins to select a lower processor clock ( MSEL CCLK speed upon reset. Adjust the clock to the desired operating speed in the software. 19-4 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 817: Configuring And Servicing Interrupts
However, these system interrupts can be remapped via the System Interrupt Assignment Registers ( ). For more information, see “System Interrupt Assign- SIC_IARx ment Registers (SIC_IARx)” on page 4-29. ADSP-BF535 Blackfin Processor Hardware Reference 19-5...
Page 818: Semaphores
In multithreaded systems, the instruction is required to maintain semaphore consistency. TESTSET To ensure that the store operation is flushed through any store or write buffers, issue an immediately after semaphore release. SSYNC 19-6 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 819: Example Code For Query Semaphore
*/ R0.L = THREAD_ID ; B[P0]=R0 ; /* When done using shared resource, write a zero-byte to [P0] */ R0 = 0 ; B[P0] = R0 ; SSYNC ; ADSP-BF535 Blackfin Processor Hardware Reference 19-7...
Page 820: Data Delays, Latencies And Throughput
ADSP-BF535 processor to act as a slave on the PCI bus. USB Device Connection The ADSP-BF535 processor’s USB peripheral supports USB device mode, but not USB host mode. For USB device operation, use an external USB buffer/driver chip and oscillator. 19-8 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 821: External Memory Design Issues
Note this application requires that the 16-bit packing mode be enabled for this bank of memory. Otherwise, the programming model must ensure that every other 16-bit memory location is accessed starting on an even (byte address[1:0]=00) 16-bit address. ADSP-BF535 Blackfin Processor Hardware Reference 19-9...
Page 822: Avoiding Bus Contention
This feature allows software to set the number of clock cycles between these types of accesses on a bank by bank basis. Minimally, the EBIU provides one cycle for the transition to occur. 19-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 823: Supported Sdram Configurations
4banks   4banks   4banks   4banks   4banks   4banks   4banks   4banks   4banks   4banks   4banks   4banks ADSP-BF535 Blackfin Processor Hardware Reference 19-11...
Page 824: Example Sdram Interfaces
SDRAM chip enables. Since the data bus is only 32 bits wide at the most, 64-bit DIMMs must be connected as two banks. Note the range of num- bers for the signals on the SDRAM DIMM may not match DATA the corresponding range on the ADSP-BF535 processor. 19-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 825 64 MB DIMM. The DIMM is connected to the ADSP-BF535 processor as bank 0 ( ) and bank 1 ( ) with each SMS[0] SMS[1] bank having 32 MB. ADSP-BF535 Blackfin Processor Hardware Reference 19-13...
Page 826: High Frequency Design Considerations
Point-to-Point Connections on Serial Ports Although the processor’s serial ports may be operated at a slow rate, the output drivers still have fast edge rates and for longer distances may require source termination. 19-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 827: Signal Integrity
“Recommended Reading” on page 19-17 for suggestions on transmission-line termination. Also, see ADSP-BF535 Blackfin Embed- ded Processor Data Sheet for output drivers’ rise and fall time data. Signal Integrity The capacitive loading on high-speed signals should be reduced as much as possible.
Page 828: Decoupling Capacitors And Ground Planes
4 inches of ground lead causes ringing to be seen on the displayed trace and makes the signal appear to have excessive overshoot and undershoot. To see the signals accurately, a 1 GHz or better sampling oscilloscope is needed. 19-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 829: Recommended Reading
COMPONENT (TOP) SIDE OF BOARD, BENEATH DSP PACKAGE BOARD, AROUND DSP PACKAGE Figure 19-7. Bypass Capacitor Placement Recommended Reading High-Speed Digital Design: A Handbook of Black Magic, Johnson & Gra- ham, Prentice Hall, Inc., ISBN 0-13-395724-1. ADSP-BF535 Blackfin Processor Hardware Reference 19-17...
Page 830 • High-speed Properties of Logic Gates • Measurement Techniques • Transmission Lines • Ground Planes & Layer Stacking • Terminations • Vias • Power Systems • Connectors • Ribbon Cables • Clock Distribution • Clock Oscillators 19-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 831: Watchpoint Unit
By monitoring the addresses on both the instruction bus and the data bus, the Watchpoint Unit provides several mechanisms for examining program behavior. After counting the number of times a particular address is matched, the unit schedules an event based on this count. ADSP-BF535 Blackfin Processor Hardware Reference 20-1...
Page 832 , are decremented on each WPIACNT[5:0] match. The six Watchpoint Instruction Address registers may be further grouped into three ranges of instruction-address-range watchpoints. The ranges are identified by the addresses in WPIA0 WPIA1 WPIA2 WPIA3, WPIA4 WPIA5 20-2 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 833 If the bit is 0, then WPAND an event is triggered when any of the enabled watchpoints or watchpoint ranges match. ADSP-BF535 Blackfin Processor Hardware Reference 20-3...
Page 834: Instruction Watchpoints
The watchpoint registers are used to trigger an exception at the start addresses of the earlier code. The exception routine then vectors to the location in memory that contains the new code. 20-4 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 835: Watchpoint Instruction Address Registers (Wpiax)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ments, see Reset = Undefined Table 20-4. WPIA (Instruction Address)[30:15] 15 14 13 12 11 10 WPIA (Instruction Address)[14:0] Figure 20-1. Watchpoint Instruction Address Registers ADSP-BF535 Blackfin Processor Hardware Reference 20-5...
Page 836 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ments, see Reset = Undefined Table 20-5. 15 14 13 12 11 10 WPIACNT (Count Value)[15:0] Figure 20-2. Watchpoint Instruction Address Count Registers 20-6 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 837 Figure 20-3 shows the upper half of the register, and Figure 20-4 shows the lower half of the register. For more information about the bits in this register, see “Instruction Watchpoints” on page 20-4. ADSP-BF535 Blackfin Processor Hardware Reference 20-7...
Page 838 1 - Enable instruction address instruction address counter 5 watchpoint, WPIA5 WPICNTEN4 0 - Disable watchpoint instruction address counter 4 1 - Enable watchpoint instruction address counter 4 Figure 20-3. Watchpoint Instruction Address Control Register [31:16] 20-8 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 839 1 - Match on WPIA0 causes an 0 - Match on WPIA1 causes an emulation event exception event 1 - Match on WPIA1 causes an emulation event Figure 20-4. Watchpoint Instruction Address Control Register [15:0] ADSP-BF535 Blackfin Processor Hardware Reference 20-9...
Page 840: Data Address Watchpoints
Determines whether an event is caused by an address within the range iden- tified or outside the range.  Note Data address watchpoints always trigger emulation events.  To enable the Data address watchpoints, the bit of the WPPWR register must be set to 1. WPIACTL 20-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 841: Watchpoint Data Address Registers (Wpdax)
Load this register with a value that is one WPDAx WPDACNTx less than the number of times the watchpoint must match before trigger- ing an event. ADSP-BF535 Blackfin Processor Hardware Reference 20-11...
Page 842 15 14 13 12 11 10 WPDACNT (Count Value)[15:0] Figure 20-6. Watchpoint Data Address Count Value Registers Table 20-9. Watchpoint Data Address Count Value Register MMR Assignments Register Name Memory-Mapped Address WPDACNT0 0xFFE0 7180 WPDACNT1 0xFFE0 7184 20-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 843 WPDA0 to WPDA1 range 1 - Enable watchpoint 11 - Watch addresses on either DAG0 or DAG1 data address counter 1 on WPDA0 or on the WPDA0 to WPDA1 range Figure 20-7. Watchpoint Data Address Control Register ADSP-BF535 Blackfin Processor Hardware Reference 20-13...
Page 844: Watchpoint Status Register (Wpstat)
Because zero-overhead loops are not recorded in the trace buffer, this feature can be used to pre- vent trace overflow from loops that are nested four deep. 20-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 845 Trace Unit stack, which contains as many as sixteen entries. Each entry contains a pair of branch source and branch target addresses. A read of returns the newest entry first, starting with the branch destination. TBUF The next read provides the branch source address. ADSP-BF535 Blackfin Processor Hardware Reference 20-15...
Page 846: Trace Buffer Control Register (Tbufctl)
TBUFEN Trace Unit. Figure 20-9 shows the Trace Buffer Control register ( ). If TBUFCTL , then the Trace Unit does not record discontinuities in the TBUFOVF = 1 exception, NMI, and reset routines. 20-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 847: Trace Buffer Status Register (Tbufstat)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFE0 6004 Reset = Undefined 15 14 13 12 11 10 TBUFCNT[4:0] Number of valid discontinuities stored in the trace buffer Figure 20-10. Trace Buffer Status Register ADSP-BF535 Blackfin Processor Hardware Reference 20-17...
Page 848: Trace Buffer Register (Tbuf)
TBUF recording new discontinuities. Code to Recreate the Execution Trace in Memory Listing 20-1 provides code that can be used to recreate the entire execu- tion trace in memory. 20-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 849: Performance Monitoring Unit
In addition, events such as mispredictions and hold cycles can also be monitored. ADSP-BF535 Blackfin Processor Hardware Reference 20-19...
Page 850: Performance Monitor Counter Registers (Pfcntrx)
( ) take effect. Use the bits to enable or PFCENx PFCENx disable the performance monitors in User mode, Supervisor mode, or both. Use the bits to select the type of event triggered. PEMUSWx 20-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 851 Monitor 0 in Supervisor emulation event mode only PFMON0[7:0] 11 - Enable Performance Refer to Event Monitor table Monitor 0 in both User and (Table 20-11) Supervisor modes Figure 20-13. Performance Monitor Control Register ADSP-BF535 Blackfin Processor Hardware Reference 20-21...
Page 852: Event Monitor Table
Indirect branches 0x26 Mispredicted branches 0x27 Taken branches 0x28 Not taken branches 0x29 Total branches 0x2A Stalls because of CSYNC, SSYNC 0x2B EXCPT instructions 0x2C CSYNC, SSYNC instructions 0x2D Committed instructions 0x2E Interrupts taken 20-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 853 DAG0 & DAG1 bank conflicts 0x6E Scratch SRAM hits 0x6F DMA reads 0x70 DMA writes 0x71 LMU stalls in EX2 0x72 LMU stalls in EX3 0x73 LMU exceptions 0x74 Stall cycles because of store buffer cancels ADSP-BF535 Blackfin Processor Hardware Reference 20-23...
Page 854: Cycle Counter
This example shows how to turn on the cycle counter: r2 = 0 ; cycles = r2 ; cycles2 = r2 ; r2 = SYSCFG ; bitset(r2, 1) ; SYSCFG = r2 ; /* Insert code to be benchmarked */ 20-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 855: Product Identification Registers
) is a system MMR that contains the CHIPID product identification and revision fields for the ADSP-BF535 processor. The 32-bit DSP Device ID register ( ) is a core MMR that contains DSPID core identification and revision fields for the core. ADSP-BF535 Blackfin Processor Hardware Reference 20-25...
Page 856: Chip Id Register (Chipid)
CHIPID[31:28] • : part number 0x4000 CHIPID[27:12] • : Analog Devices, Inc., ID number 0xE5 – drop the CHIPID[11:1] MSB (parity) and set MSBs to 0 (no ID extension) in accordance with the JTAG standard: 0x065. • : set to 1...
Page 857: Dsp Device Id Register (Dspid)
“Chip Bus Hierarchy” on page 7-1. If a DMA channel does not behave as expected, these two registers provide a debug capability: • DMA Bus Control Comparator register ( DB_CCOMP • DMA Bus Address Comparator register ( DB_ACOMP ADSP-BF535 Blackfin Processor Hardware Reference 20-27...
Page 858: Dma Bus Control Comparator Register (Db_Ccomp)
0 - No interrupt generated CH (Compare Hit) - W1C on hit 0 - No match detected 1 - Interrupt generated on hit 1 - Match detected detect Figure 20-17. DMA Bus Control Comparator Register 20-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 859: Dma Bus Address Comparator Register (Db_Acomp)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0xFFC0 4884 Reset = 0x0000 0000 DMA Address[31:16] 15 14 13 12 11 10 DMA Address[15:0] Figure 20-18. DMA Bus Address Comparator Register ADSP-BF535 Blackfin Processor Hardware Reference 20-29...
Page 860 DMA Bus Debug Registers 20-30 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 861: L1 Data Memory Controller Registers
(DMEM_CONTROL)” on page 6-12 0xFFE0 0008 DCPLB_STATUS “DCPLB Status Register (DCPLB_STATUS)” on page 6-73 0xFFE0 000C DCPLB_FAULT_ADDR “DCPLB Fault Address Register (DCPLB_FAULT_ADDR)” on page 6-75 0xFFE0 0100 DCPLB_ADDR0 “DCPLB Address Registers (DCPLB_ADDRx)” on page 6-69 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 862 “DCPLB Address Registers (DCPLB_ADDRx)” on page 6-69 0xFFE0 0134 DCPLB_ADDR13 “DCPLB Address Registers (DCPLB_ADDRx)” on page 6-69 0xFFE0 0138 DCPLB_ADDR14 “DCPLB Address Registers (DCPLB_ADDRx)” on page 6-69 0xFFE0 013C DCPLB_ADDR15 “DCPLB Address Registers (DCPLB_ADDRx)” on page 6-69 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 863 “DCPLB Data Registers (DCPLB_DATAx)” on page 6-65 0xFFE0 0230 DCPLB_DATA12 “DCPLB Data Registers (DCPLB_DATAx)” on page 6-65 0xFFE0 0234 DCPLB_DATA13 “DCPLB Data Registers (DCPLB_DATAx)” on page 6-65 0xFFE0 0238 DCPLB_DATA14 “DCPLB Data Registers (DCPLB_DATAx)” on page 6-65 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 864: L1 Instruction Memory Controller Registers
See Section Address 0xFFE0 1004 IMEM_CONTROL “Instruction Memory Control Register (IMEM_CONTROL)” on page 6-12 0xFFE0 1008 ICPLB_STATUS “ICPLB Status Register (ICPLB_STATUS)” on page 6-74 0xFFE0 100C ICPLB_FAULT_ADDR “ICPLB Fault Address Register (ICPLB_FAULT_ADDR)” on page 6-76 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 865 “ICPLB Address Registers (ICPLB_ADDRx)” on page 6-71 0xFFE0 1130 ICPLB_ADDR12 “ICPLB Address Registers (ICPLB_ADDRx)” on page 6-71 0xFFE0 1134 ICPLB_ADDR13 “ICPLB Address Registers (ICPLB_ADDRx)” on page 6-71 0xFFE0 1138 ICPLB_ADDR14 “ICPLB Address Registers (ICPLB_ADDRx)” on page 6-71 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 866 “ICPLB Data Registers (ICPLB_DATAx)” on page 6-67 0xFFE0 122C ICPLB_DATA11 “ICPLB Data Registers (ICPLB_DATAx)” on page 6-67 0xFFE0 1230 ICPLB_DATA12 “ICPLB Data Registers (ICPLB_DATAx)” on page 6-67 0xFFE0 1234 ICPLB_DATA13 “ICPLB Data Registers (ICPLB_DATAx)” on page 6-67 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 867: Interrupt Controller Registers
“Core Event Vector Table” on page 4-35 (RST) 0xFFE0 2008 EVT2 “Core Event Vector Table” on page 4-35 (NMI) 0xFFE0 200C EVT3 “Core Event Vector Table” on page 4-35 (EVX) 0xFFE0 2010 EVT4 “Core Event Vector Table” on page 4-35 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 868 “Core Event Vector Table” on page 4-35 (IVG15) 0xFFE0 2104 IMASK “Core Interrupt Mask Register” on page 4-32 (EVT_IMASK) 0xFFE0 2108 IPEND “Core Interrupt Pending Register” on (EVT_IPEND) page 4-34 0xFFE0 210C ILAT “Core Interrupt Latch Register” on page 4-33 (EVT_ILAT) ADSP-BF535 Blackfin Processor Hardware Reference...
Page 869: Core Timer Registers
MMR assignments for the DSP Device ID register (0xFFE0 5000–0xFFE0 500C). Table A-5. DSPID Register Memory- Mapped Register Name See Section Address 0xFFE0 5000 DSPID “DSP Device ID Register (DSPID)” on page 20-27 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 870: Trace Unit Registers
Register (WPIACTL)” on page 20-7 0xFFE0 7040 WPIA0 “Watchpoint Instruction Address Registers (WPIAx)” on page 20-5 0xFFE0 7044 WPIA1 “Watchpoint Instruction Address Registers (WPIAx)” on page 20-5 0xFFE0 7048 WPIA2 “Watchpoint Instruction Address Registers (WPIAx)” on page 20-5 A-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 871 “Watchpoint Data Address Count Value Reg- isters (WPDACNTx)” on page 20-11 0xFFE0 7184 WPDACNT1 “Watchpoint Data Address Count Value Reg- isters (WPDACNTx)” on page 20-11 0xFFE0 7200 WPSTAT “Trace Buffer Status Register (TBUFSTAT)” on page 20-17 ADSP-BF535 Blackfin Processor Hardware Reference A-11...
Page 872: Performance Monitor Registers
Address 0xFFE0 8000 PFCTL “Performance Monitor Control Register (PFCTL)” on page 20-20 0xFFE0 8100 PFCNTR0 “Performance Monitor Control Register (PFCTL)” on page 20-20 0xFFE0 8104 PFCNTR1 “Performance Monitor Control Register (PFCTL)” on page 20-20 A-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 873 MMR, refer to the page shown in the “See Section” column. When viewing the PDF version of this document, click a refer- ence in the “See Section” column to jump to the additional information about the MMR. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 874: Clock And System Control Registers
Table B-2 lists the MMR assignment for the Chip ID register (0xFFC0 48C0). Table B-2. Chip ID Register Memory- Mapped Register Name See Section Address 0xFFC0 48C0 CHIPID “Chip ID Register (CHIPID)” on page 20-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 875: System Interrupt Controller Registers
(SIC_IARx)” on page 4-29 0xFFC0 0C10 SIC_IMASK “System Interrupt Status Register (SIC_ISR)” on page 4-25 0xFFC0 0C14 SIC_ISR “System Interrupt Status Register (SIC_ISR)” on page 4-25 0xFFC0 0C18 SIC_IWR “System Interrupt Wakeup-Enable Register (SIC_IWR)” on page 4-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 876: Watchdog Timer Registers
17-7 0xFFC0 1404 RTC_ICTL “RTC Interrupt Control Register (RTC_ICTL)” on page 17-8 0xFFC0 1408 RTC_ISTAT “RTC Interrupt Status Register (RTC_ISTAT)” on page 17-9 0xFFC0 140C RTC_SWCNT “RTC Stopwatch Count Register (RTC_SWCNT)” on page 17-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 877: Uart0 Controller Registers
12-10 0xFFC0 1802 UART0_IER “UARTx Interrupt Enable Registers (UARTx_IER)” on page 12-7 0xFFC0 1804 UART0_IIR “UARTx Interrupt Identification Registers (UARTx_IIR)” on page 12-9 0xFFC0 1806 UART0_LCR “UARTx Line Control Registers (UARTx_LCR)” on page 12-3 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 878 “UARTx Receive DMA Start Address Low Registers (UARTx_START_ADDR_LO_RX)” on page 12-23 0xFFC0 1A08 UART0_COUNT_RX “UARTx Receive DMA Count Regis- ters (UARTx_COUNT_RX)” on page 12-24 0xFFC0 1A0A UART0_NEXT_DESCR_RX “UARTx Receive DMA Next Descriptor Pointer Registers (UARTx_NEXT_DESCR_RX)” on page 12-25 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 879 “UARTx Transmit DMA Start Address Low Registers (UARTx_START_ADDR_LO_TX)” on page 12-31 0xFFC0 1B08 UART0_COUNT_TX “UARTx Transmit DMA Count Reg- isters (UARTx_COUNT_TX)” on page 12-32 0xFFC0 1B0A UART0_NEXT_DESCR_TX “UARTx Transmit DMA Next Descriptor Pointer Registers (UARTx_NEXT_DESCR_TX)” on page 12-33 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 880: Uart1 Controller Registers
12-10 0xFFC0 1C02 UART1_DLH “UARTx Divisor Latch Registers (UARTx_DLL, UARTx_DLH)” on page 12-10 0xFFC0 1C02 UART1_IER “UARTx Interrupt Enable Registers (UARTx_IER)” on page 12-7 0xFFC0 1C04 UART1_IIR “UARTx Interrupt Identification Registers (UARTx_IIR)” on page 12-9 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 881 “UARTx Receive DMA Start Address Low Registers (UARTx_START_ADDR_LO_RX)” on page 12-23 0xFFC0 1E08 UART1_COUNT_RX “UARTx Receive DMA Count Regis- ters (UARTx_COUNT_RX)” on page 12-24 0xFFC0 1E0A UART1_NEXT_DESCR_RX “UARTx Receive DMA Next Descriptor Pointer Registers (UARTx_NEXT_DESCR_RX)” on page 12-25 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 882 Address Low Registers (UARTx_START_ADDR_LO_TX)” on page 12-31 0xFFC0 1F08 UART1_COUNT_TX “UARTx Transmit DMA Count Reg- isters (UARTx_COUNT_TX)” on page 12-32 0xFFC0 1F0A UART1_NEXT_DESCR_TX “UARTx Transmit DMA Next Descriptor Pointer Registers (UARTx_NEXT_DESCR_TX)” on page 12-33 B-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 883: Timer Registers
(TIMERx_COUNTER)” on page 16-11 0xFFC0 2008 TIMER0_PERIOD_LO “Timer Period Registers (TIMERx_PERIOD)” on page 16-10 0xFFC0 200A TIMER0_PERIOD_HI “Timer Period Registers (TIMERx_PERIOD)” on page 16-10 0xFFC0 200C TIMER0_WIDTH_LO “Timer Width Registers (TIMERx_WIDTH)” on page 16-11 ADSP-BF535 Blackfin Processor Hardware Reference B-11...
Page 884 (TIMERx_COUNTER)” on page 16-11 0xFFC0 2026 TIMER2_COUNTER_HI “Timer Counter Registers (TIMERx_COUNTER)” on page 16-11 0xFFC0 2028 TIMER2_PERIOD_LO “Timer Period Registers (TIMERx_PERIOD)” on page 16-10 0xFFC0 202A TIMER2_PERIOD_HI “Timer Period Registers (TIMERx_PERIOD)” on page 16-10 B-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 885: Programmable Flag Registers
(FIO_MASKA_C, FIO_MASKA_S, FIO_MASKB_C, FIO_MASKB_S)” on page 15-5 0xFFC0 240A FIO_MASKA_S “Flag Interrupt Mask Registers (FIO_MASKA_C, FIO_MASKA_S, FIO_MASKB_C, FIO_MASKB_S)” on page 15-5 0xFFC0 240C FIO_MASKB_C “Flag Interrupt Mask Registers (FIO_MASKA_C, FIO_MASKA_S, FIO_MASKB_C, FIO_MASKB_S)” on page 15-5 ADSP-BF535 Blackfin Processor Hardware Reference B-13...
Page 886: Sport0 Controller Registers
11-9 0xFFC0 2802 SPORT0_RX_CONFIG “Transmit and Receive Configuration Registers (SPORTx_TX_CONFIG, SPORTx_RX_CONFIG)” on page 11-9 0xFFC0 2804 SPORT0_TX “SPORTx Transmit (SPORTx_TX) Registers” on page 11-17 0xFFC0 2806 SPORT0_RX “SPORTx Receive (SPORTx_RX) Registers” on page 11-19 B-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 887 SPORT0_MTCS2 “SPORTx Multichannel Transmit Select (SPORTx_MTCSx) Registers” on page 11-25 0xFFC0 2818 SPORT0_MTCS3 “SPORTx Multichannel Transmit Select (SPORTx_MTCSx) Registers” on page 11-25 0xFFC0 281A SPORT0_MTCS4 “SPORTx Multichannel Transmit Select (SPORTx_MTCSx) Registers” on page 11-25 ADSP-BF535 Blackfin Processor Hardware Reference B-15...
Page 888 SPORT0_MRCS5 “SPORTx Multichannel Receive Select (SPORTx_MRCSx) Registers” on page 11-27 0xFFC0 282E SPORT0_MRCS6 “SPORTx Multichannel Receive Select (SPORTx_MRCSx) Registers” on page 11-27 0xFFC0 2830 SPORT0_MRCS7 “SPORTx Multichannel Receive Select (SPORTx_MRCSx) Registers” on page 11-27 B-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 889 “SPORTx Receive DMA Count (SPORTx_COUNT_RX) Registers” on page 11-36 0xFFC0 2A0A SPORT0_NEXT_DESCR_RX “SPORTx Receive DMA Next Descriptor Pointer (SPORTx_NEXT_DESCR_RX) Registers” on page 11-36 0xFFC0 2A0C SPORT0_DESCR_RDY_RX “SPORTx Receive DMA Descriptor Ready (SPORTx_DESCR_RDY_RX) Registers” on page 11-37 ADSP-BF535 Blackfin Processor Hardware Reference B-17...
Page 890 Descriptor Pointer (SPORTx_NEXT_DESCR_TX) Registers” on page 11-45 0xFFC0 2B0C SPORT0_DESCR_RDY_TX “SPORTx Transmit DMA Descriptor Ready (SPORTx_DESCR_RDY_TX) Registers” on page 11-46 0xFFC0 2B0E SPORT0_IRQSTAT_TX “SPORTx Transmit DMA IRQ Sta- tus (SPORTx_IRQSTAT_TX) Regis- ters” on page 11-47 B-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 891: Sport1 Controller Registers
Divider Registers” on page 11-20 0xFFC0 2C0C SPORT1_TFSDIV “SPORTx Transmit (SPORTx_TFSDIV) and Receive (SPORTx_RFSDIV) Frame Sync Divider Registers” on page 11-22 0xFFC0 2C0E SPORT1_RFSDIV “SPORTx Transmit (SPORTx_TFSDIV) and Receive (SPORTx_RFSDIV) Frame Sync Divider Registers” on page 11-22 ADSP-BF535 Blackfin Processor Hardware Reference B-19...
Page 892 SPORT1_MTCS7 “SPORTx Multichannel Transmit Select (SPORTx_MTCSx) Registers” on page 11-25 0xFFC0 2C22 SPORT1_MRCS0 “SPORTx Multichannel Receive Select (SPORTx_MRCSx) Registers” on page 11-27 0xFFC0 2C24 SPORT1_MRCS1 “SPORTx Multichannel Receive Select (SPORTx_MRCSx) Registers” on page 11-27 B-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 893 (SPORTx_MCMCx) Registers” on page 11-29 0xFFC0 2E00 SPORT1_CURR_PTR_RX “SPORTx Receive DMA Current Descriptor Pointer (SPORTx_CURR_PTR_RX) Regis- ters” on page 11-31 0xFFC0 2E02 SPORT1_CONFIG_DMA_RX “SPORTx Receive DMA Configura- tion (SPORTx_CONFIG_DMA_RX) Registers” on page 11-31 ADSP-BF535 Blackfin Processor Hardware Reference B-21...
Page 894 Descriptor Pointer (SPORTx_CURR_PTR_TX) Regis- ters” on page 11-39 0xFFC0 2F02 SPORT1_CONFIG_DMA_TX “SPORTx Transmit DMA Configu- ration (SPORTx_CONFIG_DMA_TX) Registers” on page 11-40 0xFFC0 2F04 SPORT1_START_ADDR_HI_TX “SPORTx Transmit DMA Start Address High (SPORTx_START_ADDR_HI_TX) Registers” on page 11-43 B-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 895: Spi0 Controller Registers
(0xFFC0 3000–0xFFC0 33FF). Table B-12. SPI0 Controller Registers Memory-Mapped Register Name See Section Address 0xFFC0 3000 SPI0_CTL “SPIx Control Register (SPIx_CTL)” on page 10-8 0xFFC0 3002 SPI0_FLG “SPIx Flag Register (SPIx_FLG)” on page 10-10 ADSP-BF535 Blackfin Processor Hardware Reference B-23...
Page 896 SPI0_NEXT_DESCR “SPIx DMA Next Descriptor Pointer Register (SPIx_NEXT_DESCR)” on page 10-24 0xFFC0 320C SPI0_DESCR_RDY “SPIx DMA Descriptor Ready Register (SPIx_DESCR_RDY)” on page 10-25 0xFFC0 320E SPI0_DMA_INT “SPIx DMA Interrupt Register (SPIx_DMA_INT)” on page 10-26 B-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 897: Spi1 Controller Registers
“SPIx DMA Start Address High Register (SPIx_START_ADDR_HI) and SPIx DMA Start Address Low Register (SPIx_START_ADDR_LO)” on page 10-22 0xFFC0 3606 SPI1_START_ADDR_LO “SPIx DMA Start Address High Register (SPIx_START_ADDR_HI) and SPIx DMA Start Address Low Register (SPIx_START_ADDR_LO)” on page 10-22 ADSP-BF535 Blackfin Processor Hardware Reference B-25...
Page 898: Memory Dma Controller Registers
Registers (MDD_DSAH, MDD_DSAL)” on page 9-35 0xFFC0 3806 MDD_DSAL “Destination Memory DMA Start Address Registers (MDD_DSAH, MDD_DSAL)” on page 9-35 0xFFC0 3808 MDD_DCT “Source Memory DMA Transfer Count Reg- ister (MDD_DCT)” on page 9-40 B-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 899 “Destination Memory DMA Next Descrip- tor Pointer Register (MDD_DND)” on page 9-36 0xFFC0 390C MDS_DDR “Destination Memory DMA Descriptor Ready Register (MDD_DDR)” on page 9-36 0xFFC0 390E MDS_DI “Destination Memory DMA Interrupt Regis- ter (MDD_DI)” on page 9-38 ADSP-BF535 Blackfin Processor Hardware Reference B-27...
Page 900: Asynchronous Memory Controller—Ebiu
See Section Address 0xFFC0 4000 PCI_CTL “PCI Bridge Control Register (PCI_CTL)” on page 13-20 0xFFC0 4004 PCI_STAT “PCI Status Register (PCI_STAT)” on page 13-21 0xFFC0 4008 PCI_ICTL “PCI Interrupt Controller Register (PCI_ICTL)” on page 13-22 B-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 901 0xEEFF FF1C PCI_CFG_RID “PCI Configuration Revision ID Register (PCI_CFG_RID)” on page 13-34 0xEEFF FF20 PCI_CFG_BIST “PCI Configuration BIST Register (PCI_CFG_BIST)” on page 13-35 0xEEFF FF24 PCI_CFG_HT “PCI Configuration Header Type Register (PCI_CFG_HT)” on page 13-36 ADSP-BF535 Blackfin Processor Hardware Reference B-29...
Page 902 PCI_CFG_IP “PCI Configuration Interrupt Pin Register (PCI_CFG_IP)” on page 13-42 0xEEFF FF4C PCI_CFG_IL “PCI Configuration Interrupt Line Register (PCI_CFG_IL)” on page 13-43 0xEEFF FF50 PCI_HMCTL “PCI Host Memory Control Register (PCI_HMCTL)” on page 13-43 B-30 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 903: Usb Device Registers
“DMA Master Channel Base Address Low Register (USBD_DMABL)” on page 14-25 0xFFC0 4444 USBD_DMABH “DMA Master Channel Base Address High Register (USBD_DMABH)” on page 14-26 0xFFC0 4446 USBD_DMACT “DMA Master Channel Count Register (USBD_DMACT)” on page 14-26 ADSP-BF535 Blackfin Processor Hardware Reference B-31...
Page 904 “USB Endpoint x Mask Registers (USBD_MASKx)” on page 14-29 0xFFC0 4498 USBD_EPCFG2 “USB Endpoint x Control Registers (USBD_EPCFGx)” on page 14-31 0xFFC0 449A USBD_EPADR2 “USB Endpoint x Address Offset Registers (USBD_EPADRx)” on page 14-33 B-32 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 905 “USB Endpoint x Mask Registers (USBD_MASKx)” on page 14-29 0xFFC0 44B6 USBD_EPCFG5 “USB Endpoint x Control Registers (USBD_EPCFGx)” on page 14-31 0xFFC0 44B8 USBD_EPADR5 “USB Endpoint x Address Offset Registers (USBD_EPADRx)” on page 14-33 ADSP-BF535 Blackfin Processor Hardware Reference B-33...
Page 906 “USB Endpoint x Control Registers (USBD_EPCFGx)” on page 14-31 0xFFC0 44CC USBD_EPADR7 “USB Endpoint x Address Offset Registers (USBD_EPADRx)” on page 14-33 0xFFC0 44CE USBD_EPLEN7 “USB Endpoint x Buffer Length Registers (USBD_EPLENx)” on page 14-34 B-34 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 907: System Dma Control Registers
0xFFC0 4C04 EBIU_SDBCTL “SDRAM Memory Bank Control Register (EBIU_SDBCTL)” on page 18-49 0xFFC0 4C0A EBIU_SDRRC “SDRAM Refresh Rate Control Register (EBIU_SDRRC)” on page 18-54 0xFFC0 4C0E EBIU_SDSTAT “SDRAM Control Status Register (EBIU_SDSTAT)” on page 18-53 ADSP-BF535 Blackfin Processor Hardware Reference B-35...
Page 908 SDRAM Controller External Bus Interface Unit B-36 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 909: Test Features
The test logic consists of a Boundary-Scan register and other building blocks and is accessed through a Test Access port (TAP). Full details of the JTAG standard can be found in the document IEEE Standard Test Access Port and Boundary-Scan Architecture, ISBN 1-55937-350-4. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 910: Boundary-Scan Architecture
1 or logic 0 state. For full details of the operation, see the JTAG standard. Figure C-1 shows the state diagram for the TAP controller. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 911 • The TAP controller enters the Test-Logic-Reset state when TRST asynchronously asserted. • An external system reset does not affect the state of the TAP con- troller, nor does the state of the TAP controller affect an external system reset. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 912: Instruction Register
Register 01234 EXTEST 00000 Boundary-Scan MBIST_SCAN 00001 IDCODE 00010 CHIPID MEMTEST_SCAN 00011 DBG_SCAN 00100 WRAPPER_SCAN 00101 RUNMBIST 00111 EMUIR_SCAN 01000 RESMBIST 01001 DC_MBIST_SOF 01011 IC_MBIST_SOF 01101 WRAPPER_MODE 01111 SAMPLE/PRELOAD 00001 Boundary-Scan RS_WRAPPER_MODE 10010 EMUDAT_SCAN 10100 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 913 Register 01234 EMUPC_SCAN 10110 BYPASS 11111 Bypass Figure C-2 shows the instruction bit scan ordering for the paths shown in Table C-2. Boundary-Scan Register Bypass Register CHIPID JTAG Instruction Register Figure C-2. Serial Scan Paths ADSP-BF535 Blackfin Processor Hardware Reference...
Page 914: Public Instructions
The PRELOAD part of the instruction allows data to be loaded on the device pins and driven out on the board with the EXTEST instruction. Data is preloaded on the pins on the falling edge of ADSP-BF535 Blackfin Processor Hardware Reference...
Page 915: Idcode – Binary Code 00010
Test-Logic-Reset controller state. BYPASS – Binary Code 11111 The BYPASS instruction selects the register to be connected to BYPASS . The instruction has no effect on the internal logic. No data inversion should occur between ADSP-BF535 Blackfin Processor Hardware Reference...
Page 916: Boundary-Scan Register
) and bit 468 is the last bit output (closest to Table C-3. Scan Path Position Definitions Position Type Signal Name SUSPEND SUSPEND OE TXEN TXEN OE TXDMNS TXDMNS OE TXDPLS TXDPLS OE DMNS DPLS RESET XVER_DATA USB_CLK TX1 OE TX0 OE ADSP-BF535 Blackfin Processor Hardware Reference...
Page 917 TMR(2) OE TMR(2 TMR(1 TMR(1) OE TMR(1) TMR(0) TMR(0) OE TMR(0) ADDR(2) ADDR(2) OE ADDR(3) ADDR(3) OE ADDR(4) ADDR(4) OE ADDR(5) ADDR(5) OE ADDR(6) ADDR(6) OE ADDR(7) ADDR(7) OE ADDR(8) ADDR(8) OE ADDR(9) ADDR(9) OE ADDR(10) ADSP-BF535 Blackfin Processor Hardware Reference...
Page 918 ADDR(12) ADDR(12) OE ADDR(13) ADDR(13) OE ADDR(14) ADDR(14) OE ADDR(15) ADDR(15) OE ADDR(16) ADDR(16) OE ADDR(17) ADDR(17) OE ADDR(18) ADDR(18) OE ADDR(19) ADDR(19) OE ADDR(20) ADDR(20) OE ADDR(21) ADDR(21) OE ADDR(22) ADDR(22) OE ADDR(23) C-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 919 ADDR(24) ADDR(24) OE ADDR(25) ADDR(25) OE ABE_SDQM(0) ABE_SDQM(0) OE ABE_SDQM(1) ABE_SDQM(1) OE ABE_SDQM(2) ABE_SDQM(2) OE ABE_SDQM(3) ABE_SDQM(3) OE AMS(0) AMS(0) OE AMS(1) AMS(1) OE AMS(2) AMS(2) OE AMS(3) AMS(3) OE AOE OE ARE OE ADSP-BF535 Blackfin Processor Hardware Reference C-11...
Page 920 CLKOUT_SCLK1 Reserved SCLK0 Reserved SCKE SCKE OE SA10 SA10 OE SRAS SRAS OE SWE OE SMS(3) SMS(3) OE SMS(2) SMS(2) OE SMS(1) SMS(1) OE SMS(0) SMS(0) OE SCAS SCAS OE ARDY DATA(0) DATA(0) OE C-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 921 DATA(0) DATA(1) DATA(1) OE DATA(1) DATA(2) DATA(2) OE DATA(2) DATA(3) DATA(3) OE DATA(3) DATA(4) DATA(4) OE DATA(4) DATA(5) DATA(5) OE DATA(5) DATA(6) DATA(6) OE DATA(6) DATA(7) DATA(7) OE DATA(7) DATA(8) DATA(8) OE DATA(8) DATA(9) ADSP-BF535 Blackfin Processor Hardware Reference C-13...
Page 922 DATA(9) OE DATA(9) DATA(10) DATA(10) OE DATA(10) DATA(11) DATA(11) OE DATA(11) DATA(12) DATA(12) OE DATA(12) DATA(13) DATA(13) OE DATA(13) DATA(14) DATA(14) OE DATA(14) DATA(15) DATA(15) OE DATA(15) DATA(16) DATA(16) OE DATA(16) DATA(17) DATA(17) OE DATA(17) C-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 923 DATA(18) OE DATA(18) DATA(19) DATA(19) OE DATA(19) DATA(20) DATA(20) OE DATA(20) DATA(21) DATA(21) OE DATA(21) DATA(22) DATA(22) OE DATA(22) DATA(23) DATA(23) OE DATA(23) DATA(24) DATA(24) OE DATA(24) DATA(25) DATA(25) OE DATA(25) DATA(26) DATA(26) OE ADSP-BF535 Blackfin Processor Hardware Reference C-15...
Page 924 DATA(26) DATA(27) DATA(27) OE DATA(27) DATA(28) DATA(28) OE DATA(28) DATA(29) DATA(29) OE DATA(29) DATA(30) DATA(30) OE DATA(30) DATA(31) DATA(31) OE DATA(31) PF(0) PF(0) OE PF(0) PF(1) PF(1) OE PF(1) PF(2) PF(2) OE PF(2) PF(3) C-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 925 PF(3) OE PF(3) PF(4) PF(4) OE PF(4) PF(5) PF(5) OE PF(5) PF(6) PF(6) OE PF(6) PF(7) PF(7) OE PF(7) PF(8) PF(8) OE PF(8) PF(9) PF(9) OE PF(9) PF(10) PF(10) OE PF(10) PF(11) PF(11) OE PF(11) ADSP-BF535 Blackfin Processor Hardware Reference C-17...
Page 926 Signal Name PF(12) PF(12) OE PF(12) PF(13) PF(13) OE PF(13) PF(14) PF(14) OE PF(14) PF(15) PF(15) OE PF(15) RSCLK0 RSCLK0 OE RSCLK0 RFS0 RFS0 OE RFS0 TSCLK0 TSCLK0 OE TSCLK0 TFS0 TFS0 OE TFS0 C-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 927 Signal Name DT0 OE RSCLK1 RSCLK1 OE RSCLK1 RFS1 RFS1 OE RFS1 TSCLK1 TSCLK1 OE TSCLK1 TFS1 TFS1 OE TFS1 DT1 OE MOSI0 MOSI0 OE MOSI0 MISO0 MISO0 OE MISO0 SCK0 SCK0 OE SCK0 MOSI1 ADSP-BF535 Blackfin Processor Hardware Reference C-19...
Page 928 MOSI1 OE MOSI1 MISO1 MISO1 OE MISO1 SCK1 SCK1 OE SCK1 PCI_AD(31) PCI_AD(31) OE PCI_AD(31) PCI_AD(30) PCI_AD(30) OE PCI_AD(30) PCI_AD(29) PCI_AD(29) OE PCI_AD(29) PCI_AD(28) PCI_AD(28) OE PCI_AD(28) PCI_AD(27) PCI_AD(27) OE PCI_AD(27) PCI_AD(26) PCI_AD(26) OE PCI_AD(26) C-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 929 PCI_AD(25) OE PCI_AD(25) PCI_AD(24) PCI_AD(24) OE PCI_AD(24) PCI_AD(23) PCI_AD(23) OE PCI_AD(23) PCI_AD(22) PCI_AD(22) OE PCI_AD(22) PCI_AD(21) PCI_AD(21) OE PCI_AD(21) PCI_AD(20) PCI_AD(20) OE PCI_AD(20) PCI_AD(19) PCI_AD(19) OE PCI_AD(19) PCI_AD(18) PCI_AD(18) OE PCI_AD(18) PCI_AD(17) PCI_AD(17) OE ADSP-BF535 Blackfin Processor Hardware Reference C-21...
Page 930 PCI_AD(17) PCI_AD(16) PCI_AD(16) OE PCI_AD(16) PCI_AD(15) PCI_AD(15) OE PCI_AD(15) PCI_AD(14) PCI_AD(14) OE PCI_AD(14) PCI_AD(13) PCI_AD(13) OE PCI_AD(13) PCI_AD(12) PCI_AD(12) OE PCI_AD(12) PCI_AD(11) PCI_AD(11) OE PCI_AD(11) PCI_AD(10) PCI_AD(10) OE PCI_AD(10) PCI_AD(9) PCI_AD(9) OE PCI_AD(9) PCI_AD(8) C-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 931 PCI_AD(8) OE PCI_AD(8) PCI_AD(7) PCI_AD(7) OE PCI_AD(7) PCI_AD(6) PCI_AD(6) OE PCI_AD(6) PCI_AD(5) PCI_AD(5) OE PCI_AD(5) PCI_AD(4) PCI_AD(4) OE PCI_AD(4) PCI_AD(3) PCI_AD(3) OE PCI_AD(3) PCI_AD(2) PCI_AD(2) OE PCI_AD(2) PCI_AD(1) PCI_AD(1) OE PCI_AD(1) PCI_AD(0) PCI_AD(0) OE PCI_AD(0) ADSP-BF535 Blackfin Processor Hardware Reference C-23...
Page 932 PCI_CBE(0) PCI_CBE(0) OE PCI_CBE(0) PCI_CBE(1) PCI_CBE(1) OE PCI_CBE(1) PCI_CBE(2) PCI_CBE(2) OE PCI_CBE(2) PCI_CBE(3) PCI_CBE(3) OE PCI_CBE(3) PCI_IRDY PCI_IRDY OE PCI_IRDY PCI_RST PCI_RST OE PCI_RST PCI_REQ PCI_REQ OE PCI_GNT PCI_IDSEL PCI_FRAME PCI_FRAME OE PCI_FRAME PCI_TRDY C-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 933 Signal Name PCI_TRDY OE PCI_TRDY PCI_DEVSEL PCI_DEVSEL OE PCI_DEVSEL PCI_STOP PCI_STOP OE PCI_STOP PCI_PERR PCI_PERR OE PCI_PERR PCI_PAR PCI_PAR OE PCI_PAR PCI_SERR PCI_SERR OE PCI_SERR PCI_LOCK PCI_CLK PCI_INTA PCI_INTA OE PCI_INTA PCI_INTB PCI_INTC PCI_INTD BMODE(0) ADSP-BF535 Blackfin Processor Hardware Reference C-25...
Page 934 Boundary-Scan Architecture Table C-3. Scan Path Position Definitions (Cont’d) Position Type Signal Name BMODE(1) BMODE(2) SLEEP SLEEP OE BYPASS EMU OE C-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 935: Unsigned Or Signed: Two's-Complement Format
LSB, so that all magnitude bits have a weight of 1 or greater. This format is shown in Figure D-1. Note in two’s-complement format, the sign bit has a negative weight. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 936 0.N format, where N is the number of bits in the data word and M = N–1. Signed Integer Weight - (2 . . . Sign Bit Radix Point Unsigned Integer Weight . . . Sign Bit Radix Point Figure D-1. Integer Format ADSP-BF535 Blackfin Processor Hardware Reference...
Page 937 The format in Figure D-2 is 13.3. Signed Fractional (13.3) Weight - (2 . . . Sign Bit Radix Point Unsigned Fractional (13.3) Weight . . . Sign Bit Radix Point Figure D-2. Example of Fractional Format ADSP-BF535 Blackfin Processor Hardware Reference...
Page 938: Binary Multiplication
(signed or unsigned, radix point in the same location) and the result for- mat is the same as the input format. Addition and subtraction are performed the same way whether the inputs are signed or unsigned. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 939: Fractional Mode And Integer Mode
(with 16 bits of addi- tional precision). For example, multiplying a 1.15 number by a 5.11 number yields a 6.26 number. When shifted left one bit, the result is a 5.27 number, or a 5.11 number plus 16 LSBs. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 940: Block Floating-Point Format
In the example, each of the three data samples has at least two non-significant, redundant sign bits. Each data value can grow by these two bits (two orders of magnitude) before overflowing; thus, these bits are called guard bits. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 941 2 guard bits. • If were 0 after processing, the block would have to be shifted two bits right. In either case, the block exponent is updated to reflect the shift. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 942 0x1FFF = 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0x03FF = 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Sign Bit Figure D-5. Block Floating-Point Adjustment ADSP-BF535 Blackfin Processor Hardware Reference...
Page 943 The Bank Activate command must be applied before a read or write command. The SDC does not interleave SDRAM accesses, so only one internal bank in a row is open at a time. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 944 The Burst Stop command is one of several ways to terminate a burst read or write operation. Since the SDRAM burst length is always programmed to be 1, the SDC does not support the Burst Stop command. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 945 Also called Associative Memory. A memory device that includes compari- son logic with each bit of storage. A datum is broadcast to all words in memory; the datum is compared with the stored values; and values that match are flagged. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 946 The process by which the DAG “wraps around” or repeatedly steps through a range of registers. companding (compressing/expanding). The process of logarithmically encoding and decoding data to minimize the number of bits that must be sent. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 947 Processing component that provides memory addresses when data is trans- ferred between memory and registers. Data Register File. A set of data registers that transfers data between the data buses and the computation units and provide local storage for operands. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 948 Jump or call/return instructions that use an absolute address that does not change at runtime, such as a program label, or use a PC-relative address. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 949 I/O processor loads the next DMA descriptor into the DMA parame- ter registers when the current DMA finishes and autoinitializes the next DMA sequence. DMA descriptor registers. Registers that hold the setup information for a DMA process. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 950 DSP. See Digital Signal Processor EAB. See External Access Bus EBC. See External Bus Controller EBIU. See External Bus Interface Unit EMB. See External Mastered Bus ADSP-BF535 Blackfin Processor Hardware Reference...
Page 951 A line or bus that allows the processor core and Memory DMA controller to directly access off-chip memory and PCI memory space to perform instruction fetches, data loads, data stores, and high-throughput mem- ory-to-memory DMA transfers. ADSP-BF535 Blackfin Processor Hardware Reference...
Page 952 A channel or port that extends the processors internal address and data buses off-chip, providing the processor’s interface to off-chip memory and peripherals. G-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 953 A digital logic chip that can be programmed after production and that contains many thousands of gates. FPGA. See Field Programmable Gate Array. fully associative. Cache architecture where each line can be placed anywhere in the cache. ADSP-BF535 Blackfin Processor Hardware Reference G-11...
Page 954 IEEE (Institute of Electrical and Electronics Engineers). An international technical professional society, based in the United States. index. Address portion that is used to select an array element (for example, line index) G-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 955 The SDC does not support interleaved accesses. The bank address can be thought of as part of the row address. The SDC also assumes that all SDRAMs to which it interfaces have four internal banks. ADSP-BF535 Blackfin Processor Hardware Reference G-13...
Page 956 JEDEC. (formerly known as the Joint Electronic Device Engineering Council, now called the JEDEC Solid State Technology Association) The semiconductor engineering standardization body of the Electronic Industries Alliance (EIA), an electronic industry trade association. G-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 957 A DAG register that sets up the range of addresses in a circular buffer. Level 1 (L1) memory. Memory that is directly accessed by the core with no intervening memory subsystems between it and the core. ADSP-BF535 Blackfin Processor Hardware Reference G-15...
Page 958 A rule based on the observation that, in general, the cache entry that has not been accessed for longest is least likely to be accessed in the near future. LSB. See Least Significant Bit. G-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 959 Once the power-up sequence has completed, the bit should not be PSSE set again unless a change to the mode register is desired. ADSP-BF535 Blackfin Processor Hardware Reference G-17...
Page 960 The multiple operations perform the same as if they were in corresponding single func- tion computations. G-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 961 (zero) voltage between encoded bits. This method eliminates the need for a clock signal. orthogonal. The characteristic of being independent. An orthogonal instruction set allows any register to be used in an instruction that references a register. PAB. See Peripheral Access Bus ADSP-BF535 Blackfin Processor Hardware Reference G-19...
Page 962 Clock, USB, programmable flags, UARTs, SPORTs, and SPIs. Peripheral Access Bus (PAB). A low and predictable latency bus that keeps core stalls to a minimum and allows for manageable interrupt latencies to time critical peripherals. G-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 963 Precharge command. The Precharge command closes a specific internal bank in the active page or all internal banks in the page. The SDC always does a Precharge All, closing all internal banks. ADSP-BF535 Blackfin Processor Hardware Reference G-21...
Page 964 Often, a least recently used (LRU) algorithm is employed. ROM (Read-Only Memory). A data storage device manufactured with fixed contents. This term is most often used to refer to non-volatile semiconductor memory. RTC. See Real-Time Clock G-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 965 Four regions of memory that can be configured to be 16 MB, 32 MB, 64 MB, or 128 MB and are selected by the pins. Each bank can SMS[3:0] be selected to be either all 32 bits wide or all 16 bits wide. ADSP-BF535 Blackfin Processor Hardware Reference G-23...
Page 966 SDC to exit the SDRAM from Self-Refresh mode. See “Enter- ing and Exiting Self-Refresh Mode (SRFS)” on page 18-44. Serial Peripheral Interface (SPI). A synchronous serial protocol used to connect integrated circuits. G-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 967 The SIC provides mapping between the peripheral interrupt sources and the prioritized general-purpose interrupt inputs of the core. SIMD (Single Instruction, Multiple Data). A parallel computer architecture in which a collection of data is processed simultaneously under one instruction. ADSP-BF535 Blackfin Processor Hardware Reference G-25...
Page 968 For the ADSP-BF535 processor, the peripheral set (Timers, Real-Time Clock, USB, programmable flags, UARTs, SPORTs, and SPIs), the PCI controller, the external memory controller (EBIU), the Memory DMA controller, and the interfaces between these, the system, and the optional, external (off-chip) resources. G-26 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 969 SDRAM Memory Global TRAS Control register ( ) is 4 bits wide and can be programmed to EBIU_SDGCTL be 1 to 15 clock cycles long. “Selecting the Bank Activate Command Delay (TRAS)” on page 18-47. ADSP-BF535 Blackfin Processor Hardware Reference G-27...
Page 970 Required delay between issuing successive Bank Activate commands to the same SDRAM internal bank. This delay is not directly programmable. The t delay must be satisfied by programming the fields TRAS RP  to ensure that t G-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 971 TAP (Test Access Port). See JTAG port TDM. See Time Division Multiplexing three-state versus Tristate. Analog Devices documentation uses the word three-state instead of tristate. Tristate™ is a trademarked term owned by National Semiconductor. ADSP-BF535 Blackfin Processor Hardware Reference G-29...
Page 972 The module in the ADSP-BF535 processor that controls the Universal Serial Bus. The USBD consists of the UDC core module and a front-end interface. The USBD connects the DAB and the PAB with and off-chip USB transceiver. G-30 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 973 A control or status bit that can be cleared (= 0) by being written to with 1. Write-1-to-Set (W1S) bit. A control or status bit that is set by writing a 1 to it. It cannot be cleared by writing a 0 to it. ADSP-BF535 Blackfin Processor Hardware Reference G-31...
Page 974 A cache write policy (also known as store through). The write data is writ- ten to both the cache line and to the source memory. The modified cache line is not written to the source memory when it is replaced. G-32 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 975 Data numeric formats, Address Generators operating modes, to 3-18, 8-12 addressing modes, 5-15 PCI, 1-8, 13-1 address tag compare operation, 6-19 PCI interface, 1-13 peripherals, programmable flags, 1-21, 15-1 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 976 Asynchronous Memory Global Control PAB, register (EBIU_AMGCTL), 18-10 SPORTs and USB, 14-3 Asynchronous Memory Interface Signals USB DMA channel, 14-3 (table), 18-5 ARDY, 18-13, 18-26 asynchronous serial communications, 12-2 ASYNC memory banks, 18-3 atomic operations, 6-83 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 977 4-10 bit toggle, 2-48 conditional branches, 4-14 bit-reversed addressing, 5-1, unconditional branches, 4-14 bit stream on the TxD pin (figure), 12-2 Branch Prediction, 4-14 bitstuff violations, 14-61 branch prediction, 4-14 Blackfin DSP family ADSP-BF535 Blackfin Processor Hardware Reference...
Page 978 6-19 from PCI, 13-7 data cache access, 6-45 buses definition, 6-19 concurrent operations, in atomic operations, 6-84 hierarchy, processing, 6-20 on-chip, requirements, 6-20 PCI AD, 13-6 cache inhibited accesses, 6-84 peripheral, buses (continued) ADSP-BF535 Blackfin Processor Hardware Reference...
Page 979 8-22 channel selection registers, 11-66 UDC, 14-13 CH (Compare Hit) bit, 20-28 USB, 14-13 CHIPID (Chip ID register), 20-26, C-4, clock input (CLKIN) pin, 19-2 clock phase, SPI, 10-28, 10-30 clock polarity, SPI, 10-28 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 980 20-28 control registers computation EBIU, 18-8 instructions, control transfer status, 2-22 problems, USB, 14-59 concurrent bus operations, USB, 14-47, 14-56 conditional with data phase, USB, 14-58 JUMP instruction, 4-10 with no data phase, USB, 14-57 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 981 4-43 Core Timer Count register (TCOUNT), DAG0 Multiple CPLB Hits, 4-43 16-23 DAG0 Protection Violation, 4-43 Core Timer Period register (TPERIOD), DAG1 CPLB Miss, 4-43 16-24 DAG1 Misaligned Access, 4-43 DAG1 Multiple CPLB Hits, 4-43 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 982 Data Receive, serial (DRx) pins, 11-3, 11-4 DCPLB Address registers Data Register File, (DCPLB_ADDRx), 6-69, 6-70 data registers, 2-5, DCPLB_ADDRx (Data Cacheability data sampling, serial, 11-57 Protection Lookaside Buffer Address data store format, registers), 6-70 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 983 Destination Memory DMA Next buffer size, multichannel, 11-68 Descriptor Pointer register bus, 20-27 (MDD_DND), 9-36 Bus Debug registers, 20-27 Destination Memory DMA Start Address bus error conditions, 9-45 High register (MDD_DSAH), 9-35 channel latency requirement, 12-17 channels, 12-17 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 984 DMA control registers (table), 9-30 DTEST_COMMAND (Data Test DMA Current Descriptor Pointer register, Command register), 6-49 9-26 DTEST_DATAx (Data Test Data DMA_DBP (DMA Descriptor Base registers), 6-49 Pointer register), 9-24 dual 16-bit operations, 2-25 I-10 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 985 Emulation mode, EBIU (External Bus Interface Unit) entering, as slave, 18-4 emulator mode, asynchronous interfaces supported, 18-1 Enable Download of Configuration into block diagram, 18-3 UDC Core register (USBD_EPBUF), bus error, 18-9 14-18 clock, 18-1 ADSP-BF535 Blackfin Processor Hardware Reference I-11...
Page 986 4-55 definition, 4-18 exception routine, example code, 4-57 exception, 4-38 Exceptions, 4-38 latency in servicing, 4-58 Exceptions by Descending Priority (table), nested, 4-33 4-42 Exceptions While Executing an Exception Handler, 4-43 I-12 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 987 System Interrupt Mask Register, incrementation, 4-28 fetched address, figure, System Interrupt Status Register, FFT calculations, 4-26 FIFO, 18-1 figure, System Interrupt Wakeup-Enable PCI transaction, 13-7 Register, 4-24 figure, Core Interrupt Latch Register, 4-33 ADSP-BF535 Blackfin Processor Hardware Reference I-13...
Page 988 11-50 Flag Polarity register (FIO_POLAR), 15-9 frequency flags clock, PCI status register, 13-22 EAB, 7-15 programmable, 15-1 EMB, 7-18 Transmit Holding Register Empty Front-End Interface, USB, 14-7 status, 12-5 Full On mode, 1-22 I-14 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 989 I-Fetch Access Exception, 4-42 hardware reset, 3-13 I-Fetch CPLB Miss, 4-42 Harvard architecture, I-Fetch Misaligned Access, 4-42 header type, PCI, 13-36 I-Fetch Multiple CPLB Hits, 4-42 heavy clock load and SDRAM, 18-44 I-Fetch Protection Violation, 4-42 ADSP-BF535 Blackfin Processor Hardware Reference I-15...
Page 990 Lookaside Buffer Data registers interfaces, (ICPLB_DATAx), 6-67 external memory, 18-5 Instruction Decode (DEC), internal, Instruction Fetch 1 (IF1), USB, 14-12 Instruction Fetch 2 (IF2), Interface Signals, Asynchronous Memory Instruction Fetch (Core I bus), (table), 18-5 I-16 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 991 4-54 invalidating instructions, hardware error, 4-44 invalid cache line (definition), masking, USB, 14-30 I/O Data Window, PCI, 13-6 multiple sources, 4-21 I/O drivers, PCI, 13-44 nested, 4-33 I/O memory space, 1-10 ADSP-BF535 Blackfin Processor Hardware Reference I-17...
Page 992 Level 1 (L1) Data Memory, 3-11 access, 6-38 architecture, 6-39 JTAG configuration, 6-10 port, 3-17 control registers, 6-12 standard, 20-26, C-1, C-2, Data Banks A and B, 6-37, 6-38 jump, dual port capability, 6-38 I-18 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 993 Low Transmit Frame Sync Select (LTFS) little endian data ordering, bit, 11-14, 11-56, 11-57 load, speculative execution, 6-81 L-registers (Length), Load Mode Register, 18-77 LSETUP (loop setup) instruction, 4-15 Load Mode Register command, 18-77 LT (Loop Top registers), ADSP-BF535 Blackfin Processor Hardware Reference I-19...
Page 994 USB, 14-33 MDD_DI (Destination Memory DMA DMA channel, Interrupt register), 9-38 external, MDD_DND (Destination Memory DMA how instructions are stored, 6-77 Next Descriptor Pointer register), internal, 9-36 internal bank, 18-31 L2 SRAM, I-20 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 995 DMA data packing, 11-68 6-85 multichannel enable, 11-67 PCI on EAB, 13-26 multichannel frame delay, 11-64 memory reference, exception for, 4-38 Multichannel Frame Delay (MFD) field, microcontroller load/store instructions, 11-64 minimal clock load and SDRAM, 18-44 ADSP-BF535 Blackfin Processor Hardware Reference I-21...
Page 996 2-40 data formats, 2-11 muxing SDRAM addressing, 18-60 two’s complement, unsigned, numeric formats, binary multiplication, nested interrupt, 4-33 block floating point, logging, 4-52 integer mode, Nested Interrupt Handling (figure), 4-50 two’s complement, I-22 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 997 USB buffer, 14-43 clock requirements, 13-45 overview, 4-1, 7-1, 11-1 core access, 13-3, 13-18 core access, bus operation ordering, 13-18 PAB Agents (Masters, Slaves), core application interface logic, 13-20 data windows, 13-6 delayed transactions, 13-7 ADSP-BF535 Blackfin Processor Hardware Reference I-23...
Page 998 13-15 Code register), 13-33 overview, 13-1 PCI_CFG_CLS (PCI Configuration parity error, 13-8 Cache Line Size register), 13-37 power domains, 13-45 PCI_CFG_CMD (PCI Configuration power savings, 8-24 Command register), 13-32 programming model, 13-18 I-24 ADSP-BF535 Blackfin Processor Hardware Reference...
Page 999 13-26 PCI Configuration Device ID register PCI Enable bit, 13-20 (PCI_CFG_DIC), 13-29 PCI_HMCTL (PCI Host Memory PCI Configuration Header Type register Control register), 13-14, 13-43 (PCI_CFG_HT), 13-36 PCI Host Memory Control register (PCI_HMCTL), 13-43 ADSP-BF535 Blackfin Processor Hardware Reference I-25...
Page 1000 PC-Relative Indirect Branch and Call, 4-12 peripheral DMA Next Descriptor Pointer PDWN bit, register, 9-23 performance peripheral DMA Start Address registers, DAB, 7-11 9-21 EAB, 7-15 peripheral DMA Transfer Count register, EAB estimates (table), 7-15 9-19 EMB, 7-18 I-26 ADSP-BF535 Blackfin Processor Hardware Reference...

Analog Devices ADSP-BF535 Blackfin Hardware Reference Manual

Preface

Introduction

Computational Units

Operating Modes and States

Program Sequencer

Data Address Generators

Memory

Chip Bus Hierarchy

Dynamic Power Management

Quick Links

Hardware Reference

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Summary of Contents for Analog Devices ADSP-BF535 Blackfin