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Transmit Control Register
The
register enables the SPI transmit channel, initiates transmit transfers, and configures
SPI_TXCTL
SPI_TFIFO
buffer watermark settings.
TRWM (R/W)
FIFO Regular Watermark
TDU (R/W)
Transmit Data Underrun
TDR (R/W)
Transmit Data Request
TUWM (R/W)
FIFO Urgent Watermark
Figure 16-39: SPI_TXCTL Register Diagram
Table 16-37: SPI_TXCTL Register Fields
Bit No.
(Access)
18:16
TUWM
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit Name
FIFO Urgent Watermark.
The SPI_TXCTL.TUWM bits select the transmit FIFO (SPI_TFIFO) watermark
level for urgent data bus requests. The SPI also uses this watermark level for generation
of the SPI_ILAT.TUWM interrupt request. When an urgent
mark is enabled with SPI_TXCTL.TUWM, the SPI_TXCTL.TRWM selection is used
as the deassertion condition for any SPI_ILAT.TUWM interrupt requests that are
latched.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Description/Enumeration
0 Disabled
1 25% empty TFIFO
2 50% empty TFIFO
3 75% empty TFIFO
4 Empty TFIFO
ADSP-SC58x SPI Register Descriptions
TEN (R/W)
Transmit Enable
TTI (R/W)
Transmit Transfer Initiate
TWCEN (R/W)
Transmit Word Counter Enable
SPI_TFIFO
water-
16–79
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