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Delay Register
The
register selects a transfer delay and the lead/lag timing between slave select signals and SPI clock
SPI_DLY
edge assertion/deassertion.
LAGX (R/W)
Extended SPI Clock Lag Control
LEADX (R/W)
Extended SPI Clock Lead Control
Figure 16-22: SPI_DLY Register Diagram
Table 16-20: SPI_DLY Register Fields
Bit No.
(Access)
9
LAGX
(R/W)
8
LEADX
(R/W)
7:0
STOP
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
9
8
0
0
0
0
0
0
1
1
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit Name
Extended SPI Clock Lag Control.
The SPI_DLY.LAGX bit enables insertion of a 1-SPI_CLK cycle lag (extend lag) in
the timing between the slave select (SPI_SEL[n]) assertion and first SPI clock edge.
Extended SPI Clock Lead Control.
The SPI_DLY.LEADX bit enables insertion of a 1-SPI_CLK cycle lead (extend lead)
in the timing between the slave select (SPI_SEL[n]) deassertion and last SPI clock
edge.
Transfer Delay Time in Multiples of SPI Clock Period.
The SPI_DLY.STOP bits select a delay (number of stop bits in multiples of SPI
clock duration) at the end of each SPI transfer. The default delay is the minimum val-
ue required to comply with the SPI protocol (1-bit duration). The SPI_DLY.STOP
bits can be programmed with smaller delay values, resulting in continuous operation
(for example, stop bits =0).
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Description/Enumeration
0 Disable
1 Enable
0 Disable
1 Enable
ADSP-SC58x SPI Register Descriptions
STOP (R/W)
Transfer Delay Time in Multiples of
SPI Clock Period
16–43
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