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Channel Timing Control Unit
The negative values of T
a 0% duty cycle. In a similar fashion, the maximum value is T
100% duty cycle. Calculation of duty for other pulse modes can be similarly executed.
Special Consideration for PWM Operation in Over-Modulation
The PWM timing unit can produce PWM signals with variable duty cycle values at the PWM output pins. In pulse
modes 00 and 01, at the extremities of the modulation process, duty cycles of 0% and 100% occur. In pulse modes
01 and 10, at the extremities of the modulation process, duty cycles of 0% and 50% occur. The modulation is called
full off when the lower extremity of modulation is set for any PWM timer period for the corresponding channel.
The modulation is called full on when the higher extremity of modulation is set for any PWM timer period for the
corresponding channel. In between, for other duty cycle values, the operation is termed normal modulation.
Full On Modulation
In pulse modes 00 and 01, a PWM channel is in full on modulation if the high-side output of that channel is asser-
ted. The output is asserted for the whole duration of the period of the PWM timer that channel is referencing. The
conditions for full on modulation are:
• PWM_xH0 DT > PWM_TMy/2 for pulse mode 00
• PWM_xH1 DT > PWM_TMy/2 for pulse modes 00 and 01
In pulse mode 10, a PWM channel is in full on modulation if the high-side output of that channel is asserted. The
output is asserted for the whole duration of the first half period of the PWM timer that the channel is referencing.
The conditions for full on modulation are:
• PWM_xH0 DT > PWM_TMy/2 for pulse mode 10
• PWM_xH1 + DT < PWM_TMy/2 for pulse mode 10
In pulse mode 11, a PWM channel is in full on modulation if the high-side output of that channel is asserted. The
output is asserted for the whole duration of the second half period of the PWM timer that the channel is referenc-
ing. The conditions for full on modulation are:
• PWM_xH0 + DT < PWM_TMy/2 for pulse mode 11
• PWM_xH1 DT > PWM_TMy/2 for pulse mode 11
Full Off Modulation
In pulse modes 00 and 01, a PWM channel is in full off modulation if the high-side output of that channel is deas-
serted. The output is deasserted for the whole duration of the period of the PWM timer that channel is referencing.
The conditions for full off modulation are:
• PWM_xH0 DT < PWM_TMy/2 for pulse mode 00
• PWM_xH1 DT < PWM_TMy/2 for pulse modes 00 and 01
19–22
and T
are not permitted and the minimum permissible value is zero, corresponding to
AH
AL
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
, the PWM switching period, corresponding to a
s
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