Table of Contents
Advertisement
Initializing the DMC (ADSP-SC58x)
To initialize the DMC, use the following steps. If it is not the first time that the DMC initializes, check to first
ensure that the DMC is idle and not in the midst of any activity.
If DMC initialization occurs for the first time after power-up, PHY and PAD initialization is a requirement. The
initialization occurs with the following steps:
For LPDDR mode, set the DMC_PHY_CTL4.DDRMODE bits to 0b'11 (3 in decimal) and set the
DMC_PHY_CTL1.BYPODTEN bit.
For DDR2/DDR3 modes, follow these steps to perform pad impedance calibration:
1. Set the device mode in the DMC_PHY_CTL4.DDRMODE to DDR2 or DD3.
2. Configure the required values in the
ting the DMC_CAL_PADCTL0.CALSTRT bit.
3. Set the DMC_CAL_PADCTL0.CALSTRT bit.
4. Wait for 300 DCLK cycles for the PAD calibration to complete.
Bits 0, 1, 2, 3 of the
are timing trim bits. Always set these bits for DDR2 and DDR3 modes. For example, set these bits during first-
time DMC initialization. Then, software does not need to touch or clear these bits.
Bits 0, 1, 2, 3 of the
register are timing trim bits. Always set these bits for DDR2 and DDR3 modes. For example, set these bits
during first-time DMC initialization. Then, software does not need to touch or clear these bits.
Use the following C code to set these bits for the first time DMC initialization:
*pREG_DMC0_PHY_CTL0 |= 0x0000000F;
*pREG_DMC0_PHY_CTL2 |= 0xFC000000;
Bits 6, 7, 25 and 27 of the
NOTE:
(DDR3/DDR2/LPDDR). The program can set these bits during first-time DMC initialization.
Then, software need not touch or clear these bits. Use the following C code to set these bits for the
first time DMC initialization:
*pREG_DMC0_PHY_CTL3=0xA0000C0;
NOTE:
For DDR3 mode, set bit 1 and configure bits [5:2] of the
CWL + AL in DCLK cycles. For example, in case of DMC0, if CWL =6 and AL =0, program the
DMC_CPHY_CTL
Use the following steps for first-time DMC initialization and reinitialization:
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DMC_CAL_PADCTL0
DMC_PHY_CTL0
register and the bits 31 through 26 of the
register and bits 26, 27, 28, 29, 30, and 31 of the
DMC_PHY_CTL0
DMC_PHY_CTL3
register with the value 0x0000001A.
and
DMC_CAL_PADCTL2
register should always be set for all the DDR modes
DMC_CPHY_CTL
DMC Programming Model
registers without set-
DMC_PHY_CTL2
register
DMC_PHY_CTL2
register with WL =
10–19
Advertisement
Table of Contents
