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ADSP-SC58x SMPU Register Descriptions
Interrupt Details Register
The
register provides the ID of the last signaled interrupt, whether the interrupt was caused by a
SMPU_IDTLS
read or write, and whether the transaction that caused the last signaled interrupt was secure.
ID[7:0] (R)
ID of Transaction
RNW (R)
Read/Write Status
ID[12:8] (R)
ID of Transaction
Figure 13-8: SMPU_IDTLS Register Diagram
Table 13-12: SMPU_IDTLS Register Fields
Bit No.
(Access)
20:8
ID
(R/NW)
1
RNW
(R/NW)
0
SECURE
(R/NW)
13–22
15
14
13
12
11
10
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
Bit Name
ID of Transaction.
The SMPU_IDTLS.ID bit field provides the ID of the transaction that caused the
interrupt.
Read/Write Status.
The SMPU_IDTLS.RNW bit indicates whether the last transaction that caused the in-
terrupt was a read or write.
Secure Status.
The SMPU_IDTLS.SECURE bit indicates whether the last transaction that caused
the interrupt was secure or non-secure.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 Transaction that caused last signaled interrupt was a
write
1 Transaction that caused last signaled interrupt was a
read
0 Transaction that caused last signaled interrupt was non-
secure
1 Transaction that caused last signaled interrupt was se-
cure
2
1
0
0
0
0
SECURE (R)
Secure Status
17
16
0
0
0
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