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Regardless of the DMA_CFG.SYNC setting, the DMA stream has not left the UART transmitter completely at the
time the interrupt request is generated. Transmission can abort in the middle of the stream, causing data loss, when
the UART clock was disabled without extra synchronization with the UART_STAT.TEMT bit.
The UART provides functionality to avoid resource-consuming polling of the UART_STAT.TEMT bit. The
UART_IMSK_SET.EDTPTI bit enables the UART_STAT.TEMT bit to trigger a DMA interrupt. To delay the
DMA completion interrupt until the last data word of a STOP DMA has left the UART, keep the DMA_CFG.INT
bit cleared and set the UART_IMSK_SET.EDTPTI bit instead. Then, the normal DMA completion interrupt is
suppressed. Later, the UART_STAT.TEMT event triggers a DMA interrupt after the last word of the DMA has left
the UART transmit buffers. If DMA_CFG.INT and UART_IMSK.EDTPTI are set, when finishing STOP mode,
the DMA requests two interrupts.
The DMA of the UART module supports 8-bit and 16-bit operation, but not 32-bit operation. It does not support
sign-extension.
Mixing DMA and Core Modes
Switching from DMA mode to core operation dynamically requires some consideration, especially for transmit oper-
ations. By default, the interrupt timing of the DMA is synchronized with the memory side of the DMA FIFOs.
Normally, the transmit DMA completion interrupt is generated after the last byte is copied from the memory into
the DMA FIFO. The transmit DMA interrupt service routine is not yet permitted to disable the DMA_CFG.EN
bit. The interrupt is requested when the DMA_STAT.IRQDONE bit is set. The DMA_STAT.RUN bit, however,
remains set until the data has completely left the transmit DMA FIFO.
When planning to switch from a DMA to core mode, set the DMA_CFG.SYNC bit in the word of the last descrip-
tor or work unit before handing over control. Then, after the interrupt request occurs, software can write new data
into the
UART_THR
register as soon as the UART_STAT.THRE bit permits. If the DMA_CFG.SYNC bit cannot
be set, software can poll the DMA_STAT.RUN bit instead. Alternatively, using the UART_IMSK.EDTPTI bit can
avoid expensive status bit polling.
When switching from core to DMA operation, ensure that the first DMA request is issued properly. If the DMA is
enabled while the UART is still transmitting, no precaution is required. If, however, the DMA is enabled after the
UART_STAT.TEMT bit is high, pulse the UART_IMSK.ETBEI bit to initiate DMA transmission.
Setting Up Hardware Flow Control
Use the following steps to set up UART hardware flow control.
1. Configure automatic or manual hardware flow control for the receiver through the UART_CTL.ARTS bit, or
the transmitter through the UART_CTL.ACTS bit.
2. Configure UART_CTS and UART_RTS polarity through the UART_CTL.FCPOL bit.
On reset, when the UART is not yet enabled and the port multiplexing has not been programmed, the UART_RTS
pin is not driven. Some applications require a resistor pull the UART_RTS signal to either state during reset.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
UART Data Transfer Modes
17–17
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