Control Register Details - Analog Devices ADAU1961 Manual

ADAU1961

CONTROL REGISTER DETAILS

All registers except for the PLL control register are 1-byte write and read registers.
R0: Clock Control, 16,384 (0x4000)
Bit 7 Bit 6
Table 26. Clock Control Register
Bits Bit Name
3 CLKSRC
[2:1] INFREQ[1:0]
0 COREN
R1: PLL Control, 16,386 (0x4002)
Byte Bit 7
0
1
2
3
4 Reserved
5
Table 27. PLL Control Register
Byte Bits Bit Name
0 [7:0] M[15:8]
1 [7:0] M[7:0]
2 [7:0] N[15:8]
3 [7:0] N[7:0]
Downloaded from Elcodis.com electronic components distributor
Bit 5 Bit 4
Reserved
Description
Clock source select.
0 = direct from MCLK pin (default).
1 = PLL clock.
Input clock frequency. Sets the core clock rate that generates the core clock. If the PLL is used, this value is
automatically set to 1024 × f .
S
Setting
00
01
10
11
Core clock enable. Only the R0 and R1 registers can be accessed when this bit is set to 0 (core clock disabled).
0 = core clock disabled (default).
1 = core clock enabled.
Bit 6 Bit 5
R[3:0]
Reserved
Description
PLL denominator MSB. This value is concatenated with M[7:0] to make up a 16-bit number.
PLL denominator LSB. This value is concatenated with M[15:8] to make up a 16-bit number.
M[15:8] (MSB)
00000000
...
00000000
...
11111111
PLL numerator MSB. This value is concatenated with N[7:0] to make up a 16-bit number.
PLL numerator LSB. This value is concatenated with N[15:8] to make up a 16-bit number.
N[15:8] (MSB)
00000000
...
00000000
...
11111111
Bit 3 Bit 2
CLKSRC
Input Clock Frequency
256 × f (default)
S
512 × f
S
768 × f
S
1024 × f
S
Bit 4 Bit 3
M[15:8]
M[7:0]
N[15:8]
N[7:0]
M[7:0] (LSB)
00000000
...
11111101
...
11111111
N[7:0] (LSB)
00000000
...
00001100
...
11111111
Rev. 0 | Page 44 of 76
Bit 1
INFREQ[1:0]
Bit 2 Bit 1
X[1:0]
Lock
Value of M
0
...
253 (default)
...
65,535
Value of N
0
...
12 (default)
...
65,535
Bit 0
COREN
Bit 0
Type
PLLEN