Analog Devices ADSP-SC58 Series Hardware Reference Manual page 450

ADSP-SC58x DMC Register Descriptions
Table 10-21: DMC_MR Register Fields (Continued)
Bit No.
(Access)
8 DLLRST
(R/W)
10–44
Bit Name
DLL Reset.
The DMC_MR.DLLRST bit initiates a DLL reset on the SDRAM. Note that this pa-
rameter applies only for DDR2/DDR3 mode and is reserved for LPDDR mode. For
more information about this operation, see the data sheet for the SDRAM being used
in your system.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
5 6 Clock Cycles for DDR2 and 10 clock cycles for
DDR3
6 7 Clock Cycles for DDR2 and 12 clock cycles for
DDR3
7 8 Clock Cycles for DDR2 and 14 clock cycles for
DDR3
0 Normal Operation
1 Reset DLL