Analog Devices ADSP-SC58 Series Hardware Reference Manual page 962

Table 19-5: ADSP-SC58x PWM Register List (Continued)
Name
PWM_CHA_DT
PWM_CHB_DT
PWM_CHC_DT
PWM_CHD_DT
PWM_CHOPCFG
PWM_CH_DUTY0
PWM_CH_DUTY1
PWM_CL0
PWM_CL0_HP
PWM_CL1
PWM_CL1_HP
PWM_CL_DUTY0
PWM_CL_DUTY1
PWM_CTL
PWM_DCTL
PWM_DH0
PWM_DH0_HP
PWM_DH1
PWM_DH1_HP
PWM_DH_DUTY0
PWM_DH_DUTY1
PWM_DL0
PWM_DL0_HP
PWM_DL1
PWM_DL1_HP
PWM_DLYA
PWM_DLYB
PWM_DLYC
PWM_DLYD
PWM_DL_DUTY0
PWM_DL_DUTY1
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
Channel A Dead-time Register
Channel B Dead-time Register
Channel C Dead-time Register
Channel D Dead-time Register
Chop Configuration Register
Channel C-High Full Duty0 Register
Channel C-High Full Duty1 Register
Channel C-Low Pulse Duty Register 0
Channel C-Low Pulse Duty Register 1
Channel C-Low Duty-1 Register
Channel C-Low Heightened-Precision Duty-1 Register
Channel C-Low Full Duty0 Register
Channel C-Low Full Duty1 Register
Control Register
Channel D Control Register
Channel D-High Duty-0 Register
Channel D-High Pulse Heightened-Precision Duty Register 0
Channel D-High Pulse Duty Register 1
Channel D High Pulse Heightened-Precision Duty Register 1
Channel D-High Full Duty0 Register
Channel D-High Full Duty1 Register
Channel D-Low Pulse Duty Register 0
Channel D-Low Heightened-Precision Duty-0 Register
Channel D-Low Pulse Duty Register 1
Channel D-Low Heightened-Precision Duty-1 Register
Channel A Delay Register
Channel B Delay Register
Channel C Delay Register
Channel D Delay Register
Channel D-Low Full Duty0 Register
Channel D-Low Full Duty1 Register
ADSP-SC58x PWM Register Descriptions
19–41