Table of Contents
Advertisement
PB_03:02 Pins
PC_15:13 Pins
PD_13:12 Pins
PE_02:01 Pins
PE_11:10 Pins
Figure 1-19: UART System Diagram
Enhanced Parallel Peripheral Interface (EPPI)
The
Enhanced Parallel Peripheral Interface (EPPI)
three frame sync (FS) pins. It can support direct connections to active TFT LCDs, parallel A/D and D/A converters,
video encoders and decoders, image sensor modules and other general-purpose peripherals. Each EPPI has two
DMA channels associated with it. Moreover, in some modes, an EPPI can use an extra DMA channel.
PB_05:00 Pins
PD_15:12 Pins
PE_15:00 Pins
Figure 1-20: EPPI System Diagram
Pulse-Width Modulator (PWM)
The
Pulse-Width Modulator (PWM)
Figure 1-21: PWM System Diagram
General-Purpose Counter (CNT)
The
General-Purpose Counter (CNT)
tative of the actual position of the pulse. This conversion is done by integrating (counting) pulses on one or two
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
UARTx_TX
PD_00 Pin
UARTx_RX
UARTx_RTS
UARTx_CTS
Clocked by SCLK0_0
PC_15 Pin
PPI0_Dyy
PD_00 Pin
PPI0_FSy
PPI0_CLK
Clocked by SCLK1_0
module is a flexible and programmable waveform generator.
PWMx_AH
PB_08:06 Pins
PWMx_AL
PB_15:11 Pins
PWMx_BH
PC_00 Pin
PWMx_BL
PD_11:02 Pins
PD_15:14 Pins
PWMx_CH
PE_00 Pin
PWMx_CL
PE_05:04 Pins
PWMx_DH
PE_10:09 Pins
PWMx_DL
PWMx_TRIP0
PF_09:06 Pins
PWMx_SYNC
Clocked by SCLK0_0
converts pulses from incremental position encoders into data that is represen-
UART
UART TX/RX DMA Data Interrupts to SEC/GIC
UART TX/RX DMA Error Interrupts to SEC/GIC
UART Status Interrupts to SEC/GIC
UART_TX/RXDMA Triggers to/from TRU Slaves/Masters
System MMR Write-Protection (WP87:82, 33:31) from SPU
Enable Secure Peripheral (SECUREP87:82, 33:31) from SPU
is a half-duplex, bidirectional port with a dedicated clock pin and
EPPI
EPPI DMA Data Interrupts to SEC/GIC
EPPI DMA Error Interrupts to SEC/GIC
EPPI Status Interrupts to SEC/GIC
EPPIx_CHy_DMA Triggers to/from TRU Slaves/Masters
System MMR Write-Protection (WP108:107, 95) from SPU
Enable Secure Peripheral (SECUREP108:107, 95) from SPU
PWM
EPPI DMA Data Interrupts to SEC/GIC
EPPI DMA Error Interrupts to SEC/GIC
EPPI Status Interrupts to SEC/GIC
EPPIx_CHy_DMA Triggers to/from TRU Slaves/Masters
System MMR Write-Protection (WP108:107, 95) from SPU
Enable Secure Peripheral (SECUREP108:107, 95) from SPU
Peripherals
1–11
Advertisement
Table of Contents
