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Status Register
The
register indicates ECC error status, refresh register status, and bus error status.
L2CTL_STAT
ECCERR7 (R/W1C)
ECC Error Bank 7
ECCERR6 (R/W1C)
ECC Error Bank 6
ECCERR5 (R/W1C)
ECC Error Bank 5
ECCERR4 (R/W1C)
ECC Error Bank 4
ECCERR3 (R/W1C)
ECC Error Bank 3
ECCERR2 (R/W1C)
ECC Error Bank 2
Figure 9-20: L2CTL_STAT Register Diagram
Table 9-21: L2CTL_STAT Register Fields
Bit No.
(Access)
15
ECCERR7
(R/W1C)
14
ECCERR6
(R/W1C)
13
ECCERR5
(R/W1C)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
ECC Error Bank 7.
The L2CTL_STAT.ECCERR7 bit indicates that an ECC double-bit error occurred
inside L2 bank 7.
ECC Error Bank 6.
The L2CTL_STAT.ECCERR6 bit indicates that an ECC double-bit error occurred
inside L2 bank 6.
ECC Error Bank 5.
The L2CTL_STAT.ECCERR5 bit indicates that an ECC double-bit error occurred
inside L2 bank 5.
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
1
0
0
0
0
0
0
Description/Enumeration
0 No Status
1 ECC Double Bit Error
0 No Status
1 ECC Double Bit Error
0 No Status
1 ECC Double Bit Error
ADSP-SC58x L2CTL Register Descriptions
1
0
0
0
ERR0 (R/W1C)
Error Port 0
ERR1 (R/W1C)
Error Port 1
RFRS (R)
Refresh Register Status
ECCERR0 (R/W1C)
ECC Error Bank 0
ECCERR1 (R/W1C)
ECC Error Bank 1
17
16
0
0
9–31
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