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LP Operating Modes
data transmission. If the master wishes to give up the token, it can send back a user-defined token release word and
thereafter clear its token flag. Simultaneously, the slave examines the data sent back and if it is the token release
word, the slave sets its token, and can thereafter transmit.
The link port protocol includes handshake mechanism to inform the other end of transfer (transmit or receive) of an
enable instance. However, it does not support handshakes to inform a disable instance, while a chunk of data trans-
fers. The application must assume the disabled state of the other end, and take appropriate action.
For example, in a multi-processing environment, a receiver did not read its full FIFO for an extended time due to
internal bus arbitrations. The transmitter can require software or a peripheral timer-based timeout to inform the
application that the LP_ACK signal is low for an extended time period.
LP Operating Modes
The link port does not have particular modes of operation, as the peripheral is based on a simple protocol. The
following sections explain the data transfer modes, using the core and using DMA.
•
Core Data Transfers
•
DMA Data Transfers
LP Data Transfer Modes
This section describes link port DMA and core data transfers.
Core Data Transfers
If DMA is disabled for a link port buffer, the processor core can write or read internal FIFO buffers as a memory-
mapped register through the MMR access bus. In order to avoid FIFO overflow or underflow, the core can access
the FIFO registers in one of the two following ways.
1. Access link port registers using an interrupt service routine (ISR) mapped to the data request interrupt of the
link port. The interrupt request remains high only if the FIFO is accessible (if the FIFO is not full in transmit
mode and not empty in receive mode).
2. Poll the FIFO status bits of the
receive FIFO if not empty.
DMA Data Transfers
Dedicated DMA channels are available for each link port. DMA-related activity is explained in the following steps.
1. Data Receive – Once the DMA channel and link port module are configured and enabled, the external device
begins writing data to the FIFO through the data pins of the link port. The FIFO detects this activity and in
turn sends a DMA request. After the request is granted, the DMA transfer progresses until the FIFO is empty.
2. Data Transmit – Once the DMA channel and link port module are configured and enabled, setting the
LP_CTL.EN bit automatically asserts a DMA request when the transmit FIFO is empty. After the request is
granted, DMA fills the FIFO. The external device begins reading data from the FIFO through the data pins of
15–12
register. Write to the transmit FIFO if not full or read from the
LP_STAT
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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