Analog Devices ADSP-SC58 Series Hardware Reference Manual page 580

PORT Event Control
Figure 14-3: ADSP-SC57x/SC58x PINTx Block Diagram
As shown in the PINTx Block Diagram, each port is subdivided into two 8-pin half ports, upper (PxH) and lower
(PxL). The PINT_ASSIGN
er half units (eight pins) can be forwarded to either byte 0 or byte 2 of the PINTx blocks, and the upper half units
(eight pins) can be forwarded to either byte 1 or byte 3 of the PINTx blocks.
When a half port is assigned to a byte in any PINTx block, the state of the eight pins appears in the
PINT_PINSTATE register, regardless of whether the pin is enabled for GPIO or peripheral functions (input or
output). When neither the input nor output drivers of the pin are enabled, the pin state is read as zero. The
PINT_PINSTATE register reports the inverted state of the pin when the
signal inverter. The inverter can be enabled on an individual bit-by-bit basis. Each bit in the PINT_INV_SET/
PINT_INV_CLR register pair represents a pin signal.
By default, PORT interrupt request generation is level-sensitive, and an interrupt request occurs when the enabled
pin is sensed as active high. Use the
to instead be edge-sensitive (rising edge generates the interrupt request). Use the
the polarity such that the PINTx block generates the interrupt request on active-low signals or falling edges.
The PINTx modules also assist when both signal edges must generate unique interrupt requests. If two different
interrupt requests are required, the
blocks, where one block inverts the signal in the
ion, a unique software routine is associated with the hardware PINTx block that is generating the unique interrupt
request for each signal edge. When both signal edges can be serviced by the same interrupt request, each half port
can be routed to two separate bytes within a single PINTx block using the
14–8
PINT2
BYTE3 BYTE2 BYTE1
PCH PDH
PCL PDL PCH PDH
PINT1
BYTE3
BYTE2 BYTE1
PBH PCH PBL PCL PBH PCH
PINT0
BYTE3 BYTE2 BYTE1
PAH PBH PAL PBL PAH PBH
registers control the 8-bit multiplexers associated with these half ports, where the low-
PINT_EDGE_SET
PINT_ASSIGN
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
IRQ18
PINT5
BYTE0 BYTE3
PFH PGH
PCL PDL PFL
IRQ17
PINT4
BYTE3
BYTE0
PBL PCL PEH PFH PEL
IRQ16
PINT3
BYTE0 BYTE3
PAL PBL PDH PEH PDL
register to change the interrupt request genearion scheme
registers can route a single input signal to two different PINTx
PINT_INV_SET register and the other one does not. In this fash-
IRQ21
BYTE2 BYTE1 BYTE0
PGL PFH PGH PFL PGL
IRQ20
BYTE2 BYTE1 BYTE0
PFL PEH PFH PEL PFL
IRQ19
BYTE2 BYTE1 BYTE0
PEL PDH PEH PDL PEL
PINT_INV_SET register activates the
PINT_INV_SET
PINT_ASSIGN register, and then one of
register to invert