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ADSP-SC58x UART Register Descriptions
Table 17-19: UART_STAT Register Fields (Continued)
Bit No.
(Access)
9
ASTKY
(R/W1C)
8
TFI
(R/W1C)
7
TEMT
(R/NW)
17–46
Bit Name
Address Sticky.
The UART_STAT.ASTKY bit is used in multi-drop bus mode to indicate whether a
peripheral is currently being addressed. This bit is a sticky version of the
UART_STAT.ADDR bit and is set by hardware when setting the
UART_STAT.ADDR bit. The UART_STAT.ASTKY bit can only be cleared by soft-
ware with a write-one-to-clear (W1C) operation. With the UART_STAT.ASTKY bit
set, words will be received irrespective of the UART_CTL.MOD bit or
UART_STAT.ADDR bit selection. With the UART_STAT.ASTKY bit cleared, only
address words (UART_CTL.MOD bit set) will be received and words with
UART_CTL.MOD bit cleared are ignored (not moved from the RSR to the RX FIFO)
in MDB mode. The UART_STAT.ASTKY bit does not affect reception in non-MDB
modes.
Transmission Finished Indicator.
The UART_STAT.TFI bit is a sticky version of the UART_STAT.TEMT bit. While
UART_STAT.TEMT is automatically cleared by hardware when new data is written to
the
UART_THR
cleared by software (W1C). The UART_STAT.TFI bit enables more flexible transmit
interrupt request timing.
TSR and THR Empty.
The UART_STAT.TEMT bit indicates that the
ters and the
write to the
UART_STAT.TEMT bit can also be used as indicator that pending UART transmis-
sion is completed. At that time, it is safe to disable the UART_CTL.EN bit or to
three-state the off-chip line driver.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 ADDR bit has not been set
1 ADDR bit has been set
register, the sticky UART_STAT.TFI bit remains set, until it is
0 TEMT did not transition from 0 to 1
1 TEMT transition from 0 to 1
UART_TSR
register are empty. In this case, the program is permitted to
UART_THR
and
UART_TAIP
0 Not empty TSR/THR
1 TSR/THR Empty
UART_THR
and
UART_TAIP
registers twice without losing data. The
regis-
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