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Data Transfer Modes
• When EPPI_CTL.DLEN =24, the EPPI packs four 24-bit words into three 32-bit words.
When EPPI_CTL.PACKEN =0, the EPPI receives the incoming data and sends it on the bus as-is. If
EPPI_CTL.DLEN is less than or equal to 16 bits, the DMA is a 16-bit DMA; otherwise it is a 32-bit DMA.
Data Packing for Transmit Modes
For transmit modes, if the EPPI_CTL.DLEN bit =1 and the DMA is a 32-bit DMA, the EPPI unpacks the 32-bit
word according to the EPPI_CTL.DLEN and EPPI_CTL.SWAPEN bit settings.
If EPPI_CTL.SWAPEN =1, the EPPI transmits the most significant bits as the first data, and if
EPPI_CTL.SWAPEN =0, the EPPI transmits the least significant bits as the first data. The unpacking options for
the EPPI_CTL.DLEN bits are as follows.
• When EPPI_CTL.DLEN =8, the EPPI transmits one 32-bit word from memory as four 8-bit data words.
• For EPPI_CTL.DLEN values greater than 8 bits but less than or equal to 16 bits, the EPPI transmits one 32-
bit word from memory as two 16-bit data words.
• When EPPI_CTL.DLEN =18 or 24, the EPPI transmits three 32-bit words from memory as four data words.
Sign-Extended and Zero-Filled Data
The following list describes the bit settings and functionality for sign-extending and zero-filling data.
• For EPPI_CTL.DLEN equal to 10, 12 or 14, data is zero-filled or sign-extended to 16 bits.
• For EPPI_CTL.DLEN equal to 18 bits, data is zero-filled or sign-extended to 24 bits if packing is enabled,
and zero-filled or sign-extended to 32 bits if packing is disabled.
• For EPPI_CTL.DLEN equal to 24 bits, data is zero-filled or sign-extended to 32 bits if packing is disabled.
• For EPPI_CTL.DLEN equal to 8 bits, data is zero-filled or sign-extended to 16 bits if packing is disabled.
• If EPPI_CTL.SIGNEXT =1, then the data is sign-extended, otherwise it is zero-filled.
Split Receive Modes
The control register has three control bits for split receive modes: EPPI_CTL.SPLTEO,
EPPI_CTL.SUBSPLTODD, and EPPI_CTL.DMACFG. Packing is not valid in split modes.
• If EPPI_CTL.SPLTEO =1, the EPPI splits the incoming data stream into two substreams, an even stream,
and an odd stream, and packs them separately.
• The EPPI_CTL.SUBSPLTODD bit is available only when EPPI_CTL.SPLTEO =1. When
EPPI_CTL.SUBSPLTODD =1, the EPPI subsplits the odd substream, and packs the streams separately.
• The EPPI_CTL.DMACFG bit is also available only if EPPI_CTL.SPLTEO =1. If EPPI_CTL.DMACFG
=1, the EPPI uses two DMA channels and if EPPI_CTL.DMACFG =0, the EPPI uses only one DMA chan-
nel.
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ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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