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SCI Priority Mask Register n
The SEC SCI priority mask register (SEC_CPMSK[n]) contains the SCI priority mask for core n and includes a
register lock.
Figure 7-10: SEC_CPMSK[n] Register Diagram
Table 7-9: SEC_CPMSK[n] Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
7:0
PRIO
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
0
0
0
PRIO (R/W)
IRQ Priority Mask
31
30
29
0
0
0
LOCK (R/W)
Lock
Bit Name
Lock.
If the global lock is enabled (SPU_CTL.GLCK bit =1) and the
SEC_CPMSK[n].LOCK bit is enabled, the
IRQ Priority Mask.
The SEC_CPMSK[n].PRIO contains the system interrupt priority mask for core n.
The core uses the SEC_CPMSK[n].PRIO field to mask (block) interrupts below the
specified level.
12
11
10
9
8
7
6
5
0
0
0
0
0
1
1
1
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
0 Unlock
1 Lock
0 Priority level 0 (highest)
1-254
255 Priority level 255 (lowest)
ADSP-SC58x SEC Register Descriptions
4
3
2
1
0
1
1
1
1
1
20
19
18
17
16
0
0
0
0
0
SEC_CPMSK[n]
register is read only.
7–31
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