Analog Devices ADSP-SC58 Series Hardware Reference Manual page 410

DMC Functional Description
Table 10-1: ADSP-SC58x DMC Register List
Name
DMC_CFG
DMC_CPHY_CTL
DMC_CTL
DMC_DLLCTL
DMC_DT_CALIB_ADDR
DMC_DT_DATA_CALIB_DATA0
DMC_DT_DATA_CALIB_DATA1
DMC_EFFCTL
DMC_EMR1
DMC_EMR2
DMC_MR
DMC_MR1
DMC_MR2
DMC_MSK
DMC_PRIO
DMC_PRIO2
DMC_PRIOMSK
DMC_PRIOMSK2
DMC_RDDATABUFID1
DMC_RDDATABUFID2
DMC_RDDATABUFMSK1
DMC_RDDATABUFMSK2
DMC_STAT
DMC_TR0
DMC_TR1
DMC_TR2
ADSP-SC58x DMC Register List
A set of registers governs DMCPHY operations. For more information on functionality, see the register descriptions.
10–4
Description
Configuration Register
Controller to PHY Interface Register
Control Register
DLL Control Register
Data Calibration Address Register
Data Calibration Data 0 Register
Data Calibration Data 1 Register
Efficiency Control Register
Shadow EMR1 DDR2 Register
Shadow EMR2 Register (DDR2)/Shadow EMR Register (LPDDR)
Shadow MR Register (DDR2/LPDDR), Shadow MR0 Register (DDR3)
Shadow MR1 Register (DDR3)
Shadow MR2 Register (DDR3)
Mask (Mode Register Shadow) Register
Priority ID Register 1
Priority ID Register 2
Priority ID Mask Register 1
Priority ID Mask Register 2
DMC Read Data Buffer ID Register 1
DMC Read Data Buffer ID Register 2
DMC Read Data Buffer Mask Register 1
DMC Read Data Buffer Mask Register 2
Status Register
Timing 0 Register
Timing 1 Register
Timing 2 Register
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference