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ADSP-SC58x DMC Register Descriptions
Calibration PAD Control 2 Register
The
DMC_CAL_PADCTL2
required driver impedance and the On Die Termination (ODT) value using the corresponding bits in this register.
These values are translated by the auto calibration logic into a corresponding drive strength control inside the PHY
and then routed to the PADS. Auto-calibration starts as soon as the DMC_CAL_PADCTL0.CALSTRT bit is pro-
grammed. The DCLK needs to be set at the required frequency before setting the
DMC_CAL_PADCTL0.CALSTRT bit.
IMPWRDQ (R/W)
Impedance for DQ
IMPRTT (R/W)
Impedance RTT Value
Figure 10-29: DMC_CAL_PADCTL2 Register Diagram
Table 10-39: DMC_CAL_PADCTL2 Register Fields
Bit No.
(Access)
23:16
IMPRTT
(R/W)
15:8
IMPWRDQ
(R/W)
7:0
IMPWRAD
(R/W)
10–70
register sets the pad calibration controls. The DMC pads can be auto-calibrated to the
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit Name
Impedance RTT Value.
Writing to the DMC_CAL_PADCTL2.IMPRTT bit field sets the required initializa-
tion sequence to program the termination impedance for the data PADS and the DQS
PADS.
Impedance for DQ.
The DMC_CAL_PADCTL2.IMPWRDQ bit field sets the drive impedance for DQ
DQS CLK and DM pads. Data pads (DDR_DQ[NN]), DQS pads (DDR_LDQS, /
DDR_LDQS, DDR_UDQS, /DDR_UDQS), Clock pads (DDR_CK, /DDR_CK), DM
pads (DDR_UDM, DDR_LDM)
Impedance for ADDR_CMD PADS.
The DMC_CAL_PADCTL2.IMPWRAD bit field sets the desired drive for address pads
(DDR_A[NN]), Command pads (DDR_RAS, DDR_CAS, DDR_CKE, DDR_WE,
DDR_CS[N], DDR_ODT).
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Description/Enumeration
IMPWRAD (R/W)
Impedance for ADDR_CMD PADS
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