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• Fault Output. This configuration alows the SEC to indicate the fault status based on the
SEC_FCTL.CMS bit configuration.
• Computer Operating Normally (COP) mode. To configure fault output for COP mode, set the
SEC_FCTL.FOEN bit to enable fault output. Set the SEC_FCTL.CMS bit to select COP mode to
toggle the fault pin when no fault is active. Program the
width value for the COP toggled output pin.
• Fault mode. Set the SEC_FCTL.FOEN bit to enable fault output. The SEC_FCTL.CMS bit
should be set to Fault mode to toggle the fault pin when a fault is active.
3. If required, program the Fault Input to sample fault inputs from external devices on fault pins. Configure the
SEC_FCTL.FIEN bit to enable the SEC to sample a fault input from an external device.
ADDITIONAL INFORMATION: The SEC_FCTL.FIEN bit should be set only while the SEC_FCTL.EN
bit is low. If the SEC_FCTL.EN bit is already high and the SEC_FCTL.FIEN bit needs to be set, the
SEC_FCTL.EN bit should be cleared first. Fault input can only be enabled when Fault mode is selected by the
SEC_FCTL.CMS bit.
4. Program the required fault delay to the SEC_FDLY.COUNT bit field if a delay between fault source assertion
and the fault response is required.
5. Configure the
SEC_FCTL
ADDITIONAL INFORMATION: The SEC_FCTL.EN bit should be set only while the SEC_FSTAT.ACT
bit is low.
6. Write to the control register of a specific source register using the
as a fault.
Configuring a System Source to Interrupt a Core
To configure a system source to interrupt a core, the SEC itself must be enabled with the source interface (SSI) and
core interface (SCI) properly initialized. Specifically, the SCI must be set up to accept interrupt signaling from the
SEC and pass them to the specified core, and the SSI must properly enable each of the peripheral interrupt sources
to generate interrupt signals and optionally define a priority scheme that overrides the default priority settings. In
summary:
1. Write to the
SEC_GCTL
2. Write to the appropriate SCI
3. Write to the appropriate SSI
set the core target field to map the source to the desired SCI.
4. (Optional) By default, all the SEC interrupts are grouped as a single priority level, so passing of peripheral in-
terrupt requests from the SEC is based solely on the default enumerated source ID. By programming the
SEC_CPLVL[n].PLVL register, interrupt sources can be grouped into priority levels within the SEC such
that arbitration is first performed by source ID within a grouped priority level before proceeding to the next
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register to enable the SEC.
register to enable the SEC.
SEC_CCTL[n]
register to enable SEC interrupts to be sent to that core.
SEC_SCTL[n]
register to enable that peripheral as an interrupt source and to
period register with a desired
SEC_FCOPP
SEC_SCTL[n]
register to enable the source
Programming Examples
7–19
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