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Fault Delay Current Register
The SEC fault delay current register (SEC_FDLY_CUR) contains the active count (SEC_FDLY_CUR.COUNT
field) in (SEC) clock periods for the delay from fault pending to fault active, when actions are enabled. The count is
loaded from the
SEC_FDLY
ments the value in
SEC_FDLY_CUR
Figure 7-19: SEC_FDLY_CUR Register Diagram
Table 7-18: SEC_FDLY_CUR Register Fields
Bit No.
(Access)
31:0
COUNT
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register when a fault becomes pending (SEC_FSTAT.PND bit is set). The SEC decre-
each (SEC) clock cycle while the SEC_FSTAT.PND bit is set.
15
14
0
COUNT[15:0] (R)
Fault Delay
31
30
0
COUNT[31:16] (R)
Fault Delay
Bit Name
Fault Delay.
The SEC_FDLY_CUR.COUNT bit field is the active count in (SEC) clock periods for
the delay from fault pending to fault active, when actions are enabled.
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
29
28
27
26
25
24
23
22
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x SEC Register Descriptions
6
5
4
3
2
1
0
0
0
0
0
0
0
0
21
20
19
18
17
16
0
0
0
0
0
0
0
7–43
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