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Functional Description
recover its blocking capability before the complementary switch is turned on. This time delay prevents a potentially
destructive short-circuit condition from developing across the dc link capacitor of a typical voltage source inverter.
Duty Cycle
The proportion of on time to the regular interval or period of time (expressed in percent, 100% being fully on). A
low duty cycle corresponds to low power, because the power is off for most of the time.
Switching Frequency
The average value of voltage (and current) fed to the load is controlled by turning the switch between supply and
load on and off at a fast rate. The longer the switch is on compared to the off periods, the higher the total power
supplied to the load.
Architectural Concepts
A clock, whose period is t
, drives the PWM controller. The PWM generator produces four pairs (four high-
SCLK0_0
side and four low-side) of PWM signals on the eight PWM output pins. Each high and low pair signal constitutes a
channel. For example, the PWM_AL and PWM_AH signals make up channel A, and the PWM_BL and PWM_BH
signals make up channel B, and so on.
Each pair of channel outputs references either a main timer or an independent timer. These timers operate on a
switching frequency determined by the
through
registers. There are two duty registers for ev-
PWM_TM0
PWM_TM4
ery PWM output. The registers enable generation of symmetrical or asymmetrical waveforms. The waveforms pro-
duce lower harmonic distortion in three-phase PWM inverters, with minimal CPU intervention.
Block Diagram
The PWM Block Diagram figure shows a block diagram that represents the main functional blocks of the PWM
controller.
19–6
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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