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Control Register
The RCU control register (RCU_CTL) provides a register lock, enables for the core and system reset requests inputs
and control for the Reset Output pin.
CRSTREQEN (R/W)
Core Reset Request Enabled
SRSTREQEN (R/W)
System Reset Request Enabled
RSTOUTDSRT (R0/W)
Reset Out Deassert
LOCK (R/W)
Lock
Figure 6-4: RCU_CTL Register Diagram
Table 6-9: RCU_CTL Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
9
CRSTREQEN
(R/W)
8
SRSTREQEN
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Lock.
If the global lock bit is set (SPU_CTL.GLCK bit =1) and the RCU_CTL.LOCK bit is
set, the
any system reset event.
Core Reset Request Enabled.
The RCU_CTL.CRSTREQEN bit controls whether the SYSCLK domain source(s) of
reset is/are enabled to reset the core(s) when asserted. This bit is cleared by hard reset
or any system reset event.
System Reset Request Enabled.
The RCU_CTL.SRSTREQEN bit controls whether the SYSCLK domain sources of
reset are enabled to do a system reset when asserted. This bit is cleared by a hard reset.
9
8
7
6
5
4
3
2
1
1
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
RCU_CTL
register is read only (locked). This bit is cleared by a hard reset or
0 Unlock
1 Lock
0 Disabled
1 Enabled
0 Disabled
1 Enabled
ADSP-SC58x RCU Register Descriptions
1
0
0
0
SYSRST (R0/W)
System Reset
RSTOUTASRT (R0/W)
Reset Out Assert
17
16
0
0
6–13
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