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ADSP-21368 SHARC

Processor

®

Hardware Reference

Includes ADSP-21367, ADSP-21369,

ADSP-21371, ADSP-21375

Revision 1.0, September 2006

Part Number

82-000100-01

Analog Devices, Inc.

One Technology Way

a

Norwood, Mass. 02062-9106

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Page 1 ADSP-21368 SHARC Processor ® Hardware Reference Includes ADSP-21367, ADSP-21369, ADSP-21371, ADSP-21375 Revision 1.0, September 2006 Part Number 82-000100-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106...
Page 2 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
Page 3: Table Of Contents
CONTENTS PREFACE Purpose of This Manual ............... xxxi Intended Audience ............... xxxi Manual Contents ................ xxxii What’s New in This Manual ............xxxiv Technical or Customer Support ........... xxxv Supported Processors ..............xxxvi Product Information ..............xxxvi MyAnalog.com ..............xxxvii Processor Product Information ..........
Page 4 Contents Processor Peripherals ............... 1-7 I/O Processor ..............1-7 Digital Audio Interface (DAI) ..........1-9 Digital Peripheral Interface (DPI) ........1-10 Development Tools ..............1-10 Differences From Previous Processors .......... 1-11 I/O Architecture Enhancements ..........1-11 Instruction Set Enhancements ..........1-12 I/O PROCESSOR General Procedure for Configuring DMA ........
Page 5 Contents Port, Buffer, and DMA Control Registers ....... 2-26 Addressing ................2-29 External Port DMA ..............2-35 Setting Up and Starting Chained DMA ........2-36 Delay Line DMA ..............2-38 Serial Port DMA ................. 2-40 Setting Up and Starting Chained DMA ........2-40 Inserting a TCB in an Active Chain ........
Page 6 Contents EMI Registers and Signals ............. 3-16 External Port Arbitration Logic ......... 3-18 Channel Freezing .............. 3-18 Managing Data Paths ............3-18 External Memory Interface Pins ..........3-19 Asynchronous Memory Interface ..........3-20 AMI Timing Control ..............3-21 Wait States ................3-21 Bus Idle Cycles ..............
Page 7 Contents SDRAM Control Status Register (SDSTAT) ......3-49 SDRAM Refresh Rate Control Register (SDRRC) ....3-49 SDRAM Initialization ............3-51 SDRAM Address Mapping ............ 3-51 SDRAM Controller Address Mapping ....... 3-58 SDC Operation ..............3-58 Single Bank Operation ............3-60 Multibank Operation (ADSP-2137x Processors) ....
Page 8 Contents SDRAM Timing ..............3-74 SDRAM Read Optimization ..........3-75 External Memory Access Restrictions ........ 3-78 Shared Memory Interface ............3-79 Shared Memory Bus Arbitration ..........3-79 Bus Arbitration Protocol ........... 3-82 Bus Arbitration Priority (RPBA) ........3-86 Bus Mastership Time-out ..........3-87 Bus Synchronization After Reset ..........
Page 9 Contents Making Connections in the SRUs ..........4-15 DAI/SRU1 Connection Groups ..........4-18 Group A Connections—Clock Signals ....... 4-19 Group B Connections—Data Signals ......... 4-25 Group C Connections—Frame Sync Signals ...... 4-31 Group D Connections—Pin Signal Assignments ....4-36 Group E Connections—Interrupts and Miscellaneous Signals ................
Page 10 Contents Configuring Peripherals Using SRU1 .......... 4-71 Configuring the SPORTs ............4-71 Configuring the PCGs ............4-72 Configuring Peripherals Using SRU2 .......... 4-72 Configuring the SPI .............. 4-72 Choosing the Pin Enable for the SPI Clock ....... 4-72 Configuring the Two Wire Interface ........4-73 Using the SRU() Macro to Configure the DAI ...................
Page 11 Contents Left-Justified Sample Pair Mode Control Bits ..... 5-17 Setting Word Length (SLEN) ..........5-17 Enabling SPORT Master Mode (MSTR) ......5-18 Selecting Transmit and Receive Channel Order (FRFS) ..5-18 Selecting Frame Sync Options (DIFS) ....... 5-18 Enabling SPORT DMA (SDEN) ........5-19 I2S Mode ................
Page 12 Contents Active Low Versus Active High Frame Syncs ......5-39 Sampling Edge for Data and Frame Syncs ......5-39 Early Versus Late Frame Syncs ..........5-40 Data-Independent Frame Syncs ..........5-41 Frame Sync Error Detection ..........5-42 Data Word Formats ..............5-43 Word Length ................
Page 13 Contents SPORT Programming Examples ..........5-82 SERIAL PERIPHERAL INTERFACE PORTS Functional Description ..............6-2 SPI Interface Signals ..............6-4 SPI Clock Signal (SPICLK) ............. 6-4 SPICLK Timing ..............6-5 SPI Slave Select Input (SPIDS) ..........6-6 SPI Flag Signals (SPIFLG3-0) ..........6-6 Master Out Slave In (MOSI) ...........
Page 14 Contents DMA Error Interrupts ............6-25 DMA Chaining ..............6-27 SPI Transfer Formats ..............6-27 Beginning and Ending an SPI Transfer ........6-29 SPI Word Lengths ..............6-31 8-Bit Word Lengths .............. 6-31 16-Bit Word Lengths ............6-32 32-Bit Word Lengths ............6-32 Packing .................
Page 15 Contents Packing Mode 10 .............. 7-10 Packing Mode 01 .............. 7-11 Packing Mode 00 .............. 7-11 Clocking Edge Selection ............7-12 Hold Input ................7-12 PDAP Strobe ................. 7-14 FIFO Control and Status ............7-15 FIFO to Memory Data Transfer ........... 7-16 IDP Transfers Using the Core ..........
Page 16 Contents Switching Frequencies ............. 8-5 Dead Time ................8-6 Duty Cycles ................8-7 Duty Cycles and Dead Time ..........8-8 Over Modulation .............. 8-12 Update Modes ..............8-15 Single Update ..............8-15 Double Update ..............8-15 Configurable Polarity ............8-15 PWM Pins and Signals ............
Page 17 Contents S/PDIF Transmitter Registers ..........9-12 Modes of Operation .............. 9-12 Standalone Mode .............. 9-13 Structure of the Serial Input Data .......... 9-14 S/PDIF Receiver ................. 9-16 S/PDIF Receiver Registers ............. 9-17 SRU1 Receiver Signals ............9-18 Phase-Locked Loop ..............9-19 Channel Status Decoding ............
Page 18 Contents Status Bits ................ 9-26 Interrupted Data Streams on the Receiver ......9-27 ASYNCHRONOUS SAMPLE RATE CONVERTER Theory of Operation ..............10-2 Conceptual Model ..............10-4 Hardware Model ..............10-7 Sample Rate Converter Architecture ..........10-8 Group Delay ............... 10-12 SRC Operation .................
Page 19 Contents SRU Programming .............. 10-22 SRC Mute-Out Interrupt ............. 10-23 Sample Rate Ratio ............... 10-23 Programming Summary ............10-23 UART PORT CONTROLLER Serial Communications ............... 11-2 UART Control and Status Registers ..........11-3 UARTxLCR Registers ............11-3 UARTxLSR Register .............. 11-4 UARTxTHR Register ............
Page 20 Contents TWIDIV Register ..............12-5 Slave Mode Control Register ..........12-5 Slave Mode Address Register ..........12-6 Slave Mode Status Register ............ 12-6 Master Mode Control Register ..........12-6 Master Mode Address Register ..........12-6 Master Mode Status Register ..........12-7 FIFO Control Register ............
Page 21 Contents Master Mode Clock Setup ........... 12-17 Master Mode Transmit ............12-17 Master Mode Receive ............12-18 Repeated Start Condition ............ 12-19 Transmit/Receive Repeated Start Sequence ....... 12-19 Receive/Transmit Repeated Start Sequence ....... 12-21 Electrical Specifications ............. 12-22 PRECISION CLOCK GENERATORS Clock Outputs ................
Page 22 Contents SYSTEM DESIGN Processor Pin Descriptions ............14-2 Pin Multiplexing ..............14-2 Choosing EP Data Mode ..........14-6 Interrupt and Timer Pins ............14-8 Core-Based Flag Pins ............. 14-8 Programming Flags ............14-9 RESETOUT/CLKOUT/RUNRSTIN ......14-12 JTAG Interface Pins ............14-12 Clock Derivation ..............
Page 23 Contents Designing for High Frequency Operation ........14-33 Clock Specifications and Jitter ..........14-33 Other Recommendations and Suggestions ......14-34 Decoupling Capacitors and Ground Planes ......14-35 Oscilloscope Probes ............. 14-35 Recommended Reading ............14-36 Booting ..................14-37 External Port Booting ............14-39 Booting Through the AMI ..........
Page 24 Contents DMA Stalls ................. 14-56 IOP Buffer Stalls ..............14-56 REGISTER REFERENCE I/O Processor Registers ..............A-2 Notes on Reading Register Drawings ........A-3 System Control Register (SYSCTL) ......... A-5 System Status Register (SYSTAT) ..........A-9 External Port Registers ..............A-10 External Port Control Register (EPCTL) .......
Page 25 Contents SPORT Compand Registers (SPxCCSy) ........ A-47 SPORT Error Control Register (SPERRCTLx) ...... A-48 SPORT Error Status Register (SPERRSTAT) ......A-49 SPORT DMA Index Registers (IISPx) ........A-50 SPORT DMA Modifier Registers (IMSPx) ......A-50 SPORT DMA Count Registers (CSPx) ......... A-51 SPORT Chain Pointer Registers (CPSPx) ......
Page 26 Contents Input Data Port Control Register 1 (IDP_CTL1) ....A-68 Input Data Port FIFO Register (IDP_FIFO) ......A-69 Input Data Port DMA Control Registers ....... A-70 IDP_DMA_Ix ..............A-70 IDP_DMA_Mx ..............A-71 IDP_DMA_Cx ..............A-71 Input Data Port Ping-Pong DMA Registers ......A-72 IDP Ping-Pong Index Registers (IDP_DMA_IxA) .....
Page 27 Contents Sony/Philips Digital Interface Registers ........A-86 Transmitter Control Register (DITCTL) ....... A-86 Left Channel Status for Subframe A Registers (DITCHANAx) ..........A-89 Right Channel Status for Subframe B Registers (DITCHANBx) ..........A-90 User Bits Buffer Registers for Subframe A Registers (DITUSRBITAx) ..........
Page 28 Contents DPI Resistor Pull-up Enable Register (DPI_PIN_PULLUP) ............A-115 DPI Pin Buffer Status Register (DPI_PIN_STAT) ....A-116 DPI Interrupt Controller Registers ........A-116 UART Control and Status Registers .......... A-118 Line Control Registers (UARTxLCR) ........A-118 Line Status Registers (UARTxLSR) ........A-120 Transmit Hold Registers (UARTxTHR) .......
Page 29 Contents Master Control Register (TWIMCTL) ........ A-136 Master Address Register (TWIMADDR) ......A-139 Master Status Register (TWIMSTAT) ......... A-140 FIFO Control Register (TWIFIFOCTL) ......A-143 FIFO Status Register (TWIFIFOSTAT) ......A-145 Interrupt Source Register (TWIIRPTL) ......A-147 Interrupt Enable Register (TWIIMASK) ......A-150 8-Bit Transmit FIFO Register (TXTWI8) ......
Page 30 Contents Power Management Control Register (PMCTL) ..............A-170 Hardware Breakpoint Control Register ........A-175 Enhanced Emulation Status Register ......... A-179 INTERRUPTS Interrupt Vector Tables ..............B-1 Interrupt Priorities ..............B-4 Interrupt Registers ................ B-6 Interrupt Register (LIRPTL) ........... B-6 Interrupt Latch Register (IRPTL) .......... B-13 Interrupt Mask Register (IMASK) .........
Page 31: Preface
Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices processors. This manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices...
Page 32: Manual Contents
Manual Contents Manual Contents The manual consists of: • Chapter 1, “Introduction” Provides an architectural overview of the ADSP-21367/8/9 and ADSP-2137x SHARC processors. • Chapter 2, “I/O Processor” Describes ADSP-21367/8/9 and ADSP-2137x processors input/output processor architecture and direct memory accesses (DMA) for the peripherals that have this feature.
Page 33 Preface • Chapter 8, “Pulse Width Modulation” Describes the implementation and use of the pulse width modula- tion module which provides a technique for controlling analog circuits with the microprocessor’s digital outputs. • Chapter 9, “S/PDIF Transmitter/Receiver” Provides information on the use of the Sony/Philips Digital Inter- face which is a standard audio file transfer format that allows the transfer of digital audio signals from one device to another without having to be converted to an analog signal.
Page 34: What's New In This Manual
What’s New in This Manual • Appendix A, “Register Reference” Provides a graphical presentation of all registers and describes the bit usage in each register. • Appendix B, “Interrupts” Provides a complete listing of the registers that are used to config- ure and control interrupts.
Page 35: Technical Or Customer Support
Instructions From External Memory” on page 3-3 “Running Reset (ADSP-2137x)” on page 14-22. Technical or Customer Support You can reach Analog Devices, Inc. Customer Support in the following ways: • Visit the Embedded Processing and DSP products Web site at http://www.analog.com/processors/manuals • E-mail tools questions to processor.tools.support@analog.com...
Page 36: Supported Processors
Supported Processors Supported Processors The following is the list of Analog Devices, Inc. processors supported in VisualDSP++®. Blackfin® (ADSP-BFxxx) Processors The name Blackfin refers to a family of 16-bit, embedded processors. VisualDSP++ currently supports the following Blackfin families: ADSP-BF53x, ADSP-BF54x, and ADSP-BF56x.
Page 37: Myanalog.com
Preface MyAnalog.com is a free feature of the Analog Devices Web site that allows MyAnalog.com customization of a Web page to display only the latest information on products you are interested in. You can also choose to receive weekly e-mail notifications containing updates to the Web pages that meet your interests.
Page 38: Related Documents
Related Documents The following publications that describe the ADSP-2136x SHARC pro- cessors (and related processors) can be ordered from any Analog Devices sales office: • ADSP-21362 SHARC Processor Data Sheet • ADSP-21363 SHARC Processor Data Sheet • ADSP-21364 SHARC Processor Data Sheet •...
Page 39: Online Technical Documentation
Preface For information on product related development software and Analog Devices processors, see these publications: • VisualDSP++ User’s Guide • VisualDSP++ C/C++ Compiler and Library Manual for SHARC Processors • VisualDSP++ Assembler and Preprocessor Manual • VisualDSP++ Linker and Utilities Manual •...
Page 40 Product Information File Description Help system files and manuals in Help format .CHM Dinkum Abridged C++ library and FlexLM network license manager software doc- .HTM umentation. Viewing and printing the files requires a browser, such as .HTML .HTML Internet Explorer 4.0 (or higher). VisualDSP++ and processor manuals in Portable Documentation Format (PDF).
Page 41: Printed Manuals
To purchase VisualDSP++ manuals, call 1-603-883-2430. The manuals may be purchased only as a kit. If you do not have an account with Analog Devices, you are referred to Analog Devices distributors. For information on our distributors, log onto http://www.analog.com/salesdir/continent.asp...
Page 42 1-800-ANALOGD (1-800-262-5643); they also can be downloaded from the Web site. To have a data sheet faxed to you, call the Analog Devices Faxback System at 1-800-446-6212. Follow the prompts and a list of data sheet code numbers will be faxed to you. If the data sheet you want is not listed, check for it on the Web site.
Page 43: Conventions
Preface Conventions Text conventions used in this manual are identified and described as follows. Example Description Close command Titles in reference sections indicate the location of an item within the (File menu) VisualDSP++ environment’s menu system. For example, the Close command appears on the File menu.
Page 44 Conventions Additional conventions, which apply only to specific chapters, may appear throughout this document. xliv ADSP-21368 SHARC Processor Hardware Reference...
Page 45: Introduction
1 INTRODUCTION The ADSP-21367/8/9 and ADSP-2137x SHARC processors are high per- formance, 32-bit processors used for high quality audio, medical imaging, communications, military, test equipment, 3D graphics, speech recogni- tion, motor control, imaging, and other applications. By adding on-chip SRAM, integrated I/O peripherals, and an additional processing element for single-instruction, multiple-data (SIMD) support, this processor builds on the ADSP-21000 family DSP core to form a complete system-on-a-chip.
Page 46 Design Advantages and input/output (I/O) buses. In the core, every instruction can execute in a single cycle. The buses and instruction cache provide rapid, unimpeded data flow to the core to maintain the execution rate. Figure 1-1 shows a detailed block diagram of the processor core and the I/O processor (IOP).
Page 47 Introduction from memory, access an instruction (from the cache), and perform a DMA transfer. Figure 1-1 also shows the asychronous memory interface available on the ADSP-21368 processor. INSTRUCTION ON -C HIP M EM OR Y FLAGS 4-15 CACHE 3 2 X 4 8-BI T PW M 2 DAG S ADDR...
Page 48 Design Advantages Unconstrained Data Flow. The ADSP-21367/8/9 and ADSP-2137x pro- cessors have a Super Harvard Architecture combined with a ten-port data register file. In every cycle, the processor can write or read two operands to or from the register file, supply two operands to the ALU, supply two operands to the multiplier, and receive three results from the ALU and multiplier.
Page 49 Introduction Input Data Port (IDP). The IDP provides an additional input path to the processor core, configurable as eight channels of serial data or seven chan- nels of serial data and a single channel of up to 20-bit wide parallel data. Two Serial Peripheral Interfaces (SPI).
Page 50: Architectural Overview
Please visit www.analog.com/SHARC for complete information. 3 Analog Devices offers these packages in lead-free (Pb) versions. Architectural Overview The ADSP-21367/8/9 and ADSP-2137x processors form a complete sys- tem-on-a-chip, integrating a large, high speed SRAM and I/O peripherals supported by a dedicated I/O bus.
Page 51: Processor Core
Introduction Processor Core The processor core of the ADSP-21367/8/9 and ADSP-2137x processors contain two processing elements (each with three computation units and data register file), a program sequencer, two data address generators, a timer, and an instruction cache. All digital signal processing occurs in the processor core.
Page 52 Architectural Overview same serial clock and frame sync. Accordingly, each serial port has two DMA channels and serial data buffers associated with it to service the dual serial data pins. Programmable data direction provides greater flexibility for serial communications. Serial port data can automatically transfer to and from on-chip memory using DMA.
Page 53: Digital Audio Interface (Dai)
Introduction ROM-Based Security. For those processors with application code in the on-chip ROM, an optional ROM security feature is included. This feature provides hardware support for securing user software code by preventing unauthorized reading from the enabled code. The processor does not boot-load any external code, executing exclusively from internal ROM.
Page 54: Digital Peripheral Interface (Dpi)
Development Tools Digital Peripheral Interface (DPI) The digital peripheral interface (DPI) unit is a new addition to the SHARC processor peripherals. This set of audio peripherals consists of an interrupt controller, a two wire interface port (TWI), and a signal routing unit, three timers and a Universal Asynchronous Receiver/Transmitter (UART).
Page 55: Differences From Previous Processors
Introduction Differences From Previous Processors This section identifies differences between the ADSP-21367/8/9 and ADSP-2137x processors and previous SHARC processors: ADSP-21161, ADSP-21160, ADSP-21060, ADSP-21061, ADSP-21062, and ADSP-21065L. Like the ADSP-2116x family, the ADSP-2136x SHARC processor family is based on the original ADSP-2106x SHARC family. The ADSP-21367/8/9 and ADSP-2137x processors preserve much of the ADSP-2106x architecture and is code compatible to the ADSP-21160, while extending performance and functionality.
Page 56: Instruction Set Enhancements
Differences From Previous Processors Instruction Set Enhancements The ADSP-21367/8/9 and ADSP-2137x processors provide source code compatibility with the previous SHARC processor family members to the application assembly source code level. All instructions, control registers, and system resources available in the ADSP-2106x core programming model are also available in the ADSP-21367/8/9 and ADSP-2137x proces- sors.
Page 57 2 I/O PROCESSOR In applications that use extensive off-chip data I/O, programs may find it beneficial to use a processor resource other than the processor core to per- form data transfers. The ADSP-21367/8/9 and ADSP-2137x processors contain an I/O processor (IOP) that supports a variety of DMA (direct memory access) operations.
Page 58: General Procedure For Configuring Dma
General Procedure for Configuring DMA To further increase off-chip I/O, multiple DMAs can occur at the same time. The IOP accomplishes this by managing DMAs of processor mem- ory through the TWI, UART, SPI, input data port (IDP), and serial ports. Accesses to IOP spaces (from the processor core) should not use Type 1 (dual access) or LW instructions.
Page 59: Core Access To Iop Registers
I/O Processor • Serial peripheral interface ports (SPI) • Input data port (IDP) 4. Enable DMA • Set the applicable bits in the appropriate control registers For peripheral specific DMA information, see the following sections. • “External Port DMA” on page 2-35 •...
Page 60 Core Access to IOP Registers Table 2-1. I/O Processor Stall Conditions (Cont’d) Type Of Access Number of Core Cycles Aborted conditional I/O processor register read/write Conditional I/O processor register read/write 9/10 1 Applies to memory-mapped registers from Table 2-2. 2 Applies to all other memory-mapped registers not in Table 2-2.
Page 61 I/O Processor Table 2-2. Memory-Mapped Emulation/Breakpoint Registers (Cont’d) Register Description Address DMA1S/E Data memory breakpoint address number 0x300B2/ 1 start/end 0x300B3 DMA2S/E Data memory breakpoint address number 0x300B3/ 2 start/end 0x300B4 PMDAS/E Program memory breakpoint address 0x300B8/ start/end 0x300B9 In addition to the above, the following situations incur additional stall cycles.
Page 62: Configuring Iop/Core Interaction
Configuring IOP/Core Interaction In order to resolve this issue, use one of the following methods. 1. Read an IOP register from the same peripheral block before execut- ing the RTI. This read forces the write to occur first. dm(TXSPI) = R0; /* Write to TXSPI FIFO */ R0 = dm(SPICTL);...
Page 63 I/O Processor The processors also have programmable interrupts using the peripheral interrupt priority control registers, For more PICRx information, see “Peripheral Interrupt Priority Control Registers” on page A-164. Programs can check the appropriate status or configuration register to determine which channels are performing a DMA or chained DMA. All DMA channels can be active or inactive.
Page 64 Configuring IOP/Core Interaction During interrupt-driven DMA, programs use the interrupt mask bits in , and reg- IMASK LIRPTL DAI_IRPTL_PRI DAI_IRPTL_RE DAI_IRPTL_FE isters to selectively mask DMA channel interrupts that the I/O processor latches into the , and registers. IRPTL LIRPTL DAI_IRPTL_H DAI_IRPTL_L The I/O processor only generates a DMA complete interrupt when...
Page 65 I/O Processor Table 2-3. Default DMA Interrupt Vector Locations Associated Register(s) Bits Vector Interrupt Data Buffer Address Name Channel IRPTL/IMASK 0x38 SP1I RXSP1A, TXSP1A LIRPTL 0x44 SP0I RXSP0A, TXSP0A IRPTL/IMASK 0x3C SP3I RXSP3A, TXSP3A LIRPTL 0x48 SP2I RXSP2A, TXSP2A IRPTL/IMASK 0x40 SP5I RXSP5A, TXSP5A...
Page 66 Configuring IOP/Core Interaction Table 2-3. Default DMA Interrupt Vector Locations (Cont’d) Associated Register(s) Bits Vector Interrupt Data Buffer Address Name Channel IRPTL/IMASK 0x2C DAIHI IDP_FIF0 (high priority option) Channel 2 LIRPTL 0x5C DAILI (low priority option) IRPTL/IMASK 0x2C DAIHI IDP_FIF0 (high priority option) Channel 3 LIRPTL...
Page 67: Interrupt Latency In Interrupt-Driven Transfers
I/O Processor Table 2-3. Default DMA Interrupt Vector Locations (Cont’d) Associated Register(s) Bits Vector Interrupt Data Buffer Address Name Channel IRPTL/IMASK UART1TXI THR1 LIRPTL 0x50 EPDMA EPDF0 LIRPTL EPDMA EPTF0 LIRPTL 0x50 EPDMA EPDF1 IRPTL/IMASK MTMI MTM Write FIFO For more information, see the program sequencer “Interrupts and Sequencing”...
Page 68: Polling/Status-Driven I/O
Configuring IOP/Core Interaction 2. Add sufficient instructions after a write. In the worst case pro- grams need to add ten instructions after a write as shown in the example code below. isr_code: R0 = 0x0; dm(SPICTL) = R0; /* disable SPI */ nop;...
Page 69: Dma Controller Operation
I/O Processor • Bit definitions for the register are illustrated in “SPI Port SPIDMAC Status (SPISTAT, SPISTATB) Registers” on page A-56. • Bit definitions for the register are illustrated in “SPORT SPMCTLx Multichannel Control Registers (SPMCTLx)” on page A-40. • Bit definitions for the register are illustrated in DAI_STAT Figure A-41 on page...
Page 70: Chaining Dma Processes
Configuring IOP/Core Interaction In general, a DMA sequence starts when one of the following occurs: • Chaining is disabled, and the DMA enable bit transitions from low to high. • Chaining is enabled, DMA is enabled, and the chain pointer regis- ter address field is written with a nonzero value.
Page 71 I/O Processor parameters stored in the processor’s internal memory. These are the registers for the SPORTs, the register for the external port, CPSPxy CPEP registers for the UART, and the register for the SPI. RXCP_UACx CPSPI Each new set of parameters is stored in a four-word, user-initialized buffer in internal memory known as a transfer control block (TCB).
Page 72: Transfer Control Block Chain Loading (Tcb)
Configuring IOP/Core Interaction processor’s internal memory before it is used by the I/O processor. On the ADSP-21367/8/9 and ADSP-2137x processors, this offset value is 0x0008 0000. Bit 19 of the chain pointer register is the program-controlled interrupts ) bit. This bit controls whether an interrupt is latched after every DMA in the chain (when set), or whether the interrupt is latched after the entire DMA sequence completes (if cleared).
Page 73 I/O Processor 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 EIPP...
Page 74: Setting Up Dma Channel Allocation And Priorities
Configuring IOP/Core Interaction Table 2-4. TCB Chain Loading Sequence Address External Port Serial Ports SPI Port CPSPx + 0x0008 0000 Table 2-9, Table 2-10, IISPx IISPI Table 2-11 CPSPx – 1 + 0x0008 0000 IMSPx IMSPI CPSPx – 2 + 0x0008 0000 CSPx CSPI CPSPx –...
Page 75: Managing Dma Channel Priority
I/O Processor transfers. Table 2-5 shows the DMA channel allocation and parameter register assignments for the ADSP-21367/8/9 and ADSP-2137x processors. DMA channels vary by processor model. For a breakdown of DMA channels for a particular model, see the processor specific data sheet.
Page 76: Dma Bus Arbitration
Configuring IOP/Core Interaction If a DMA channel is disabled ( , or EPDEN SPIDEN SDEN IDP_DMA_EN bits =0), the I/O processor does not issue internal DMA grants to that channel (whether or not the channel has data to transfer). The default DMA channel priority is fixed prioritization by DMA channel group (serial ports, TWI, UART, IDP, or SPI port).
Page 77 I/O Processor IOP channel arbitration can be set to use either a fixed or rotating algo- rithm by setting or clearing bit 7 ( ) in the register: DCPR SYSCTL • fixed cleared (0) SYSCTL[7] • rotating set (1) SYSCTL[7] In the fixed priority scheme, the lower indexed peripheral has the highest priority.
Page 78 Configuring IOP/Core Interaction Table 2-5. DMA Channel Allocation and Parameter Register Assignments (Cont’d) Data Buffer Group IOP Address of Description Channel Data Buffers Number RXSP0A, TXSP0A 0xC61, 0xC60 Serial Port 0A Data RXSP0B, TXSP0B 0xC63, 0xC62 Serial Port 0B Data RXSP3A, TXSP3A 0x465, 0x464 Serial Port 3A Data...
Page 79 I/O Processor Table 2-5. DMA Channel Allocation and Parameter Register Assignments (Cont’d) Data Buffer Group IOP Address of Description Channel Data Buffers Number IDP_FIF0 0x24D0 DAI IDP Channel 6 IDP_FIF0 0x24D0 DAI IDP Channel 7 RXSPI, TXSPI 0x1004, 0x1003 SPI Data RXSPIB, TXSPIB 0x2804, 0x2803 SPI Data...
Page 80: Setting Up Dma Parameter Registers
Setting Up DMA Parameter Registers Setting Up DMA Parameter Registers Once you have determined and configured the DMA options, you can configure the DMA parameter registers. The parameter registers control the source and destination of the data, the size of the data buffer, and the step size used.
Page 81: Data Buffer Registers
I/O Processor D M D , P M D IO A B U S IO D B U S B U S E S (T O C O R E ) M U X M U X S P O R T S S P O R T T X S P 5 A -0 A , IIS P 7 A -0 A ,...
Page 82: Port, Buffer, And Dma Control Registers
Setting Up DMA Parameter Registers • Serial port transmit buffers ( ). These transmit buffers for the TXSPx serial ports have two-position FIFOs for transmitting data when connected to another serial device. • SPI receive buffers ( ). These receive buffers for the RXSPI RXSPIB SPI ports have a single-position buffer for receiving data when con-...
Page 83 I/O Processor • Universal asynchronous receiver/transmitter registers ). These control registers configure and RXCTL_UACx TXCTL_UACx enable the UART receiver and transmitter DMA, (chaining and non chaining). • Memory-to-memory DMA control register ( ). This control MTMCTL register contains the MTM DMA read and write channel enable and status bits.
Page 84 Setting Up DMA Parameter Registers • External modify registers ( ). Modify registers provide the EMEPx increment by which the DMA controller post-modifies the corre- sponding external memory index register after the DMA read or write. • External count registers ( ).
Page 85: Addressing
I/O Processor Table 2-6. DMA Parameter Registers Register Function Width Description Internal Index Register 19 bits Address of buffer in internal memory IMxy Internal Modify Register 16 bits Stride for internal buffer Internal Count Register 16 bits Length of internal buffer CPxy Chain Pointer Register 20 bits...
Page 86 Setting Up DMA Parameter Registers All addresses in the index registers are offset by a value that matches the processor’s first internal normal word addressed RAM location (before the I/O processor uses the addresses). For the ADSP-21367/8/9 and ADSP-2137x processors, this offset value is 0x0008 0000. DMA ADDRESS GENERATOR (INTERNAL ADDRESSES) LOCAL BUS INTERNAL...
Page 87 I/O Processor The following rules for data transfers must be followed. • DMA addresses must always be normal word (32-bit) memory. • Internal memory data transfer sizes are 32 bits, while external data transfer sizes may be 32, 16, or 8 bits. •...
Page 88 Setting Up DMA Parameter Registers In the serial port pair SP0/1, SP1 has a higher priority. For multichannel pairs, the odd numbered channels have a higher priority (for example SP3, SP5). Table 2-7. DMA Channel Registers: Controls, Parameters, and Buffers Control Registers Parameter Registers Buffer Registers Description...
Page 89 I/O Processor Table 2-7. DMA Channel Registers: Controls, Parameters, and Buffers (Cont’d) Control Registers Parameter Registers Buffer Registers Description Channel Number SPCTL7 IISP7A, IM7P5A, CSP7A, RXSP7A, Serial Port CPSP7A TXSP7A 7A Data SPCTL7 IISP7B, IMSP7B, CSP7B, RXSP7B, Serial Port CPSP7B TXSP7B 7B Data SPCTL6...
Page 90 Setting Up DMA Parameter Registers Table 2-7. DMA Channel Registers: Controls, Parameters, and Buffers (Cont’d) Control Registers Parameter Registers Buffer Registers Description Channel Number IDP_CTL IDP_DMA_I7, IDP_FIFO DAI IDP IDP_DMA_M7, Channel 7 IDP_DMA_C7 SPICTL IISPI, IMSPI, CSPI, CPSPI RXSPI, TXSPI SPI Data SPICTLB IISPIB, IMSPIB, CSPIB,...
Page 91: External Port Dma
I/O Processor Table 2-7. DMA Channel Registers: Controls, Parameters, and Buffers (Cont’d) Control Registers Parameter Registers Buffer Registers Description Channel Number TXCTL_UAC0 TXI_UAC0, TXM_UAC0, THR0 UART0 Tx TXC_UAC0, TXCP_UAC0, TXSTAT_UAC0 TXCTL_UAC1 TXI_UAC1, TXM_UAC1, THR1 UART1 Tx TXC_UAC1, TXCP_UAC1, TXSTAT_UAC1 All of the I/O processor’s registers are memory-mapped, ranging from address 0x0000 0000 to 0x0003 FFFF.
Page 92: Setting Up And Starting Chained Dma
External Port DMA Table 2-8. External Port Registers Register Description Address EPCTL External Port Global Control Register 0x1801 DMAC1–0 External Port DMA Control Register 0x180B, 0x180C IIEP1–0 Internal Index Register 0x1823, 0x1833 IMEP1–0 Internal Modifier Register 0x1824, 0x1834 ICEP1–0 Internal Count Register 0x1825, 0x1835 EIEP1–0 External Index Register...
Page 93 I/O Processor 3. If circular buffering is needed, then program additional writes to registers. Note that for normal chained DMA, ELEP EBEP registers are not part of the TCB. So if circular ELEP EBEP buffering is used with the normal chained DMA, all the DMA blocks will have same values.l ELEP...
Page 94: Delay Line Dma
External Port DMA Table 2-10. Chain Pointer Loading Sequence (Circular Buffering Enabled) Address Register Value ELEP[18:0] IIEP CPEP[18:0] – 0x1 IMEP CPEP[18:0] – 0x2 ICEP CPEP[18:0] – 0x3 EIEP CPEP[18:0] – 0x4 EMEP CPEP[18:0] – 0x5 CPEP EPCP[18:0] – 0x5 EPEB EPCP[18:0] –...
Page 95 I/O Processor as the external index and is incremented by the external modifier register ( ) after each write. These writes are circular buffered if EMEP circular buffering is enabled. 2. In chained DMA, when the writes are complete, ( = zero) the ICEP register, which serves as the write pointer of the delay line, is...
Page 96: Serial Port Dma
Serial Port DMA 4. Once the read count completes, the delay line DMA access is com- plete and the DMA complete interrupt is generated. Note that if chaining is enabled, the interrupt is generated based on the setting. For more information on the bit, see “Interrupt-Driven I/O”...
Page 97: Inserting A Tcb In An Active Chain
I/O Processor 2. Write to the appropriate DMA control register, setting the DMA enable bit to one and the chaining enable bit to one. 3. Write the address containing the index register value of the first TCB to the chain pointer register, which starts the chain. The I/O processor responds by autoinitializing the first DMA parameter registers with the values from the first TCB, and then starts the first data transfer.
Page 98: Serial Peripheral Interface Dma
Serial Peripheral Interface DMA Chain insertion mode operates the same as non-chained DMA mode. When the current DMA transfer ends, an interrupt request occurs and no TCBs are loaded. This interrupt request is independent of the state. Chain insertion should not be set up as an initial mode of operation. This mode should only be used to insert one or more TCBs into an active DMA chaining sequence.
Page 99 I/O Processor Writing an address to the register does not begin a chained CPSPI DMA sequence unless the , and registers are ini- IISPI IMSPI CSPI tialized, SPI DMA is enabled, the SPI port is enabled, and SPI DMA chaining is enabled. The sequence for setting up and starting a chained DMA is outlined in the following steps and can also be seen in Listing 6-3 on page...
Page 100: Uart Dma
UART DMA UART DMA In the UART, separate receive and transmit DMA channels move data between the UART and memory. The software does not have to move data, it just has to set up the appropriate transfers either through the descriptor mechanism or through auto buffer mode.
Page 101 I/O Processor DMA through the UART is started by setting up values in the DMA parameter registers and then writing to the transmit and receive control registers, enabling the module using the bits (in the UARTEN UARTxTXCTL registers) and enabling DMA using the bits.
Page 102 UART DMA When performing DMA using the UART module, receive interrupts are generated when: • The receive word block is complete/the DMA is complete. • A receive overrun error is detected. • A receive parity error is detected. • A receive framing error is detected. •...
Page 103: Notes On Using Dma With The Uart
I/O Processor Notes On Using DMA With the UART The following should be noted when performing DMA in conjunction with the UART module. 1. DMA can be interrupted by resetting the bit, but none of the other control settings should be changed. If the UART is enabled again, then interrupted DMA can be resumed by resetting the bit.
Page 104: Memory-To-Memory Dma
Memory-to-Memory DMA Memory-to-Memory DMA Memory-to-memory (MTM) DMA allows programs to transfer blocks of 64-bit data from one internal memory location to another. This transfer method uses two DMA channels, one for reading data and one for writing data. This data transfer can be set up using the following procedure. 1.
Page 105: Programming Example
I/O Processor that channel. If the parameters configure the channel to receive, the I/O processor transfers data words received at the buffer to the destination in internal memory. If the parameters configure the channel to transmit, the I/O processor transfers a word automatically from the source memory to the channel’s buffer register.
Page 106 Programming Example .align 2; .var source[100]; /* Main code section */ .global _main; .section/pm seg_pmco; _main: r0=0x11111111; i0=source; /* Fill the source buffer */ lcntr=LENGTH(source), do fill until lce; dm(i0,1)=r0; fill: r0=rot r0 by 1; /* Set the interrupt mask for MTMDMA */ bit set imask MTMI;...
Page 107 I/O Processor /* Read and write sequentially with a step of 1 */ r0=1; dm(IMMTMW)=r0; dm(IMMTMR)=r0; /* Read the number of words in source */ r0=@source; dm(CMTMR)=r0; /* Write the number of words in destination */ r0=@dest; dm(CMTMW)=r0; /* Enable MTMDMA */ r0=MTMEN;...
Page 108 Programming Example 2-52 ADSP-21368 SHARC Processor Hardware Reference...
Page 109: External Port
3 EXTERNAL PORT The external ports of the ADSP-21367/8/9 and ADSP-2137x processors are comprised of the following modules. • An “Asynchronous Memory Interface” on page 3-20 which com- municates with SRAM, FLASH, and other devices that meet the standard asynchronous SRAM access protocol. The AMI supports 16M words of external memory in bank1, bank2, and bank3 and 14M words of external memory in bank0.
Page 110: External Memory Interface
External Memory Interface External Memory Interface The external memory interface provides a glueless interface to external memories. The processor’s I/O processor (IOP) supports synchronous DRAMs (SDRAMs), SRAMs, FIFOs, flash memory, and ASIC/FPGA devices. The external memory interface and the SDRAM memory that interfaces to the external port is clocked by the SDRAM clock ( SDCLK The ratio of core clock (...
Page 111: External Memory Interface On The Adsp-2137X Processors
External Port External memory address space is supported in normal word addressing mode only. Single-instruction, multiple-data (SIMD), extended-precision, short word and long word addressing modes are not supported. Program execution from external memory on the ADSP-2136x processors is also not supported. External Memory Interface on the ADSP-2137x Processors The ADSP-2137x SHARC processors support direct execution of instruc-...
Page 112: Location Of Interrupt Vector Table (Ivt)
External Memory Interface wide external port. When executing from external asynchronous memory, instruction throughput depends on the settings of asynchronous memory such as the number of wait states, the ratio of core to peripheral clock and other settings. For details, please refer to the external port global control register ( ), asynchronous memory interface control register EPCTL...
Page 113: Instruction Cache
External Port When an unmasked interrupt occurs and is serviced, program execution automatically jumps to the location of the corresponding interrupt vector table in internal memory. Upon returning from the interrupt, the sequencer resumes execution from external memory because locating the IVT in external memory is not supported.
Page 114 External Memory Interface Instruction Cache 32-bit x 48-bit *The external bus is 32 bits on the ADSP-21371 and 16 bits on the ADSP-21375. PROGRAM Sequencer 16/32* EXTERNAL PORT PM Address Bus Data SDRAM Controller DM Address Bus PM Data Bus Control Asynchronous DM Data Bus...
Page 115 External Port In other words, the 32-entry 2-way set-associative cache in the SHARC has been modified to act as an instruction cache when the program sequencer executes instructions from external memory, while continuing to work as the traditional conflict cache when the sequencer executes instructions located in internal memory.
Page 116 External Memory Interface The following example shows the innermost loop of a FIR filter. lcntr=FILTER_TAPS-1, do macloop until lce; macloop: f12=f0*f4, f8=f8+f12, f0=dm(i0,m1), f4=pm(i9,m9); In this example, if the code is stored and executed from external memory, the first time through this loop the program sequencer places the appro- priate 24-bit address on the external address bus, and fetches the instruction in line 2 from external memory.
Page 117: Instruction Storage And Packing
External Port Instruction Storage and Packing The ADSP-2137x processors incorporate a 32-bit SDRAM controller. However, the SDRAM controller supports SDRAMs with data bus widths of 16 as well as 32 bits. The packing logic in the SDRAM controller packs the data from SDRAM into 48-bit instructions. Any address produced by the sequencer which falls in external memory is first translated into the physical address in external memory based on the actual data bus width of external memory as shown in...
Page 118 External Memory Interface “Physical External ADSP-213xx Memory Address” on Bank 0 External address bus “Logical Port Address” Address Address Sequencer Packing Translator Data Unit 16/32 bit* “Instruction Data” on data bus *32-bit on the ADSP-21371 and 16-bit on the ADSP-21375. Figure 3-3.
Page 119 External Port Table 3-2. External Address Space for SDRAM Memory Accesses Bank Size in words Address Range Bank 0 0x0020 0000 – 0x03FF FFFF Bank 1 0x0400 0000 – 0x07FF FFFF Bank 2 0x0800 0000 – 0x0BFF FFFF Bank 3 0x0C00 0000 –...
Page 120 External Memory Interface words and packs them to form the 48-bit instruction to be executed. The address is automatically incremented, and program execution continues with placing the next address on the external address bus, and so on. Table 3-3, the logical to physical translation is a multiplication by a factor of 3/2 and N = 0x8AAAA9.
Page 121 External Port Table 3-4. Logical Versus Physical Address Mapping, 16-Bit Asynchronous Memory Logical Address Dispatched Physical Address Observed Data by Program Sequencer on the External Address Bus 0x200000 0x600000 Instr0[15:0] 0x600001 Instr0[31:16] 0x600002 Instr0[47:32] 0x200001 0x600003 Instr1[15:0] 0x600004 Instr1[31:16] 0x600005 Instr1[47:32] 0x200002 0x600006...
Page 122 External Memory Interface Table 3-5. Logical Versus Physical Address Mapping, 32-Bit SDRAM Memory Logical Address Dispatched Physical Address Observed Data by Program Sequencer on the External Address Bus 0x200000 0x300000 Instr0[31:0] 0x300001 Instr1[15:0] Instr0[47:32] 0x200001 0x300001 Instr1[47:16] 0x300002 Instr2[31:0] 0x200002 0x300002 Instr3[15:0] Instr2[47:32]...
Page 123: Register Configurations For External Memory Execution
External Port Table 3-6. Logical Versus Physical Address Mapping, 16-Bit SDRAM Memory (Cont’d) Logical Address Dispatched Physical Address Observed Data by Program Sequencer on the External Address Bus 0x200001 0x600003 Instr1[15:0] 0x600004 Instr1[31:16] 0x600005 Instr1[47:32] 0x200002 0x600006 Instr2[15:0] 0x600007 Instr2[31:16] 0x600008 Instr2[47:32] 0xFFFFFF...
Page 124: Emi Registers And Signals
External Memory Interface For the ADSP-21371 processor, the register needs to be SDCTL explicitly programmed for 16-bit wide external memory by setting bit 16 (X16DE) of this register. EMI Registers and Signals The external port global control register is used to set the priority between core and DMA memory accesses and to determine whether SDRAM or asynchronous memory is used on each bank.
Page 125 External Port Table 3-7. External Port Control Register Bit Descriptions (Cont’d) Name Description Default B3SD Bank 3 SDRAM. 1 = Bank 3 (MS3) connected to SDRAM 0 = Bank 3 (MS3) connected to asynchronous memory 5–4 EPBR External Port Bus Priority. 11 = Rotating priority 10 = Core has high priority 01 = DMA has high priority...
Page 126: External Port Arbitration Logic
External Memory Interface External Port Arbitration Logic The external port arbitration logic controls the arbitration between the two DMA channels and processor core. The following control the arbitra- tion logic. • The register can be programmed to use the various features EPCTL of arbitration between different channels.
Page 127: External Memory Interface Pins
External Port External Memory Interface Pins The pins used by the external memory interface are described in Table 3-8. Table 3-8. External Memory Pin Descriptions Pin Name Description for AMI Description for SDRAM DATA31–0 Data bus Data bus ADDR23–0 Address bus Address bus, includes bank selects ADDR [23:0] SDCLK...
Page 128: Asynchronous Memory Interface
Asynchronous Memory Interface Asynchronous Memory Interface Both the processor core and the I/O processor have access to external memory using the AMI. Table 3-9 describes the processor pins used for interfacing to external memory. The processor’s memory control signals also permit direct connection to fast static RAM devices.
Page 129: Ami Timing Control
External Port Table 3-9. Asynchronous Memory Interface Signals (Cont’d) Type Description MS3–0 Memory Select Lines [FLAG2-3 are muxed and used as MS2 and MS3]. Memory select lines 0–1 are asserted (low) as chip selects for the corresponding banks of external memory. The MS3-0 lines are decoded memory address lines that change at the same time as the other address lines.
Page 130: Bus Idle Cycles
AMI Timing Control enabled, the minimum value is = 2 (a wait state value of 0 corresponds to 32 wait cycles). The processor samples the signal after the pro- grammed wait state count expires—it is imperative that the value is initialized when the acknowledge enable bit ( ) is set.
Page 131: Bus Hold Cycles
External Port READ IDLE WRITE SDCLK ADDRESS 23 DATA 31 Figure 3-4. Idle Cycle Example, Wait State = 2 Bus Hold Cycles The processor is able to insert bus hold and read hold cycles by setting bits in the AMI control register ( ).
Page 132: Setting Ami Modes
Setting AMI Modes The address, data (if a write), and bank select (if in banked external mem- ory) remain unchanged and are driven for one or more cycles after the read or write strobes are deasserted. Figure 3-5 demonstrates a hold time cycle appended to an asynchronous write access ( = 011).
Page 133: External Memory Reads
External Port There is a 3:1 bus conflict resolution ratio at the external port interface (three internal buses to one external bus) in addition to the 2:1 or greater clock ratio between the processor’s internal clock and the external SDRAM clock ( ).
Page 134: External Memory Writes
Setting AMI Modes For packed data mode where = 0 and = 1, the packing order PKDIS MSWF = 8 is: first byte received is bits 31–24, the second byte is bits 23–15, and so on. If the bit is set (=1), then the 8- or 16-bit data (based on the bus PKDIS width) is zero appended to 32 bits.
Page 135: Data Packing
External Port controller or through direct core writes. Writes to the AMI set a status bit , bit 2 in the register) and initiate the external write AMITXS AMISTAT access. Once a full word is transferred out of the AMI, the bit is cleared AMITXS and new writes are allowed.
Page 136: Read/Write Throughput
Setting AMI Modes Read/Write Throughput For a wait state of 2 (which is the smallest wait state), the throughput is shown in Table 3-11. Table 3-11. Read/Write Throughput Bus Width Operation Throughput in SDCLK Cycles 32-bit Write One 32-bit word per 3 SDCLK cycles 32-bit Read One 32-bit word per 3 SDCLK cycles...
Page 137 External Port • For an external bus width of 32 bits, or when packing is disabled with other bus widths ( = 1 and = 16 bits or = 1 and PKDIS PKDIS = 8 bits), then the external physical memory is the same as the lower 24 bits of bits 23–0 in the address being supplied to the external port by the core or DMA controller.
Page 138: External Port Dma
SDRAM Controller External Port DMA The AMI shares the two DMA channels of the external port with the SDRAM controller. Either of these DMA channels can be directed to the external asynchronous memories. For information on external port DMA, Chapter 2, I/O Processor.
Page 139: Definition Of Terms
External Port • SDC uses open page policy—any open page is closed only if a new access in another page of the same bank occurs • Supports multibank operation within the SDRAM (ADSP-2137x only) • Uses a programmable refresh counter to coordinate between vary- ing clock frequencies and the SDRAM’s required refresh rate •...
Page 140 SDRAM Controller Burst length The burst length determines the number of words that the SDRAM device stores or delivers after detecting a single write or read command, respectively. The SDC supports burst length = 1 mode only. Burst stop command Use of this command is one of several ways to terminate or interrupt a burst read or write operation.
Page 141 External Port CBR (CAS before RAS) Refresh or auto-refresh. When the SDC refresh counter times out, the SDC precharges all four banks of SDRAM and then issues an auto-refresh command to them. This causes the SDRAMs to generate an internal CBR refresh cycle.
Page 142 SDRAM Controller The initial read or write triggers the SDRAM power-up sequence, which programs the SDRAM’s mode register with the CAS latency from the register. This initial read or write to SDRAM takes many cycles to SDCTL complete. Note that for most applications the SDRAM power-up sequence and a write to the mode register is performed only once.
Page 143 External Port tRAS Required delay between issuing a bank activate command and a precharge command, and between issuing the self-refresh command and the exit from self-refresh mode. The bits (7–4) in the register can be SDTRAS SDCTL set to 1 to 15 clock cycles. Required delay between issuing a precharge command and issuing: •...
Page 144: Timing External Memory Accesses
SDRAM Controller Required delay between issuing successive bank activate commands to the same SDRAM internal bank. This delay is not directly programmable. The t delay is satisfied by programming the fields to SDTRAS SDTRP ≥ t ensure that t tRFC Required delay between issuing an auto-refresh command and a bank acti- vate command, and between issuing successive auto-refresh commands.
Page 145 External Port The SDRAM CAS latency, ( bits), precharge ( bits), SDCL SDTRAS SDTRP RAS to CAS delay ( bits), and write before precharge timing ( SDTRCD SDTWR bits) should be programmed based on the SDRAM clock frequency and the timing specifications of the SDRAM used. All timing parameters are written with valid values based on the clock frequency and the tim- SDCLK...
Page 146 SDRAM Controller PLLD Bit Setting Clock Ratio CCLK divider of 1 CCLK divider of 2 CCLK divider of 4 CCLK divider of 8 SDCKR Bit Setting Clock Ratio SDCLK divider of 2 SDCLK divider of 2.5 SDCLK divider of 3 SDCLK divider of 3.5 SDCLK divider of 4 3.
Page 147: Parallel Connection Of Sdrams
External Port For more information on SDRAM clocking and programming the PLL, “Clock Derivation” on page 14-13, “Power Management Control Reg- ister” on page 14-14, and “Power Management Control Register (PMCTL)” on page A-170. Parallel Connection of SDRAMs To specify a SDRAM system, multiple possibilities are given based on the different memory sizes.
Page 148 SDRAM Controller SDRAM CAS latency parameter setting. bits 1–0. The column SDCL address strobe (CAS) latency is the delay in clock cycles between when the SDRAM detects the read command and when it provides the data at its output pins. Settings are: 10 = 2 cycles, 11 = 3 cycles. Generally, the frequency of operation determines the value of the CAS latency.
Page 149 External Port The t parameter allows the ADSP-21367/8/9 and ADSP-2137x pro- cessors to adapt to the timing requirements of the system’s SDRAM devices. Any value between 1 and 15 cycles can be selected as shown SDCLK Table 3-14. Table 3-14. Bank Activate Command Delay Bit Settings Bit Setting Clock Cycles Bit Setting...
Page 150 SDRAM Controller Table 3-15. Precharge Delay Bit Settings Bit Setting Clock Cycles Bit Setting Clock Cycles Reserved SDTRP4 = 100 SDTRP1 = 001 SDTRP5 = 101 SDTRP2 = 010 SDTRP6 = 110 SDTRP3 = 011 SDTRP7 = 111 SDRAM power-up mode. bit 11.
Page 151 External Port SDRAM power-up sequence start. bit 14. The bit specifies SDPSS SDPM the power-up mode and the bit starts an SDRAM power-up (initial- SDPSS ization) sequence. When this bit is set (=1), the SDRAM power-up sequence starts on the next SDRAM access. When cleared, this bit has no effect.
Page 152 SDRAM Controller • If cleared (=0), a 32-bit SDRAM should be used; should be connected to the SDRAM data pins; DATA[31–0] should be connected SDRAM address pins 14–0. ADDR[15:1] more information, see “SDRAM Address Mapping” on page 3-51. Note that pins are also used.
Page 153 External Port Force auto-refresh. bit 20. When set (=1), forces auto-refresh. Force AR When cleared (=0), has no effect. Note that when bit is set, setting SDORF this bit causes to have no effect. Force AR Force precharge. bit 21. When set (=1), forces precharge. When Force PC cleared (=0), has no effect.
Page 154 SDRAM Controller ADSP-21367 SDRAM #1 4M X 4 X 4 SDWE SDCKE A[15:11] A[14:0] A[9:1] SDA10 SDCLK DATA [3:0] DATA [3:0] DATA[31-0] DATA [7:4] DATA [3:0] SDRAM #2 4M X 4 X 4 DATA [11:8] DATA [3:0] SDRAM #3 4M X 4 X 4 DATA [15:12] DATA [3:0] SDRAM #4...
Page 155 External Port ADDR [15] CTRL [6] SDRAM BANK 1 ADDR & CTRL SDRAM BANK 2 ADDR & CTRL REG ISTERED ADSP-21367 BUFFERS SDRAM #5 4 X 4 X 4 O 1A SDWE SDCKE AA[15:1] A[15:11] A[14:0] OXA[14:0] AB[15:1] A[9:1] OXB[14:0] IX[14:0] SDA10 DATA [19:16]...
Page 156 SDRAM Controller For more information, see “Timing External Memory Accesses” on page 3-36. Any value between 1 and 7 cycles may be selected as SDCLK shown in Table 3-18. Table 3-18. SDRAM t Bit Settings SDTRCD Bit SDRAM Parameter SDTWR Bit SDRAM Parameter Setting Setting...
Page 157: Sdram Control Status Register (Sdstat)
External Port Table 3-19. SDRAM Row Address Width Bit Settings SDRAW Bit Setting Row Address Width SDRAW Bit Setting Row Address Width SDRAW8 = 000 8 bits (256) SDRAW12 = 100 12 bits (4K) SDRAW9 = 001 9 bits (512) SDRAW13 = 101 13 bits (8K) SDRAW10 = 010...
Page 158 SDRAM Controller To calculate the value to write to the register, use the following SDRRC equation. × ⎛ ⎞ SDCLK ≤ ---------------------------------- - – RDIV ⎝ ⎠ Where: frequency (SDRAM clock frequency) SDCLK SDCLK = SDRAM refresh period NRA = Number of row addresses in SDRAM (refresh cycles to refresh whole SDRAM) = Active to precharge time ( bits in the SDRAM mem-...
Page 159: Sdram Initialization
External Port 3 – ⎛ × × × ⎞ ⎜ ---------------------------------------------------------------- - ⎟ – RDIV 1030 ⎝ 8192 ⎠ This means is 0x406 (hex) and the SDRAM refresh rate control reg- RDIV ister is written with 0x406. value must be programmed to a nonzero value if the RDIV SDRAM controller is enabled.
Page 160 SDRAM Controller On the ADSP-21367/8/9 and ADSP-2137x processors, bank 0 starts at address 0x20 0000 in external memory and is followed in order by banks 1, 2, and 3. When the processor generates an address located within one of the four banks, it asserts the corresponding memory select line, MS3-0 Bank Unused...
Page 161 External Port lines are decoded memory address lines that change at the same time as the other address lines. When no external memory access is occurring, the lines are inactive. MS3-0 The width of the bank address is only two bits and is shown in Table 3-21.
Page 162 SDRAM Controller Table 3-22. 32-Bit Column, Row, and Bank Address Mapping (1K Words) (Cont’d) Column Address Row Address Bank Address Pins of SDRAM SDA10 IA[20] A[10] A[10] IA[9] IA[19] A[9] A[9] IA[8] IA[18] A[8] A[8] IA[7] IA[17] A[7] A[7] IA[6] IA[16] A[6] A[6]...
Page 163 External Port Table 3-23. 32-Bit Column, Row and Bank Address Mapping (2K Words) (Cont’d) Column Address Row Address Bank Address Pins of SDRAM A[9] IA[8] IA[19] A[8] A[8] IA[7] IA[18] A[7] A[7] IA[6] IA[17] A[6] A[6] IA[5] IA[16] A[5] A[5] IA[4] IA[15] A[4]...
Page 164 SDRAM Controller Table 3-24. 16-Bit Row and Column Address Mapping (1K Words) Column Address Row Address Bank Address Pins of SDRAM A[18] IA[22] BA[1] A[17] IA[21] BA[0] A[13] A[12] A[12] A[11] IA[20] A[11] SDA10 IA[19] A[10] A[9] IA[8] IA[18] A[9] A[8] IA[7] IA[17]...
Page 165 External Port Table 3-25. 16-Bit Row and Column Address Mapping (2K Words) Column Address Row Address Bank Address Pins of SDRAM A[18] IA[23] BA[1] A[17] IA[22] BA[0] A[13] A[12] A[12] A[11] IA[9] IA[21] A[11] SDA10 IA[20] A[10] A[9] IA[8] IA[19] A[9] A[8] IA[7]...
Page 166: Sdram Controller Address Mapping
SDRAM Controller SDRAM Controller Address Mapping To access SDRAM, the SDC multiplexes the internal 32-bit, non-multi- plexed address into a row and column address. The row and column address mappings for 32-bit and 16-bit addresses are shown in Table 3-25. The row and column addresses are muxed to pins of the processor.
Page 167 External Port The internal 32-bit non-multiplexed address is multiplexed into: • SDRAM column address • SDRAM row address • Internal SDRAM bank address The lowest bits are mapped into the column address, next bits are mapped into the row address, and the final two bits are mapped into the internal bank address.
Page 168: Single Bank Operation
SDRAM Controller Single Bank Operation The SDC keeps only one page open at a time, however, driving four exter- nal memory selects populated with SDRAM, the effective page size is increased up to four pages. Multibank Operation (ADSP-2137x Processors) Since an SDRAM contains four independent internal banks (A–D), the SDC on the ADSP-2137x processors is capable of supporting multibank operation, thus taking advantage of the architecture.
Page 169: Data Mask (Dqm)
External Port Access to page x Access to page x Bank A Bank A Access to page y Access to page y Bank B Bank B Access to page x Bank C Bank C Access to page y Bank D Bank D Single bank operation Multibank operation...
Page 170 SDRAM Controller In order to set up the SDC and start the SDRAM power-up sequence for the SDRAMs, use the following procedure. Note that the registers must be programmed in order. 1. External port control ( ) register (assign external banks to EPCTL SDC) 2.
Page 171: Sdc Commands
External Port • Select and enable the start of the SDRAM power-up sequence SDPM SDPSS • Select the column/row address widths Once the bit in the register is set to 1, and a transfer occurs to SDPSS SDCTL enabled SDRAM address space, the SDC initiates the SDRAM power-up sequence.
Page 172: Load Mode Register
SDRAM Controller • Self-refresh entry—places the SDRAM in self-refresh mode, in which the SDRAM powers down and controls its refresh opera- tions internally. • Self-refresh exit—exits from self-refresh mode by expecting auto-refresh commands from SDC. • NOP/command inhibit—no operation used to insert wait states for activate and precharge cycles •...
Page 173: Single Bank Activation
External Port While executing the load mode register command, the unused address pins are set to zero. During the first cycle following load mode reg- SDCLK ister, the SDC issues only commands. Alternatively, programs can use the Force LMR command by setting bit 22 (=1) in the register.
Page 174: Multibank Activation (Adsp-2137X Processors)
SDRAM Controller However, if an access to another bank occurs, the SDC closes the current page open and issues another bank activate command before executing the read or write command to that bank. With this method, called single bank operation, Only one page can be open at a time. Multibank Activation (ADSP-2137x Processors) Unlike this command for the ADSP-21367/8/9 processors, if any other access to another bank occurs, the SDC leaves the current page open and...
Page 175: Read/Write
External Port Read/Write This command is executed if the next read/write access is in the present active page. During the read command, the SDRAM latches the column address. The delay between activate and read commands is determined by the t parameter.
Page 176 SDRAM Controller SDCLK SDA10 COMMAND AC T ADDR RO W BA[1:0] DATA t RCD t RP t RAS t RC Figure 3-11. Read Timing Diagram ADSP-21367/8/9 SD CLK S DA10 CO MMAND BS T CO L RO W ADDR BA[1:0] DATA t WR t RCD...
Page 177: Read/Write (Adsp-2137X Processors)
External Port SDCLK SDA10 COMMAND ADDR RO W SDA10 BA[1:0] DATA t RCD t RP t RAS t RC Figure 3-13. Read Timing Diagram (ADSP-2137x, Full Page Burst) Read/Write (ADSP-2137x Processors) If the optional full page burst is select in the register, the SDC posts SDCTL for every read and write an address on the bus.
Page 178: Auto-Refresh
SDRAM Controller Auto-Refresh The SDRAM internally increments the refresh address counter and causes a CAS before RAS (CBR) refresh to occur internally for that address when the auto-refresh command is given. The SDC generates an auto-refresh command after the SDC refresh counter times out. The value in the RDIV SDRAM refresh rate control register (...
Page 179: No Operation/Command Inhibit
External Port to exit self-refresh mode. Therefore, the latency from when a transfer is received by the SDC while in self-refresh mode, until the activate com- mand occurs for that transfer, is 2 × (t ) cycles System clock during self-refresh mode. Note that the is not dis- SDCLK abled by the SDC during self-refresh mode.
Page 180 SDRAM Controller commands with no effect, the command is given. When the SDC is not accessing any SDRAM external banks, the command inhibit com- mand is given. A summary of pin states during SDC commands appears in Table 3-26. Note that an X means do not care. Table 3-26.
Page 181: Changing System Clock During Runtime
External Port Changing System Clock During Runtime All timing specifications are normalized to the system clock. Since most of these are minimum specifications, (except t , which is a maximum spec- ification), a variation of the system clock violates a specific specification and causes a performance degradation for the other specifications.
Page 182: Sdram Timing
SDRAM Controller SDRAM Timing To support key timing requirements and power-up sequences for different SDRAM vendors, the SDC provides programmability for t and the power-up sequence mode. CAS latency is programmed in the register based on the frequency SDCTL of operation. (Please refer to the SDRAM vendor’s data sheet for more information.) For other parameters, the SDC assumes: •...
Page 183: Sdram Read Optimization
External Port Table 3-28. Optimal Data Throughput for 16-Bit Data Accesses (CAS Latency = 2) Access Operation Page Throughput per SDCLK (32-Bit Data) Sequential and Read Same 32 words per 69 cycles uninterrupted Sequential and uninter- Write Same 2 cycles rupted Non Sequential and Read...
Page 184 SDRAM Controller example, if = 1, then 32 locations in the boundary of the exter- SDMODIFY nal banks should not be used. These locations can be used without optimization enabled. If = 2 then 64 locations can not be used at SDMODIFY the boundaries of the external bank (if it is fully populated).
Page 185 External Port Listing 3-3. Nonsequential Reads With Read Optimization I0 = sdram_addr; M0 = 2; /* SET sdmodify to 2 */ Lcntr = 1024, do(PC,2) until lce; R0 = R0 + R1, R0 = dm (I0, M0); NOP; Without read optimization, 1024 reads use 6144 processor cycles if all of the reads are on the same page.
Page 186: External Memory Access Restrictions
SDRAM Controller The workaround is to break up this instruction into separate instructions and use the workaround similar to case #1. r0=dm(IOP); NOP; r8=pm(Ext_Mem); External Memory Access Restrictions The following restrictions should be noted when writing programs for the ADSP-21367/8/9 and ADSP-2137x processors. 1.
Page 187: Shared Memory Interface
External Port Shared Memory Interface The ADSP-21368 processor supports connections to a common shared external memory of other ADSP-21368 processors. These connections create shared external bus processor systems. This support includes: • Support for asynchronous memory and SDRAM • Distributed, on-chip arbitration for the shared external bus •...
Page 188 Shared Memory Interface ADSP-21368 #N ADDR CLKIN DATA RESET CONTROL ID2-0 ADDR DATA B OOT EPROM (OPTIONAL) A DSP-21368 #1 CLOCK CLKIN ADDR23-0 ADDR RESET RESET GLOBAL DATA31-0 DATA MEMORY PERIPHERALS (OPTIONAL) ID2-0 MS3-0 BR4-2 SDWE SDRAM SDCLK1-0 (O PTIONAL) SDCKE SDA10 DAT A...
Page 189 External Port Table 3-30. Shared Memory Pins Signal Type Definition BR4–1 I/O/S Shared Memory Bus Requests. Used to arbitrate for bus mastership. A processor only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all others. In a shared memory system with less than four processors, the unused BRx pins should be tied high;...
Page 190: Bus Arbitration Protocol
Shared Memory Interface Conditional instructions can be written that depend upon whether the processor is the current bus master in a shared memory system. The assembly language mnemonic for this condition code is , and its com- plement is (not bus master). The condition indicates whether Not BM the processor is the current bus master.
Page 191 External Port After conditions determine that a bus transition cycle is going to occur, every processor in the system evaluates the priority of the lines asserted within that cycle. For a description of bus arbitration priority, see “Bus Arbitration Priority (RPBA)” on page 3-86.
Page 192 Shared Memory Interface are driven high (inactive) before three-stating occurs. The MS3-0 signal must be sampled high by the new master before it starts a new bus operation. For more information, see Figure 3-16. During bus transition cycle delays, execution of external accesses are delayed.
Page 193 External Port CLKIN OPTIONAL HIGHEST PRIORITY REQUESTER BECOMES BUS MASTER VALID ADDR VALID VALID VALID MS, STROBES DRIVEN INACTIVE BEFORE THREE-STATE DATA VALID VALID BTC DOES NOT OCCUR IF NO OTHER BRS ASSERTED Figure 3-16. Bus Request and Read/Write Timing keep these signals from drifting near input receiver thresholds when all drivers are three-stated.
Page 194: Bus Arbitration Priority (Rpba)
Shared Memory Interface Bus Arbitration Priority (RPBA) To resolve competing bus requests, there are two available priority schemes—fixed and rotating. The pin selects the scheme. When RPBA RPBA is high, rotating priority bus arbitration is selected, and when is low, RPBA fixed priority is selected.
Page 195: Bus Mastership Time-Out
External Port Table 3-31. Rotating Priority Arbitration Example (Cont’d) Hardwired Processor IDs and Priority Cycle Number 3-BR 2-BR 1-BR 1 The following symbols appear in these cells: 1-3 = assigned priority, M = bus mastership (in that cycle), BR = requesting bus mastership with BRx 2 Initial priority assignments 3 Final priority assignments Bus Mastership Time-out...
Page 196: Bus Synchronization After Reset
Shared Memory Interface BMAX (0x180D) 15 14 13 12 11 10 BMAX = maximum # of bus mastership cycles – 2 Bits 31-16 are reserved. Figure 3-17. BMAX Register When decrements to zero, the bus master first completes its off-chip BCNT read/write and then deasserts its own (any new off-chip accesses are...
Page 197 External Port To synchronize their bus arbitration logic and define the bus master after a system reset, the multiple processors obey the following rules: • All processors except the one with = 001 deassert their line during reset. They keep their deasserted for at least two cycles after reset and until their bus arbitration logic is synchronized.
Page 198 Shared Memory Interface If one processor comes out of reset after the others have synchronized and started program execution, that processor may not be able to synchronize immediately (for example, if it detects more than one line asserted). If the non-synchronized processor tries to execute an instruction with an off-chip read or write, it cannot assert its line to request the bus and execution is delayed until it can synchronize and correctly arbitrate for the...
Page 199: Bus Synchronization Notes
External Port /* Force an auto-refresh */ ustat1 = dm(SDCTL); bit set ustat1 F_AR; dm(SDCTL) = ustat1; After this code is executed, the processors in the system can start normal external accesses. These steps must be repeated when a pro- cessor is reset.
Page 200: Bus Lock And Semaphores
Shared Memory Interface Only SDRAM clock ( ) ratios of two and four are supported SDCLK in shared memory systems. Bus Lock and Semaphores To allow the processors in shared memory systems to share resources such as memory or I/O, semaphores can be used. A semaphore is a flag that can be read and written by any of the processors sharing the resource.
Page 201: Shared Memory Interface Status
External Port While the bit is set, the processor can determine if it has acquired BUSLK bus mastership by executing a conditional instruction with the bus master ) or not bus master ( ) condition codes, for example: Not BM IF NOT BM JUMP(PC,0);...
Page 202: Shared Memory And The Sdram Controller
Shared Memory Interface Shared Memory and the SDRAM Controller In a shared memory environment, the SDRAM is shared among two or more ADSP-21368 processors. SDRAM input signals (including clock) are always driven by the bus master. The current bus master continues to hold the bus for t –...
Page 203: Digital Audio/Digital Peripheral Interfaces
4 DIGITAL AUDIO/DIGITAL PERIPHERAL INTERFACES The digital audio interface (DAI) and the digital peripheral interface (DPI) are comprised of a groups of peripherals and their respective signal routing units (SRU1 and SRU2). The inputs and outputs of the peripher- als are not directly connected to external pins. Rather, the SRUs connect the peripherals to a set of pins and to each other, based on a set of config- uration registers.
Page 204: Structure Of The Interfaces
Structure of the Interfaces Table 4-1. Signal Routing Unit Peripheral Assignments (Cont’d) DAI SRU1 DPI SRU2 Input Data Port Flags (12) General-Purpose I/O (20 channels) 1 The precision clock generator (PCG) units C and D can also be routed through the DPI.
Page 205: Dai/Dpi System Design
Digital Audio/Digital Peripheral Interfaces This virtual connectivity design offers a number of distinct advantages: • Flexibility • Increased numbers and kinds of configurations • Connections can be made through software—no hard wiring is required Inputs may only be connected to outputs. DAI/DPI System Design Figure 4-1 Figure 4-2...
Page 206 DAI/DPI System Design DAI PIN BUFFERS DAI PINS SIGNAL ROUTING UNIT DAI_PB11_O DAI_P11 DAI_PB11_I S/PDIF TRANSMITTER DAI_PB11_PE_I DIT_CLK_I DIT_O DIT_DAT_I DAI_PB12_O DIT_FS_I DAI_P12 DAI_PB12_I DIT_HFCLK_I DIT_EXTSYNC_I* DAI_PB12_PE_I BLK_START* DAI_PB13_O S/PDIF RECEIVER DAI_P13 DAI_PB13_I DIR_I DAI_PB13_PE_I DIR_DAT_O DIR_CLK_O DIR_FS_O DAI_PB14_O DIR_TDMCLK_O DAI_P14 DAI_PB14_I SPDIF_PLLCLK_I*...
Page 207 Digital Audio/Digital Peripheral Interfaces DAI PINS DAI PIN BUFFERS SIGNAL ROUTING UNIT DAI_PB01_O DAI_P01 DAI_PB01_I PDAP_STRB_O DAI_PB01_PE_I PDAP DAI_PB02_O DAI_P02 DAI_PB02_I DMA0 IDP0 DAI_PB02_PE_I IDP0_DAT_I IDP0_FS_I IDP0_CLK_I DAI_PB03_O DAI_P03 DAI_PB03_I DAI_PB03_PE_I IDP1 IDP2 DAI_PB04_O IDP3 DAI_P04 DAI_PB04_I IDP4 DAI_PB04_PE_I IDP5 IDP6 IDP7 DAI_PB05_O...
Page 208 DAI/DPI System Design DPI PIN BUFFERS DPI PINS SIGNAL ROUTING UNIT 2 DPI_PB01_O DPI_P01 DPI_PB01_I GENERAL TIMER1_O DPI_PB01_PE_I PURPOSE TIMER1_I COUNTER/ TIMERS DPI_PB02_O TIMER2_O DPI_P02 DPI_PB02_I TIMER2_I DPI_PB02_PE_I TIMER3_O TIMER3_I DPI_PB03_O DPI_P03 DPI_PB03_I FLAGS DPI_PB03_PE_I FLAG [15-4] _PE_O FLAG [15-4] _O DPI_PB04_O DPI_P04 DPI_PB04_I...
Page 209 Digital Audio/Digital Peripheral Interfaces DPI PIN DPI PINS BUFFERS SIGNAL ROUTING UNIT 2 DPI_PB01_O DPI_P08 DPI_PB01_I DPI_PB01_PE_I SPIB SPI_MOSI_I SPI_MOSI_O DPI_PB02_O SPI_MISO_I DPI_P09 DPI_PB02_I SPI_MISO_O DPI_PB02_PE_I SPI_CLK_I SPI_CLK_O SPI_DS_I DPI_PB03_O DPI_P11 SPI_DS_O DPI_PB03_I SPI_FLG0_I DPI_PB03_PE_I SPI_FLG0_O SPI_FLG1_I SPI_FLG1_O DPI_PB04_O DPI_P12 SPI_FLG2_I DPI_PB04_I SPI_FLG2_O...
Page 210: Signal Routing Units
Signal Routing Units Signal Routing Units This section describes how to use the signal routing units (SRU1 and SRU2) to connect inputs to outputs. Connecting Peripherals The SRUs can be likened to a set of patch bays, which contains a bank of inputs and a bank of outputs.
Page 211 Digital Audio/Digital Peripheral Interfaces Table 4-2. Pin Signal Group Assignments (Cont’d) Signal Group DAI (SRU1) DPI (SRU2) Group E Interrupts and miscellaneous signals Group F Pin enable signals used to spec- ify whether each DAI pin is used as an output or an input. Each input and output in each group is given a unique mnemonic.
Page 212: Pin Interface
Signal Routing Units Pin Interface Within the context of the SRUs, physical connections to the DAI/DPI pins are replaced by a logical interface known as a pin buffer. This is a three-terminal active device capable of sourcing/sinking output current when its driver is enabled, and passing external input signals when dis- abled.
Page 213: Pin Buffers As Signal Output Pins
Digital Audio/Digital Peripheral Interfaces When the pin enable is asserted, the pin output is logically equal to pin input, and the pin is driven. When the pin enable is deasserted, the output of the buffer amplifier becomes high impedance. In this situation, an external device may drive a level onto the line, and the pin is used as an input to the ADSP-21367/8/9 and ADSP-2137x processors.
Page 214: Pin Buffers As Signal Input Pins
Signal Routing Units When the DAI/DPI pin is used only as an output, connect the corre- sponding pin buffer enable to logic high as shown in Figure 4-7. This enables the buffer amplifier to operate as a current source and to drive the value present at the pin buffer input onto the DAI/DPI pin and off chip.
Page 215: Bidirectional Pin Buffers
Digital Audio/Digital Peripheral Interfaces PIN BUFFER OUTPUT DAI_PBxx_O EXTERNAL PACKAGE CONNECTION PIN BUFFER INPUT DAI_PBxx_O (NOT USED) INTERFACE DAI_PBxx_I DRIVER TO SRU ENABLE PIN BUFFER ENABLE (= LOW) PBENxx_I Figure 4-8. Pin Buffer as Input Although not strictly necessary, it is recommended programming practice to tie the pin buffer input to logic low whenever the pin buffer enable is tied to logic low.
Page 216 Signal Routing Units For example, from an external perspective, when a serial port (SPORT) is completely routed off chip, it uses four pins—clock, frame sync, data channel A, and data channel B. Because all four of these pins comprise the interface that the serial port presents to SRU1, there are a total of 12 con- nections as shown in Figure...
Page 217: Making Connections In The Srus
Digital Audio/Digital Peripheral Interfaces page A-29. SRU1 then becomes transparent to the peripheral. Figure 4-10 demonstrates SPORT0 properly routed to DAI pins one through four— although it can be equally well routed to any of the 20 DAI pins. Though SPORT signals are capable of operating in this bidirectional man- ner, it is not required that they be connected to the pin buffer this way.
Page 218 Making Connections in the SRUs PB01_O EXTERNAL PB01_O PACKAGE PB01_I CONNECTION ENABLE PBEN01_I PB02_O SPORT0_CLK_I SPORT0_CLK_O EXTERNAL PB02_O PACKAGE PB02_I SPORT0_CLK_PBEN_O CONNECTION ENABLE SPORT0_FS_I SPORT0_FS_O PBEN02_I SPORT0_FS_PBEN_O SPORT0_DA_I PB03_O SPORT0_DA_O SPORT0_DA_PBEN_O EXTERNAL PB03_O SPORT0_DB_I PACKAGE PB03_I CONNECTION SPORT0_DB_O ENABLE SPORT0_DB_PBEN_O PBEN03_I PB04_O EXTERNAL...
Page 219 Digital Audio/Digital Peripheral Interfaces another peripheral. All of the possible encodings represent sources that are clock signals (or at least could be clock signals in some systems). Figure 4-11 diagrams the input signals that are controlled by the DAI group A register, .
Page 220: Dai/Sru1 Connection Groups
Making Connections in the SRUs Just as DAI group A routes clock signals, each of the other groups route a collection of compatible signals. Group B routes serial data streams while group C routes frame sync signals. Group D routes signals to pins so that they may be driven off chip.
Page 221: Group A Connections-Clock Signals
Digital Audio/Digital Peripheral Interfaces Group A Connections—Clock Signals Group A is used to route the following signals to clock inputs and are selected from the list of group A sources. • SPORTs clock inputs (when the SPORTs are in clock slave mode) •...
Page 222 Making Connections in the SRUs 3. Setting = 0x1C connects to logic SRU_CLK4[4:0] PCG_EXTA_I low, not PCG_CLKA_O Setting = 0x1D connects SRU_CLK4[9:5] PCG_EXTB_I logic low, not PCG_CLKB_O 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x252630C2 SRU_CLK0 (0x2430) SPORT3_CLK_I...
Page 223 Digital Audio/Digital Peripheral Interfaces 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_CLK1 (0x2431) Reset = 0x3DEF7BDE SRC1_CLK_OP_I Reserved Sample Rate Converter 1 SRC2_CLK_OP_I Clock Output Input Sample Rate Converter 2 SRC2_CLK_IP_I Clock Output Input Sample Rate Converter 2 Clock Input Input...
Page 224 Making Connections in the SRUs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_CLK3 (0x2433) Reset = 0x3DEF7BDE IDP6_CLK_I Input Data Port Channel Reserved 6 Clock Input DIT_HFCLK_I IDP7_CLK_I SPDIF Oversampling Input Data Port Channel Clock Input 7 Clock Input 15 14 13 12 11 10...
Page 225 Digital Audio/Digital Peripheral Interfaces 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x3DEF7BDE SRU_CLK5 (0x2435) Reserved PCG_SYNC_CLKD_I PCG_EXTD_I Precision Clock Generator Clock D Sync Input Precision Clock Generator External Clock D Input PCG_EXTC_I Precision Clock Generator External Clock C Input...
Page 226 Making Connections in the SRUs Table 4-4. Group A Sources—Serial Clock (Cont’d) Selection Code Source Signal Description (Source) 01011 (0xB) DAI_PB12_O Select DAI pin buffer 12 01100 (0xC) DAI_PB13_O Select DAI pin buffer 13 01101 (0xD) DAI_PB14_O Select DAI pin buffer 14 01110 (0xE) DAI_PB15_O Select DAI pin buffer 15...
Page 227: Group B Connections-Data Signals
Digital Audio/Digital Peripheral Interfaces Group B Connections—Data Signals Group B connections are used to route signals to serial data inputs. This includes serial data inputs to both the A and B channels of the SPORTs and to each of the eight IDP channels. The SRCs and SPDIF transmitter are also selected from the list of group B sources and set in the group B registers.
Page 228 Making Connections in the SRUs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_DAT1 (0x2441) Reset = 0x0F38B289 SPORT3_DB_I Reserved Serial Port 3 Data SPORT4_DB_I Channel B Input Serial Port 4 Data Channel B Input SPORT4_DA_I Serial Port 4 Data Channel A Input 15 14 13 12 11 10...
Page 229 Digital Audio/Digital Peripheral Interfaces 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x00000000 SRU_DAT3 (0x2443) SRC1_TDM_OP_I Reserved Sample Rate Converter 1 TDM Output Input SRC3_TDM_OP_I SRC2_TDM_OP_I Sample Rate Converter 3 TDM Sample Rate Converter 2 Output Input TDM Output Input...
Page 230 Making Connections in the SRUs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_DAT5 (0x2445) Reset = 0x00000000 IDP6_DAT_I DIR_DAT_I Input Data Port 6 SPDIF Receive Data Input Data Input IDP7_DAT_I Input Data Port 7 Data Input 15 14 13 12 11 10 IDP6_DAT_I IDP4_DAT_I...
Page 231 Digital Audio/Digital Peripheral Interfaces Table 4-5. Group B Sources—Serial Data Selection Code Source Signal Description (Source) 000000 (0x0) DAI_PB01_O Select DAI pin buffer 1 000001 (0x1) DAI_PB02_O Select DAI pin buffer 2 000010 (0x2) DAI_PB03_O Select DAI pin buffer 3 000011 (0x3) DAI_PB04_O Select DAI pin buffer 4...
Page 232 Making Connections in the SRUs Table 4-5. Group B Sources—Serial Data (Cont’d) Selection Code Source Signal Description (Source) 011000 (0x18) SPORT2_DA_O Select SPORT 2A data 011001 (0x19) SPORT2_DB_O Select SPORT 2B data 011010 (0x1A) SPORT3_DA_O Select SPORT 3A data 011011 (0x1B) SPORT3_DB_O Select SPORT 3B data 011100 (0x1C)
Page 233: Group C Connections-Frame Sync Signals
Digital Audio/Digital Peripheral Interfaces Table 4-5. Group B Sources—Serial Data (Cont’d) Selection Code Source Signal Description (Source) 110000 (0x30) DIT_O Select SPDIF biphase encoded output 110001 (0x31) –111101 (0x3D) Reserved 111110 (0x3E) Select logic level low (0) 111111 (0x3F) HIGH Select logic level high (1) Group C Connections—Frame Sync Signals Group C connections are used to route signals to frame sync inputs.
Page 234 Making Connections in the SRUs 4. SPORTs 6 and 7 receive frame syncs from other sources but cannot send their own frame syncs to other SPORTs or other peripherals internally through the SRU. If needed, they have to be connected externally through pins. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x2736B4E3 SRU_FS0 (0x2450)
Page 235 Digital Audio/Digital Peripheral Interfaces 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_FS1 (0x2451) Reset = 0x3DEF7BDE SRC1_FS_OP_I Reserved Sample Rate Converter 1 Frame Sync Output Input SRC2_FS_OP_I Sample Rate Converter 2 SRC2_FS_IP_I Frame Sync Output Input Sample Rate Converter 2...
Page 236 Making Connections in the SRUs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x3DEF7BDE SRU_FS3 (0x2453) IDP6_FS_I Input Data Port Channel 6 Reserved Frame Sync Input SPDIF_RX_I IDP7_FS_I SPDIF Receiver Biphase Input Data Port Channel 7 Encoded Data Input Frame Sync Input...
Page 237 Digital Audio/Digital Peripheral Interfaces Table 4-6. Group C Sources—Frame Sync Selection Code Source Signal Description (Source) 00000 (0x0) DAI_PB01_O Select DAI pin buffer 1 00001 (0x1) DAI_PB02_O Select DAI pin buffer 2 00010 (0x2) DAI_PB03_O Select DAI pin buffer 3 00011 (0x3) DAI_PB04_O Select DAI pin buffer 4...
Page 238: Group D Connections-Pin Signal Assignments
Making Connections in the SRUs Table 4-6. Group C Sources—Frame Sync (Cont’d) Selection Code Source Signal Description (Source) 11000 (0x18) SPORT4_FS_O Select SPORT 4 frame sync 11001 (0x19) SPORT5_FS_O Select SPORT 5 frame sync 11010 (0x1A) DIR_FS_O SPDIF_RX frame sync output 11011 (0x1B) Reserved 11100 (0x1C)
Page 239 Digital Audio/Digital Peripheral Interfaces 3. If = 0x13, then setting SRU_PIN4[27:21] SRU_PIN4[29] high does not invert the output. , and are 28-bit reg- SRU_PIN0 SRU_PIN1 SRU_PIN2 SRU_PIN3 isters. Reads on bits 28 through 31 always return zero. is a 30-bit register. Reads on bits 31 and 30 always SRU_PIN4 return zero.
Page 240 Making Connections in the SRUs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x03668C98 SRU_PIN2 (0x2462) DAI_PB11_I Reserved DAI Pin Buffer 11 Input DAI_PB12_I DAI Pin Buffer 12 Input 15 14 13 12 11 10 DAI_PB11_I DAI_PB09_I DAI Pin Buffer 11 Input...
Page 241 Digital Audio/Digital Peripheral Interfaces 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_PIN4 (0x2464) Reset = 0x05694F9E DAI_PB19_I Reserved DAI Pin Buffer 19 Input DAI_PB20_I DAI Pin Buffer 20 Input 15 14 13 12 11 10 DAI_PB19_I DAI_PB17_I DAI Pin Buffer 19 Input...
Page 242 Making Connections in the SRUs Table 4-7. Group D Sources—Pin Signal Assignments (Cont’d) Selection Code Source Signal Description (Source) 0001101 (0xD) DAI_PB14_O Select DAI pin buffer 14 0001110 (0xE) DAI_PB15_O Select DAI pin buffer 15 0001111 (0xF) DAI_PB16_O Select DAI pin buffer 16 0010000 (0x10) DAI_PB17_O Select DAI pin buffer 17...
Page 243 Digital Audio/Digital Peripheral Interfaces Table 4-7. Group D Sources—Pin Signal Assignments (Cont’d) Selection Code Source Signal Description (Source) 0100101 (0x25) SPORT5_CLK_O Select SPORT 5 clock 0100110 (0x26) SPORT0_FS_O Select SPORT 0 frame sync 0100111 (0x27) SPORT1_FS_O Select SPORT 1 frame sync 0101000 (0x28) SPORT2_FS_O Select SPORT 2 frame sync...
Page 244 Making Connections in the SRUs Table 4-7. Group D Sources—Pin Signal Assignments (Cont’d) Selection Code Source Signal Description (Source) 0111111 (0x3F) SRC2_DAT_OP_O SRC2 data output 1000000 (0x40) SRC3_DAT_OP_O SRC3 data output 1000001 (0x41) DIR_DAT_O SPDIF_RX data output 1000010 (0x42) DIR_FS_O SPDIF_RX frame sync output 1000011 (0x43) DIR_CLK_O...
Page 245: Group E Connections-Interrupts And Miscellaneous Signals
Digital Audio/Digital Peripheral Interfaces Group E Connections—Interrupts and Miscellaneous Signals Group E connections, shown in Table 4-8 on page 4-45, are slightly dif- ferent from the others in that the inputs and outputs being routed vary considerably in function. This group routes control signals (interrupts and miscellaneous signals) and provides a means of connecting signals between groups.
Page 246 Making Connections in the SRUs The following notes apply to group E connections. is a 30-bit register. On reads, bits 30 and 31 SRU_EXT_MISCB always return zero. 2. A detailed description of the DAI interrupt register and its usage is provided in “DAI Interrupt Controller Registers”...
Page 247 Digital Audio/Digital Peripheral Interfaces 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_MISCB (0x2471) Reset = 0x3DEF7BDE DAI_INT_25 Reserved DAI Interrupt 25 DAI_INT_27 DAI_INT_26 DAI Interrupt 27 DAI Interrupt 26 15 14 13 12 11 10 DAI_INT_25 DAI Interrupt 25 DAI_INT_22...
Page 248 Making Connections in the SRUs Table 4-8. Group E Sources—Miscellaneous Signals (Cont’d) Selection Code Source Signal Description (Output Source) 01100 (0xC) DAI_PB13_O Select DAI pin buffer 13 output 01101 (0xD) DAI_PB14_O Select DAI pin buffer 14 output 01110 (0xE) DAI_PB15_O Select DAI pin buffer 15 output 01111 (0xF) DAI_PB16_O...
Page 249: Group F-Pin Enable Signals
Digital Audio/Digital Peripheral Interfaces Group F—Pin Enable Signals Group F signals, shown in Figure 4-37 through Figure 4-40 and described Table 4-9, are used to specify whether each DAI pin is used as an out- put or an input by setting the source for the pin buffer enables. When a pin buffer enable ( ) is set (= 1) the signal present at the cor- DAI_PBENxx_I...
Page 250 Making Connections in the SRUs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_PBEN1 (0x2479) Reset = 0x1348D30F PBEN08_I Reserved DAI Port 8 Pin Buffer Enable Input PBEN10_I DAI Port 10 Pin Buffer Enable Input PBEN09_I DAI Port 9 Pin Buffer Enable Input...
Page 251 Digital Audio/Digital Peripheral Interfaces 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_PBEN3 (0x247B) Reset = 0x1D71F79B PBEN18_I Reserved DAI Port 18 Pin Buffer Enable Input PBEN20_I PBEN19_I DAI Port 20 Pin Buffer Enable Input DAI Port 19 Pin Buffer Enable Input 15 14 13 12 11 10...
Page 252 Making Connections in the SRUs Table 4-9. Group F Sources—Pin Output Enable (Cont’d) Selection Code Source Signal Description (Output Source) 001101 (0xD) SPORT1_FS_PBEN_O Select serial port 1 frame sync output enable 001110 (0xE) SPORT1_DA_PBEN_O Select serial port 1 data channel A output enable 001111 (0xF) SPORT1_DB_PBEN_O Select serial port 1 data channel B output enable...
Page 253: Dpi/Sru2 Connection Groups
Digital Audio/Digital Peripheral Interfaces Table 4-9. Group F Sources—Pin Output Enable (Cont’d) Selection Code Source Signal Description (Output Source) 100101 (0x25) SPORT7_FS_PBEN_O Select serial port 7 frame sync output enable 100110 (0x26) SPORT7_DA_PBEN_O Select serial port 7 data channel A output enable 100111 (0x27) SPORT7_DB_PBEN_O Select serial port 7 data channel B output enable...
Page 254: Group A Connections-Input Routing Signals
Making Connections in the SRUs Table 4-10. DPI/SRU2 Default Configuration (Cont’d) Pin Number Signal Pin Number Signal DPI_06 SPIFLG1 DPI_13 TIMER0_O DPI_07 SPIFLG2 DPI_14 TIMER1_O There are three separate groups of connections that are used in SRU2. The following sections summarize each. Group A Connections—Input Routing Signals Group A is used to route the 14 external pin signals, timer, and UART outputs to the inputs of the other peripherals.
Page 255 Digital Audio/Digital Peripheral Interfaces 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU2_INPUT1 Reset = 0x1AC02C00 (0x1C01) UART1_RX_I Reserved UART 1 Receiver Input TWI_SCLK_I TWI_SDATA_I TWI Serial Data Input TWI Serial Clock Input 15 14 13 12 11 10 UART1_RX_I SPIB_DS_I...
Page 256 Making Connections in the SRUs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU2_INPUT3 Reset = 0x00000000 (0x1C03) FLAG10_I Reserved Flag 10 Input FLAG12_I FLAG11_I Flag 11 Input Flag 12 Input 15 14 13 12 11 10 FLAG10_I FLAG7_I Flag 10 Input...
Page 257 Digital Audio/Digital Peripheral Interfaces 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU2_INPUT5 Reset = 0x00000000 (0x1C05) MISC6_I Miscellaneous 6 Input Reserved MISC7_I MISC8_I Miscellaneous 7 Input Miscellaneous 8 Input 15 14 13 12 11 10 MISC6_I MISC3_I Miscellaneous 6 Input...
Page 258: Group B Connections-Pin Assignment Signals
Making Connections in the SRUs Table 4-11. Group A Connections (Cont’d) Binary Decimal Signal Description 01101 DPI_P12_O External pin 12 01110 DPI_P13_O External pin 13 01111 DPI_P14_O External pin 14 10000 TIMER0_O Timer0 output 10001 TIMER1_O Timer1 output 10010 TIMER2_O Timer2 output 10011 UART0_TX_O...
Page 259 Digital Audio/Digital Peripheral Interfaces 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU2_PIN1 Reset = 0x002DB699 (0x01C11) DPI_PB08_I Reserved DPI Pin Buffer 8 Input DPI_PB10_I DPI_PB09_I DPI Pin Buffer 9 Input DPI Pin Buffer 10 Input 15 14 13 12 11 10 DPI_PB08_I DPI_PB06_I...
Page 260 Making Connections in the SRUs Table 4-12. Group B Signals (Cont’d) Binary Decimal Signal Description 000011 DPI_P02_O External pin 2 000100 DPI_P03_O External pin 3 000101 DPI_P04_O External pin 4 000110 DPI_P05_O External pin 5 000111 DPI_P06_O External pin 6 001000 DPI_P07_O External pin 7...
Page 261 Digital Audio/Digital Peripheral Interfaces Table 4-12. Group B Signals (Cont’d) Binary Decimal Signal Description 011011 SPI_FLG3_O Slave select 3 from SPI 011100 SPIB_MISO_O MISO from SPIB 011101 SPIB_M0SI_O MOSI from SPIB 011110 SPIB_CLK_O Clock output from SPIB 011111 SPIB_FLG0_O Slave select 0 from SPIB 100000 SPIB_FLG1_O Slave select 1 from SPIB...
Page 262: Group C Connections-Pin Enable Signals
Making Connections in the SRUs Table 4-12. Group B Signals (Cont’d) Binary Decimal Signal Description 110010 PCG_FSD_O Precision clock generator frame sync D out 110011– 51-63 RESERVED 111111 Group C Connections—Pin Enable Signals Group C signals, shown in Table 4-13 on page 4-62, are used to specify whether each DPI pin is used as an output or an input by setting the source for the pin buffer enable.
Page 263 Digital Audio/Digital Peripheral Interfaces 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU2_PBEN0 Reset = 0x1900C28B (0x01C20) DPI_PBEN03_I Reserved DPI Pin Buffer Enable 3 Input DPI_PBEN05_I DPI_PBEN04_I DPI Pin Buffer Enable 5 Input DPI Pin Buffer Enable 4 Input 15 14 13 12 11 10...
Page 264 Making Connections in the SRUs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU2_PBEN2 Reset = 0x00185964 (0x01C22) DPI_PBEN13_I Reserved DPI Pin Buffer Enable 13 Input DPI_PBEN14_I DPI Pin Buffer Enable 14 Input 15 14 13 12 11 10 DPI_PBEN13_I...
Page 265 Digital Audio/Digital Peripheral Interfaces Table 4-13. Group C Signals (Cont’d) Binary Decimal Signal Description 001101 SPIFLG0_PE_O Pin enable for slave select 0 from SPI 001110 SPIFLG1_PE_O Pin enable for slave select 1 from SPI 001111 SPIFLG2_PE_O Pin enable for slave select 2 from SPI 010000 SPIFLG3_PE_O Pin enable for slave select 3 from SPI...
Page 266: Dai Gpio And Flags
General-Purpose I/O (GPIO) and Flags Table 4-13. Group C Signals (Cont’d) Binary Decimal Signal Description 100101 TWI_SCLK_OE Serial clock output enable from TWI 100110 EXT_MISC_3 Miscellaneous control 3 100111 EXT_MISC_4 Miscellaneous control 4 101000 EXT_MISC_5 Miscellaneous control 5 101001 EXT_MISC_6 Miscellaneous control 6 101010 EXT_MISC_7...
Page 267: Dpi Gpio And Flags
Digital Audio/Digital Peripheral Interfaces DPI GPIO and Flags In the DPI, the signals are used for general-purpose I/O. An EXT_MISC interrupt controller processes these signals to generate an interrupt, for example . The signals can also be used to control pin DPI_INT EXT_MISC enables.
Page 268: Dai Interrupts
DAI/DPI Interrupt Controller generate an interrupt, a signal that a serial port has received data that must be processed, a signal that an SPI has either transmitted or received data, and other software interrupts like the insertion of a trap that causes a breakpoint—all are conditions, which identify to the core that an event has occurred.
Page 269: Dpi Interrupts
Digital Audio/Digital Peripheral Interfaces Just as the core has its own interrupt latch registers ( IRPTL LIRPTL the DAI has its own latch registers ( ). When DAI_IRPTL_L DAI_IRPTL_H a DAI interrupt is configured to be high priority, it is latched in the register.
Page 270 DAI/DPI Interrupt Controller register enables interrupt latching at the falling edge of that DPI_IRPTL_FE signal. A particular interrupt can be latched at the rising or falling edge independently. Keeping corresponding bits reset in both these registers ) disables the corresponding interrupt. DPI_IRPTL_RE DPI_IRPTL_FE interrupt is automatically cleared when the...
Page 271: High And Low Priority Latches
Digital Audio/Digital Peripheral Interfaces High and Low Priority Latches In the ADSP-21367/8/9 and ADSP-2137x processors, a pair of registers ) replace functions normally performed by DAI_IRPTL_H DAI_IRPTL_L register. A single register ( ) specifies the latch to IRPTL DAI_IRPTL_PRI which each of these interrupts are mapped. Two registers ( ) replace the DAI periph- DAI_IRPTL_RE...
Page 272: Rising And Falling Edge Masks
DAI/DPI Interrupt Controller register is read, the high priority latched interrupts are all cleared. When register is read, the low priority latched interrupts are all DAI_IRPTL_L cleared. Rising and Falling Edge Masks For interrupt sources that correspond to waveforms (as opposed to DAI event signals such as DMA complete or buffer full), the edge of a wave- form may be used as an interrupt source as well.
Page 273 Digital Audio/Digital Peripheral Interfaces registers enables the interrupt level on the DAI_IRPTL_RE DAI_IRPTL_FE rising and falling edges, respectively. For more information on these regis- ters, see “DAI Interrupt Controller Registers” on page A-112. Programs can manage responses to signals by configuring registers. In a sample audio application, for example, upon detection of a change of pro- tocol, the output can be muted.
Page 274: Configuring The Spi
Configuring Peripherals Using SRU2 Configuring the PCGs “Precision Clock Generators” on page 13-1 provides extensive informa- tion on programming using the DAI. “Clock and Frame Sync Divisors PCG Channel B” on page 13-20 is an example program that uses PCG channel B to output a clock on DAI pin 1 and a frame sync on DAI pin 2.
Page 275: Configuring The Two Wire Interface
Digital Audio/Digital Peripheral Interfaces Table 4-14. SPI Pin Enable Selections Mode CLKPL CPHASE Use Pin Enable... HIGH HIGH SPI_CLK_O SPI_CLK_O As an example, the output of the clock to DPI pin 3 would be configured in SPI mode 3 as follows. SRU(SPI_CLK_O,DPI_PB03_I);...
Page 276 Configuring Peripherals Using SRU2 SRU(DPI_PB11_O, TWI_DATA_I); /* DPI pin 11 output connected to TWI data input */ SRU(LOW,DPI_PB12_I) /* Since TWI output is an open-drain output, the TWI pin is connected to logic level low */ SRU2(TWI_CLK_PBEN_O,DPI_PBEN12_I) /* TWI clock connected to DPI pin 12 Listing 4-2.
Page 277 Digital Audio/Digital Peripheral Interfaces Listing 4-3. TWI Slave Transmit Mode SRU(LOW,DPI_PB11_I) /* Since TWI output is an open-drain output the TWI pin is connected to logic level low */ SRU(TWI_DATA_PBEN_O,DPI_PBEN11_I) /* TWI data output connected to DPI pin 11 input */ SRU(DPI_PB11_O,TWI_DATA_I) /* DPI pin 11 output connected to TWI data input */...
Page 278: Using The Sru() Macro To Configure The Dai
Using the SRU() Macro to Configure the DAI SRU2(DPI_PB12_O, TWI_CLK_I) /* Clock signal from DPI pin 12 is connected to the TWI slave clock input */ SRU2(LOW,DPI_PBEN12_I) ) /* Disables DPI pin 12 as input as the clock is not generated by the slave Using the SRU() Macro to Configure the DAI...
Page 279 /* Connect pin buffer enable 19 to logic low */ SRU(LOW,DAI_PBEN19_I); Additional example code is available on the Analog Devices Web site. There is a macro that has been created to connect peripherals used in a DAI configuration. This code can be used in both assembly and C code.
Page 280 Using the SRU() Macro to Configure the DAI 4-78 ADSP-21368 SHARC Processor Hardware Reference...
Page 281: Serial Ports
5 SERIAL PORTS The ADSP-21367/8/9 and ADSP-2137x processors have up to eight inde- pendent, synchronous serial ports (SPORTs) that provide an I/O interface to a wide variety of peripheral devices. They are called SPORT0, SPORT1, SPORT2, SPORT3, SPORT4, SPORT 5, SPORT6, and SPORT7.
Page 282: Features
Features Features Serial ports offer the following additional features and capabilities: • Two additional SPORTs, each with their own DMA channels and interrupts, have been added to the ADSP-21367, ADSP-21368, ADSP-21369, and ADSP-21371 SHARC processors. • Two bidirectional channels (A and B) per SPORT, configurable as either transmitters or receivers.
Page 283: Operation Modes
Serial Ports New DMA channels are added for SPORT6 and 7. These new SPORTs also have their own interrupt lines. Operation Modes Thee serial ports have four operation modes: standard DSP serial, left-jus- tified sample pair, I S, and multichannel. In standard DSP serial, left-justified sample pair and I S modes, when both A and B channels are used, they transmit or receive data simultaneously, sending or receiving bit...
Page 284 Operation Modes • In multichannel mode, support for packed I S mode is new for the ADSP-21367/8/9 and ADSP-2137x processors. However, it should be noted that packed I S mode is not identical to I S mode in all cases. For more information, see “Packed I2S Mode”...
Page 285: Serial Port Signals
Serial Ports Serial Port Signals Figure 5-1 shows the SPORT signals (note that not all models have eight SPORTs). Any 20 of these 32 signals can be mapped to digital audio interface ( ) pins through the signal routing unit (SRU1). For more DAI_Px information, see Chapter 4, Digital Audio/Digital Peripheral...
Page 286 Serial Port Signals Pairings of SPORTs (0 and 1, 2 and 3, and 4 and 5, 6 and 7) are used only in loopback mode for testing. A SPORT receives serial data on one of its bidirectional serial data signals configured as inputs, or transmits serial data on the bidirectional serial data signals configured as outputs.
Page 287 Serial Ports Figure 5-2 shows a block diagram of a SPORT. Setting the SPTRAN enables the data buffer path, which, once activated, responds by shifting data in at the rate of . An application program must use the SPORTx_CLK correct SPORT data buffers, according to the value of bit.
Page 288 Serial Port Signals DM DATA BUS I/O DATA BUS PM DATA BUS TXSPxA TXSPxB RXSPxB RXSPxA TRANSMIT DATA TRANSMIT DATA BUFFER RECEIVE DATA BUFFER RECEIVE DATA BUFFER BUFFER HARDWARE HARDWARE COMPANDING COMPANDING (COMPRESSION) (EXPANSION) SPORTS 0, 2, 4 & 6 ONLY SPORTS 1, 3, 5 &...
Page 289: Serial Port Signal Sensitivity
Serial Ports A channel, the data is (optionally) expanded (SPORT1, 3, and 5 only), then automatically transferred to the buffer. When an entire word RXSPxA is shifted in on the secondary channel, it is automatically transferred to the buffer. RXSPxB When the SPORT is configured as a receiver ( = 0), the SPTRAN...
Page 290: Sport Operation Modes
SPORT Operation Modes ) to the pin buffer input ( ). The connection of SPORTx_CLK_O PBxx_I opens a vulnerability to a glitch coming in even PBxx_O SPORTx_CLK_I though the SPORT is driving the clock as an output. By programming SRU1 to remove this input path, programs can avoid this vulnerability. This is done by leaving the routing of as before, SPORTx_CLK_O...
Page 291: Standard Dsp Serial Mode
Serial Ports The operating mode ( ) bit of the register selects between I OPMODE SPCTLx mode/left-justified sample pair mode, and non-I S mode (DSP serial port/multichannel mode). In multichannel mode, the bit in the MCEA SPM- register enables the A channels and the bit in the CTLx MCEB...
Page 292 SPORT Operation Modes Table 5-1. SPORT Operation Modes (Cont’d) Bits OPMODE LAFS FRFS MCEA MCEB SLENx Operating Modes Packed I S Mode A Channel 3-32 Packed I S Mode B Channel 3-32 Packed I S Mode A and B 3-32 Channels Left-justified Sample Pair 8-32...
Page 293: Standard Dsp Serial Mode Control Bits
Serial Ports Standard DSP Serial Mode Control Bits Several bits in the control register enable and configure standard SPCTLx DSP serial mode operation: • Operation mode, master mode enable ( OPMODE • Word length ( SLEN • SPORT enable ( SPEN_A SPEN_B Clocking Options...
Page 294: Data Formatting
SPORT Operation Modes details on this option. Similar to the serial clock, the frame sync can be an external signal or generated internally. The bit in the register SPCTL allows the selection between these options (see the internal frame sync select bit description in Figure 5-10 on page 5-70 for more details).
Page 295: Data Transfers
Serial Ports The endian format (LSB versus MSB first) is selectable by the bit of LSBF register (see “Endian Format” on page 5-45 for more details). SPCTL Data packing of two serial words into a 32-bit word is also selectable. The bit in the register controls this option.
Page 296: Left-Justified Sample Pair Mode
SPORT Operation Modes Left-Justified Sample Pair Mode In left-justified sample pair mode, each frame sync cycle receives or trans- mits two samples of data—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Prior to develop- ment of the I S standard, many manufacturers used a variety of non-standard stereo modes.
Page 297: Setting The Internal Serial Clock And Frame Sync Rates
Serial Ports Setting the Internal Serial Clock and Frame Sync Rates The serial clock rate for internal clocks can be set using the CLKDIV field in the register and the frame sync rate for internal frame sync DIVx can be set using the bit field in the register.
Page 298: Enabling Sport Master Mode (Mstr)
SPORT Operation Modes To transmit or receive words continuously in left-justified sample pair mode, load the register with the value the same as . For FSDIV SLEN example, for 8-bit data words where = 7, set = 7. SLEN FSDIV Enabling SPORT Master Mode (MSTR) The SPORTs transmit and receive channels can be configured for master or slave mode.
Page 299: Enabling Sport Dma (Sden)
Serial Ports Enabling SPORT DMA (SDEN) DMA can be enabled or disabled independently on any SPORT transmit and receive channels. For more information, see “Moving Data Between SPORTs and Internal Memory” on page 5-73. (=1) SDEN_A SDEN_B to enable DMA and set the channel in DMA-driven data transfer mode. Clear (=0) to disable DMA and set the channel in an SDEN_A...
Page 300: I2S Mode
SPORT Operation Modes SPORTX_CLK SPORTx_FS/WS LEFT-JUSTIFIED SAMPLE LSB n-1 MSB n LSB n MSB n+1 PAIR MODE DATA OR SPORTX_DA OR SPORTX_DB SAMPLE n-1 SAMPLE n SAMPLE n+1 Figure 5-3. Word Select Timing in Left-Justified Sample Pair Mode 1 This figure illustrates only one possible combination of settings attainable in the left-justified sample pair mode.
Page 301: Setting The Internal Serial Clock And Frame Sync Rates
Serial Ports The I S bus transmits audio data and control signals over separate lines. The data line carries two multiplexed data channels—the left channel and the right channel. In I S mode, if both channels on a SPORT are set up to transmit, then SPORT transmit channels ( ) transmit TXSPxA...
Page 302: Setting Word Length (Slen)
SPORT Operation Modes Several bits in the register control register enable and configure I SPCTLx operation: • Operation mode enable ( OPMODE • Channel enable ( SPEN_A SPEN_B • Word length ( SLEN • I S channel transfer order ( FRFS •...
Page 303: Enabling Sport Master Mode (Mstr)
Serial Ports Enabling SPORT Master Mode (MSTR) The SPORTs transmit and receive channels can be configured for master or slave mode. In master mode, the processor generates the word select and serial clock signals for the transmitter or receiver. In slave mode, an external source generates the word select and serial clock signals for the transmitter or receiver.
Page 304: Enabling Sport Dma (Sden)
SPORT Operation Modes When using both SPORT channels ( ) as trans- SPORTx_DA SPORTx_DB mitters and = 1, = 1, and = 0, the processor generates a MSTR SPTRAN DIFS frame sync signal only when both transmit buffers contain data because both transmitters share the same .
Page 305: Multichannel Operation
Serial Ports Interrupt-Driven Data Transfer Mode Both the A and B channels share a common interrupt vector in the inter- rupt-driven data transfer mode, regardless of whether they are configured as a transmitter or receiver. The SPORT generates an interrupt when the transmit buffer has a vacancy or the receive buffer has data.
Page 306 SPORT Operation Modes SPORTX_CLK SPORTX_FS/WS LEFT-JUSTIFI ED SAMPLE LSB n-1 MSB n LSB n MSB n+1 PAIR MODE DATA OR SPORTX_DA OR SPORTX_DB WORD n-1 WORD N WORD N+1 RIGHT CHANNEL LEFT CHANNEL RIG HT CHANNEL Figure 5-4. Word Select Timing in I S Mode serial bit stream occupies a separate channel.
Page 307 Serial Ports Although the eight SPORTs are programmable for data direction in the standard mode of operation, their programmability is restricted for multi- channel operations. The following points summarize these limitations: 1. The primary A channels of SPORT1, 3, 5, and 7 are capable of expansion only, and the primary A channels of SPORT0, 2, 4, and 6 are capable of companding only.
Page 308: Frame Syncs In Multichannel Mode
SPORT Operation Modes • The multichannel transfer is received on channel 0 (word 0), and transmits on channels 1 and 2 (word 1 and 2). WORD 0 WORD 1 WORD 2 SPORT1_CLK SPORT1_DA/B IGNORED SPORT1_FS SPORT0_DA/B SPORT0_TDV Figure 5-5. Multichannel Operation Frame Syncs in Multichannel Mode In previous SHARC processors, all receiving and transmitting devices in a multichannel system had to use the same timing reference.
Page 309: Multichannel Mode Control Bits
Serial Ports After the transmit buffer is loaded, transmission begins and the TXSPxA signal is generated. When SPORT DMA is used, this signal SPORTx_TDV may occur several cycles after the multichannel transmission is enabled. If a deterministic start time is required, pre-load the transmit buffer. Active State Multichannel Frame Sync Select bit in the , registers selects the logic level of the multichan-...
Page 310 SPORT Operation Modes Multichannel operation is activated three serial clock cycles after the bits are set. Internally-generated frame sync signals activate four MCEA MCEB serial clock cycles after the bits are set. MCEA MCEB Select the number of channels used in multichannel operation by using the 7-bit field in the multichannel control register.
Page 311 Serial Ports This bit is set when the channel has received new data while the RXSPxA buffer is full. New data then overwrites existing data. When the RXSPxB SPORT is configured as a transmitter this bit indicates the transmit underflow status (sticky, read-only). This bit is set, = 1 when multichannel signal (from internal or external source) occurred while the SPORTx_FS TXS buffer was empty.
Page 312 SPORT Operation Modes Table 5-2. Multichannel Selection Registers (Cont’d) Register Names Function SP1CCS(0–3) Multichannel Receive Compand Select. Specifies which active receive SP3CCS(0–3) channels (out of 128 channels) are companded. SP5CCS(0–3) SP7CCS(0–3) SP0CCS(0–3) Multichannel Transmit Compand Select. Specifies which active trans- SP2CCS(0–3) mit channels (out of 128 channels) are companded.
Page 313: Packed I2S Mode
Serial Ports Packed I S Mode A packed I S mode is available in ADSP-21367/8/9 SHARC processor serial ports. This mode allows applications to send more than the standard 32 bits per channel available through standard I S mode. Packed I mode is implemented using standard TDM mode (and is therefore pro- grammed similarly to TDM mode).
Page 314 SPORT Operation Modes Programming Packed I S Mode Since packed I S mode is implemented on top of TDM, programming this modes is the same as programming TDM. Use the serial port control ) and channel selection registers to configure the serial ports to run SPCTLx in packed I S mode as follows.
Page 315: Sport Loopback
Serial Ports SPORT Loopback When the SPORT loopback bit, bit 12, is set in the , control SPMCTLx registers, the SPORT is configured in an internal loopback connection as follows: SPORT0 and SPORT1 work as a pair for internal loopback, SPORT2 and SPORT3 work as pairs, SPORT4 and SPORT5 and SPORT6 and SPORT7 work as pairs.
Page 316: Clock Signal Options
Clock Signal Options not allowed. Only standard DSP serial, left-justified sample pair, and I S modes support internal loopback. In loopback, each SPORT can be configured as transmitter or receiver, and each SPORT is capable of generating an internal frame sync and clock. Any of the four paired SPORTs can be set up to transmit or receive, depending on their bit configurations.
Page 317: Frame Sync Options
Serial Ports Frame Sync Options Framing signals indicate the beginning of each serial word transfer. A vari- ety of framing options are available on the SPORTs. The SPORTx_FS signals are independent and are separately configured in the control register. Framed Versus Unframed Frame Syncs The use of frame sync signals is optional in SPORT communications.
Page 318: Internal Versus External Frame Syncs
Frame Sync Options SPORTX_CLK FRAMED DATA UNFRAMED DATA Figure 5-7. Framed Versus Unframed Data Internal Versus External Frame Syncs Both transmit and receive frame syncs can be generated internally or input from an external source. The bit of the control registers deter- SPCTLx mines the frame sync source.
Page 319: Active Low Versus Active High Frame Syncs
Serial Ports Active Low Versus Active High Frame Syncs Frame sync signals may be active high or active low (for example, inverted). The bit (bit 16) of the control registers determines SPCTLx the frame sync’s logic level: • When is cleared (=0), the corresponding frame sync signal is active high.
Page 320: Early Versus Late Frame Syncs
Frame Sync Options Early Versus Late Frame Syncs Frame sync signals can be early or late. Frame sync signals can occur dur- ing the first bit of each data word or during the serial clock cycle immediately preceding the first bit. The bit of the control LAFS...
Page 321: Data-Independent Frame Syncs
Serial Ports SPORTX_CLK LATE FRAME SYNC EARLY FRAME SYNC DATA Figure 5-8. Normal Versus Alternate Framing Data-Independent Frame Syncs When transmitting data out of the SPORT ( = 1), the inter- SPTRAN nally-generated frame sync signal normally is output-only when the transmit buffer has data ready to transmit.
Page 322: Frame Sync Error Detection
Frame Sync Options mode of operation allows data to be transmitted only at specific times. When = 0 and = 0, a receive signal is generated DIFS SPTRAN SPORTx_FS only when receive data buffer status is not full. When = 1 and = 1, the internally-generated transmit frame DIFS SPTRAN...
Page 323: Data Word Formats
Serial Ports Unlike previous SHARC processors where programs had to poll the SPORT control registers, on the ADSP-21367/8/9 and ADSP-2137x pro- cessors, an interrupt is triggered and programs simply read the SPERRSTAT register (Figure 5-9). This reduces the processor overhead needed to do the register polling.
Page 324 Data Word Formats 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SP0 FSERR Int Status Reserved SP1 FSERR Int Status SP7 FSERR Int Status SP2 FSERR Int Status SP3 FSERR Int Status SP4 FSERR Int Status SP5 FSERR Int Status SP6 FSERR Int Status...
Page 325: Endian Format
Serial Ports Transmitting or receiving words smaller than 5 bits may cause incorrect operation when all the DMA channels are enabled with no DMA chaining. Endian Format Endian format determines whether serial words transmit MSB first or LSB first. Endian format is selected by the bit in the control regis- LSBF...
Page 326: Data Type
Data Word Formats Data Type field of the control registers specifies one of four data DTYPE SPCTLx formats (for non-multichannel operation) shown in Table 5-3. This bit field is reserved in I S and left-justified mode. In DSP serial mode, if com- panding is selected for primary A channel, the secondary B channel performs a zero-fill.
Page 327: Companding
Serial Ports Linear transfers occur in the primary channel, if the channel is active and companding is not selected for that channel. Companded transfers occur if the channel is active and companding is selected for that channel. The multichannel compand select registers, , specify the transmit and SPxCCSy receive channels that are companded when multichannel mode is enabled.
Page 328 Data Word Formats When companding is enabled, the data in the buffers is the RXSPxA right-justified, sign-extended expanded value of the eight received LSBs. A write to compresses the 32-bit value to eight LSBs (zero-filled to TXSPxA the width of the transmit word) before it is transmitted. If the 32-bit value is greater than the 13-bit A-law or 14-bit μ-law maximum, it is automati- cally compressed to the maximum value.
Page 329: Sport Control Registers And Data Buffers
Serial Ports With companding enabled, interfacing the SPORT to a codec requires lit- tle additional programming effort. If companding is not selected, two formats are available for received data words of fewer than 32 bits—one that fills unused MSBs with zeros, and another that sign-extends the MSB into the unused bits.
Page 330 SPORT Control Registers and Data Buffers Table 5-5 through Table 5-8 provides a complete list of the SPORT regis- ters in IOP address order, showing the memory-mapped IOP address and a brief description of each register. Table 5-5. SPORT0 and SPORT1 Registers Register Function Width...
Page 331 Serial Ports Table 5-5. SPORT0 and SPORT1 Registers (Cont’d) Register Function Width No. of Memory Map Name Registers [17:0] CP0A Chain Pointer for DMA Chaining 00C43 Channel 0A II0B Address for DMA Channel 0B 000C44 IM0B Internal Modifier for DMA Channel 0B 00C45 Counter for DMA Channel 0B 00C46...
Page 332 SPORT Control Registers and Data Buffers Table 5-5. SPORT0 and SPORT1 Registers (Cont’d) Register Function Width No. of Memory Map Name Registers [17:0] TX1B Transmitter FIFO Register in SP1B 00C66 RX1B Receiver FIFO Register in SP1B 00C67 Table 5-6. SPORT2 and SPORT3 Registers Register Function Width...
Page 333 Serial Ports Table 5-6. SPORT2 and SPORT3 Registers (Cont’d) Register Function Width No. of Memory Map Name Registers [17:0] IM2A Internal Modifier for DMA Channel 2A 00441 Counter for DMA Channel 2A 00442 CP2A Chain Pointer for DMA Chaining 00443 Channel 2A II2B Address for DMA Channel 2B...
Page 334 SPORT Control Registers and Data Buffers Table 5-6. SPORT2 and SPORT3 Registers (Cont’d) Register Function Width No. of Memory Map Name Registers [17:0] RX3A Receiver FIFO Register in SP3A 00465 TX3B Transmitter FIFO Register in SP3B 00466 RX3B Receiver FIFO Register in SP3B 00467 Table 5-7.
Page 335 Serial Ports Table 5-7. SPORT4 and SPORT5 Registers (Cont’d) Register Function Width No. of Memory Map Name Registers [17:0] II4A Address for DMA Channel 4A 00840 IM4A Internal Modifier for DMA Channel 4A 00841 Counter for DMA Channel 4A 00842 CP4A Chain Pointer for DMA Chaining 00843...
Page 336 SPORT Control Registers and Data Buffers Table 5-7. SPORT4 and SPORT5 Registers (Cont’d) Register Function Width No. of Memory Map Name Registers [17:0] TX5A Transmitter FIFO Register in SP5A 00864 RX5A Receiver FIFO Register in SP35A 00865 TX5B Transmitter FIFO Register in SP5B 00866 RX5B Receiver FIFO Register in SP5B...
Page 337 Serial Ports Table 5-8. SPORT6 and SPORT7 Registers (Cont’d) Register Name Function Width No. of Memory Map Registers [17:0] Reserved 0481A–0483F II6A Address for DMA Channel 6A 04840 IM6A Internal Modifier for DMA Channel 04841 Counter for DMA Channel 6A 04842 CP6A Chain Pointer for DMA Chaining...
Page 338 SPORT Control Registers and Data Buffers Table 5-8. SPORT6 and SPORT7 Registers (Cont’d) Register Name Function Width No. of Memory Map Registers [17:0] RX6A Receiver FIFO Register in SP6A 04861 TX6B Transmitter FIFO Register in SP6B 04862 RX6B Receiver FIFO Register in SP6B 04863 TX7A Transmitter FIFO Register in SP7A...
Page 339: Serial Port Control Registers (Spctlx)
Serial Ports Serial Port Control Registers (SPCTLx) The main control registers for each SPORT are the SPORT control regis- ters, . These registers are described in “SPORT Serial Control SPCTLx Registers (SPCTLx)” on page A-29. When changing operating modes, clear the SPORT control registers before the new mode is written to the registers.
Page 340 SPORT Control Registers and Data Buffers Table 5-9. SPCTLx Control Bit Comparison in Four SPORT Operation Modes (Cont’d) Standard DSP Serial Mode Left-justified and I S Mode Multichannel Mode ICLK MSTR ICLK OPMODE OPMODE OPMODE CKRE Reserved CKRE Reserved Reserved Reserved IMFS DIFS...
Page 341 Serial Ports The following bits, listed in bit number order, control SPORT modes and are part of the (transmit and receive) control registers. Other bits SPCTLx in the registers set up DMA and I/O processor-related SPORT fea- SPCTLx tures. For information about configuring a specific operation mode, refer Table 5-1 on page 5-11 “Standard DSP Serial Mode”...
Page 342 SPORT Control Registers and Data Buffers This description applies only to DSP standard serial and multichannel modes only. Serial word endian select. registers, bit 3 ( ). This bit selects SPCTLx LSBF little endian words (LSB first, if set, = 1) or big endian words (MSB first, if cleared, = 0).
Page 343 Serial Ports Frame sync required select. registers, bit 13 ( ). This bit selects SPCTLx whether the SPORT requires (if set, = 1) or does not require (if cleared, = 0) a transfer frame sync. See “Frame Sync Options” on page 5-37 more details.
Page 344 SPORT Control Registers and Data Buffers Frame sync both enable. registers, bit 22 ( ). This bit SPCTLx FS_BOTH applies when the SPORTs channels A and B are configured to trans- mit/receive data. If set (= 1), this bit issues frame sync only when data is present in both transmit buffers, .
Page 345 Serial Ports When set (= 1), the SPORT is configured to transmit on both channels A and B. When configured to transmit, the buffers are TXSPxA TXSPxB activated, while the transmit shift registers are controlled by SPORTx_CLK . The buffers are inactive. This bit SPORTx_FS RXSPxA RXSPxB...
Page 346 SPORT Control Registers and Data Buffers Specifically, the operation of the bit is: ROVF • 0 = No new data while buffer is full. RXSPxA/B • 1 = New data while buffer is full. RXSPxA/B When the bit is cleared (the default setting), the frame sync signal DIFS ) is dependent upon new data being present in the transmit SPORTx_FS...
Page 347: Transmit And Receive Data Buffers (Txspxa/B, Rxspxa/B)
Serial Ports When the SPORT is configured as a transmitter, these bits reflect transmit buffer status for the buffers. When the TXSPxA TXSPxB SPORT is configured as a receiver, these bits reflect receive buffer status for the buffers. RXSPxA RXSPxB Transmit and Receive Data Buffers (TXSPxA/B, RXSPxA/B) The transmit buffers (...
Page 348 SPORT Control Registers and Data Buffers buffer is ready to accept the next word (for example, the transmit buffer is not full). This interrupt does not occur when SPORT DMA is enabled or when the corresponding mask bit in the register is set.
Page 349: Clock And Frame Sync Frequency Registers (Divx)
Serial Ports To support debugging buffer transfers, the ADSP-21367/8/9 and ADSP-2137x processors have a buffer hang disable ( ) bit. When set (= 1), this bit prevents the processor core from detecting a buffer-related stall condition, permitting debugging of this type of stall condition. For more information, see the bit description on on page...
Page 350 SPORT Control Registers and Data Buffers transmitters. The divisor is a 15-bit value, allowing a wide range of serial clock rates. Use the following equation to calculate the serial clock frequency: f CCLK --------------------------------------- SPORTx_CLK 8 CLKDIV The maximum serial clock frequency is equal to one-eighth the processor’s internal clock ( ) frequency, which occurs when is set to zero.
Page 351: Sport Reset
Serial Ports Use the following equation to determine the value of , given the FSDIV serial clock frequency and desired frame sync frequency: SPORTx_CLK --------------------------- - 1 – FSDIV SPORTx_FS The frame sync is continuously active when = 0. The value of FSDIV FSDIV should not be less than the serial word length minus one (the value of the...
Page 352: Sport Interrupts
SPORT Control Registers and Data Buffers A software reset of the enable bit disables the SPORT(s) SPEN_A SPEN_B and aborts any ongoing operations. Status bits are also cleared. The SPORTs are ready to start transmitting or receiving data two serial clock cycles after they are enabled in the registers.
Page 353: Moving Data Between Sports And Internal Memory
Serial Ports SPORT interrupts occur on the second system clock ( ) after the last CLKIN bit of the serial word is latched in or driven out. Moving Data Between SPORTs and Internal Memory Transmit and receive data can be transferred between the SPORTs and on-chip memory with single word transfers or with DMA block transfers.
Page 354 Moving Data Between SPORTs and Internal Memory Table 5-11. Serial Port DMA Channels Channel Data Buffer Description Priority RXSP1A/TXSP1A SPORT1 A data Highest RXSP1B/TXSP1B SPORT1 B data RXSP0A/TXSP0A SPORT0 A data RXSP0B/TXSP0B SPORT0 B data RXSP3A/TXSP3A SPORT3 A data RXSP3B/TXSP3B SPORT3 B data RXSP2A/TXSP2A SPORT2 A data...
Page 355: Setting Up Dma On Sport Channels
Serial Ports Although the DMA transfers are performed with 32-bit words, SPORTs can handle word sizes from 3 to 32 bits, with 8 to 32 bits for I S mode. If serial words are 16 bits or smaller, they can be packed into 32-bit words for each DMA transfer.
Page 356: Sport Dma Parameter Registers
Moving Data Between SPORTs and Internal Memory Table 5-12. SPORT DMA Parameter Registers Register Width Description (Y = A or B, and x = 0 – 5) IISPxy 19 bits DMA channel; x index; start address for data buffer IMSPxy 16 bits DMA channel;...
Page 357 Serial Ports The DMA channels operate similarly to the processor’s data address gen- erators (DAGs). Each channel has an index register ( ) and a modify IISPxy register ( ) for setting up a data buffer in internal memory. It is nec- IMSPxy essary to initialize the index register with the starting address of the data buffer.
Page 358 Moving Data Between SPORTs and Internal Memory Table 5-13. SPORT DMA Parameter Registers Addresses (Cont’d) Register Address DMA Channel SPORT Buffer IMSP1A 0xC49 RXSP1A or TXSP1A CSP1A 0xC4A RXSP1A or TXSP1A CPSP1A 0xC4B RXSP1A or TXSP1A IISP1B 0xC4C RXSP1B or TXSP1B IMSP1B 0xC4D RXSP1B or TXSP1B...
Page 359 Serial Ports Table 5-13. SPORT DMA Parameter Registers Addresses (Cont’d) Register Address DMA Channel SPORT Buffer Reserved IISP4A 0x840 RXSP4A or TXSP4A IMSP4A 0x841 RXSP4A or TXSP4A CSP4A 0x842 RXSP4A or TXSP4A CPSP4A 0x843 RXSP4A or TXSP4A IISP4B 0x844 RXSP4B or TXSP4B IMSP4B 0x845 RXSP4B or TXSP4B...
Page 360 Moving Data Between SPORTs and Internal Memory Table 5-13. SPORT DMA Parameter Registers Addresses (Cont’d) Register Address DMA Channel SPORT Buffer CPSP6B 0x4847 RXSP6B or TXSP6B IISP7A 0x4848 RXSP7A or TXSP7A IMSP7A 0x4849 RXSP7A or TXSP7A CSP7A 0x484A RXSP7A or TXSP7A CPSP7A 0x484B RXSP7A or TXSP7A...
Page 361: Sport Dma Chaining
Serial Ports Therefore, set the direction bit, the SPORT enable bit, and DMA enable bits before initiating any operations on the SPORT data buffers. If the processor operates on the inactive transmit or receive buffers while the SPORT is enabled, it can cause unpredictable results. SPORT DMA Chaining In chained DMA operations, the processor’s DMA controller automati- cally sets up another DMA transfer when the contents of the current...
Page 362: Sport Programming Examples
SPORT Programming Examples To avoid hanging the processor core, check the buffer’s full/empty status when the processor core’s program reads a word from a SPORT’s receive buffer or writes a word to its transmit buffer. The full/empty status can be read in the bits of the registers.
Page 363 Serial Ports The third listing, Listing 5-3, transmits a buffer of data from SPORT1 using DMA chaining and the internal loopback feature of the SPORT0 SPORT. In this example, drives the clock and frame sync, and the SPORT5 two TCBs for each are set up to ping-pong back and forth to con- SPORT tinually send and receive data.
Page 364 SPORT Programming Examples /* Default Buffer Length */ #define BUFSIZE 10 .SECTION/DM seg_dmda; /*Transmit buffer*/ .var tx_buf5a[BUFSIZE] = 0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x88888888, 0x99999999, 0xAAAAAAAA; /*Receive buffer*/ .var rx_buf4a[BUFSIZE]; /* Main code section */ .global _main; .SECTION/PM seg_pmco; _main: SPORT Loopback: Use SPORT4 as RX &...
Page 365 Serial Ports /* SPORT 5 Internal DMA memory address */ r0 = tx_buf5a; dm(IISP5A) = r0; /* SPORT 5 Internal DMA memory access modifier r0 = 1; dm(IMSP5A) = r0; /* SPORT 5 Number of DMA transfers to be done */ r0 = @tx_buf5a;...
Page 366 SPORT Programming Examples r0 = 0x0; dm(DIV4) = R0; ustat3 = SPEN_A| /* Enable Channel A */ SLEN32| /* 32-bit word length */ FSR| /* Frame Sync Required */ SDEN_A; /* Enable Channel A DMA */ dm(SPCTL4) = ustat3; _main.end: jump (pc,0);...
Page 367 Serial Ports .SECTION/DM seg_dmda; /* Transmit Buffer */ .var tx_buf2a[BUFSIZE] = 0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x88888888, 0x99999999, 0xAAAAAAAA; /* Receive Buffer */ .var rx_buf3a[BUFSIZE]; /* Main code section */ .global _main; .SECTION/PM seg_pmco; _main: //bit set mode1 CBUFEN; /* enable circular buffers SPORT Loopback: Use SPORT2 as RX &...
Page 368 SPORT Programming Examples SPORT_DMA_setup: /* set internal loopback bit for SPORT2 & SPORT3 */ bit set ustat3 SPL; dm(SPMCTL2) = ustat3; /* Configure SPORT2 as a transmitter */ /* internally generating clock and frame sync */ /* CLKDIV = [fCCLK(333MHz)/2 x FSCLK(8.325 MHz)] – 1 = 0x0004 */ /* FSDIV = [FSCLK(8.325 MHz)/TFS(.26 MHz)] –...
Page 369 Serial Ports Listing 5-3. SPORT Transmit Using DMA /* SPORT DMA Parameter Registers */ #define CPSP0A 0xC43 #define CPSP1A 0xC4B /* SPORT Control Registers */ #define DIV0 0xC02 #define DIV1 0xC03 #define SPCTL0 0xC00 #define SPCTL1 0xC01 #define SPMCTL0 0xC04 /* SPMCTL Bits */ #define SPL 0x00001000...
Page 370 SPORT Programming Examples 0x44444444, 0x55555555, 0x66666666, 0x77777777, 0x88888888, 0x99999999, 0xAAAAAAAA; .var tx_buf1b[BUFSIZE] = 0x12345678, 0x23456789, 0x3456789A, 0x456789AB, 0x56789ABC, 0x6789ABCD, 0x789ABCDE, 0x89ABCDEF, 0x9ABCDEF0, 0xABCDEF01; /* RX Buffers */ .var rx_buf0a[BUFSIZE]; .var rx_buf0b[BUFSIZE]; /* TX Transfer Control Blocks */ .var tx_tcb1[4] = 0,BUFSIZE,1,tx_buf1a; .var tx_tcb2[4] = 0,BUFSIZE,1,tx_buf1b;...
Page 371 Serial Ports _main: SPORT Loopback: Use SPORT0 as RX & SPORT1 as TX /* initially clear SPORT control register */ r0 = 0x00000000; dm(SPCTL0) = r0; dm(SPCTL1) = r0; dm(SPMCTL1) = r0; SPORT_DMA_setup: /* set internal loopback bit for SPORT0 & SPORT1 */ bit set ustat3 SPL;...
Page 372 SPORT Programming Examples SLEN32| /* 32-bit word length */ FSR| /* Frame Sync Required */ SDEN_A| /* Enable Channel A DMA */ SCHEN_A; /* Enable Channel A DMA Chaining */ dm(SPCTL0) = ustat3; /* Next TCB location for tx_tcb2 is tx_tcb1 */ /* Mask the first 19 bits of the TCB location */ r0 = (tx_tcb1 + 3) &...
Page 373: Serial Peripheral Interface Ports
6 SERIAL PERIPHERAL INTERFACE PORTS The ADSP-21367/8/9 and ADSP-2137x processors are equipped with two synchronous serial peripheral interface ports that are compatible with the industry-standard serial peripheral interface (SPI). The SPI ports are routed through the digital peripheral interface pins (DPI14–1). At reset, SPI functionality is available on DPI pins 1–8.
Page 374: Functional Description
Functional Description • Programmable baud rates, clock polarities, and phases • Master or slave booting from a master SPI device (“DPI/SRU2 Connection Groups” on page 4-51) • DMA capability to allow data transfers without core overhead Functional Description Each SPI port contain its own transmit shift ( ) and receive TXSR TXSRB...
Page 375 Serial Peripheral Interface Ports SPIDS MOSI MISO SPICLK FLAGX SPI INTERNAL SPI INTERFACE LOGIC CLOCK GENERATOR SPISTAT SPICTL RXSR TXSR RX SHIFT REGISTER TX SHIFT REGISTER TXSPI RXSPI TRANSMIT RECEIVE REGISTER REGISTER SPI IRQ OR DM DATA BUS DMA REQUEST PM DATA BUS I/0 DATA BUS Figure 6-1.
Page 376: Spi Interface Signals
SPI Interface Signals through their pins. The SPI ports also provide a mechanism to dis- SPIDS able the pin for multimaster systems where the slave SHARC MISO processor does not need to transmit any data to the master. SPI Interface Signals The SPI uses a 4-wire protocol to enable full-duplex serial communica- tion.
Page 377: Spiclk Timing
Serial Peripheral Interface Ports signal is a gated clock that is active only during data transfers, SPICLK and only for the duration of the transferred word. The number of active edges is equal to the number of bits driven on the data lines. The clock rate can be as high as one-fourth the peripheral clock rate.
Page 378: Spi Flag Signals (Spiflg3-0)
SPI Interface Signals SPI CLK CPHASE =0 SPIDS TO SLAVE Figure 6-3. SPICLK Timing SPI Slave Select Input (SPIDS) signal is the serial peripheral interface device select input signal. SPIDS This active low signal is used to enable a processor that is configured as a slave device.
Page 379: Master Out Slave In (Mosi)
Serial Peripheral Interface Ports Master Out Slave In (MOSI) pin is one of the bidirectional I/O data pins. If the MOSI ADSP-21367/8/9 and ADSP-2137x processors are configured as masters, pin becomes a data transmit (output) pin. If the processors are MOSI configured as slaves, the pin becomes a data receive (input) pin.
Page 380: Spi General Operations
SPI General Operations SHARC Processor as SPI Slave 8-bit Host ADSP-213xx MICROCONTROLLER SPI SLAVE DEVICE SPICLK SCLK SPIDS S_SEL MOSI MOSI MISO MISO SHARC Processor as SPI Master ADSP-213xx AD1855 MASTER DEVICE STEREO 96 KHz DAC CCLK SPICLK CLATCH FLAG0 DATA MOSI Figure 6-4.
Page 381: Spi Enable
Serial Peripheral Interface Ports SPI Enable For slaves, the slave-select input acts like a reset for the internal SPI logic. For this reason, the line must be error free. The signal can SPIDS SPIEN also be used as a software reset of the internal SPI logic. An exception to this is the W1C-type (write 1-to-clear) bits in the (SPI status) SPISTATx...
Page 382: Master Mode Operation
SPI General Operations Master Mode Operation When the SPI is configured as a master, configure the SPI port and start transfers using the following steps: 1. Before enabling the SPI port, programs should specify which of the slave-select signals to use, setting one or more of the required SPI flag select bits ( ) in the registers.
Page 383: Slave Mode Operation
Serial Peripheral Interface Ports In master mode, if the transmit buffer remains empty, or the receive buffer remains full, the device operates according to the states of the SENDZ bits in the registers. SPICTLx • If = 1 and the transmit buffer is empty, the device repeatedly SENDZ transmits zeros on the pin.
Page 384: Multimaster Operation
SPI General Operations Once the signal’s falling edge is detected, the slave starts SPIDS sending and receiving data on active edges. SPICLK The reception or transmission continues until is released. SPIDS The slave device continues to receive or transmit with each new active clock edge while the signal is active.
Page 385: Spi Data Transfer Operations
Serial Peripheral Interface Ports immediately reconfigured as a slave. In order to safely transition from one master to the other, the SPI port uses open drain outputs for the data pin drivers. This helps to avoid possible damage from data contention. More information on this topic is described in “Mode Fault Error (MME)”...
Page 386: Spi Operation Using Dma
SPI Data Transfer Operations • When a master is configured with = 00 and the receive buffer TIMOD becomes full the SPI device stalls the SPI clock until all of the data is read from the receive buffer. SPI Operation Using DMA Each SPI has a single DMA channel associated with it that can be config- ured to support either an SPI transmit or a receive, but not both simultaneously.
Page 387: Master Mode Dma Operation
Serial Peripheral Interface Ports SPI transfers. For example, the registers should not be used as a TXSPIx scratch register for temporary data storage. Writing to the registers TXSPIx sets the bit. When the SPI DMA engine is configured for transmitting: 1.
Page 388 SPI Data Transfer Operations 4. For a single DMA, define the parameters of the DMA transfer by writing to the , and registers. For DMA IISPIx IMSPIx CSPIx chaining, also write the chain pointer address to the regis- CPSPIx ters after the other DMA registers. For more information, see “Setting Up and Starting Chained DMA over the SPI”...
Page 389 Serial Peripheral Interface Ports 3. The SPI generates the signal (as specified by SPICLK CPHASE , and other bit settings) and the data is shifted out of SPIBAUD MOSI and in from simultaneously. MISO 4. The SPI continues sending or receiving words until the SPI DMA word count register decrements to 0.
Page 390 SPI Data Transfer Operations Master Transfer Preparation When the processor is enabled as a master, the initiation of a transfer is defined by the two bit fields (bits 1–0) of in the registers. TIMOD SPICTLx Based on these two bits and the status of the interface, a new transfer is started upon either a read of the registers or a write to the RXSPIx...
Page 391: Slave Mode Dma Operation
Serial Peripheral Interface Ports Slave Mode DMA Operation A slave mode DMA transfer occurs when the SPI port is enabled and con- figured in slave mode, and DMA is enabled. When the signal SPIDS transitions to the low state or when the first active edge of SPICLK detected, it triggers the start of a transfer.
Page 392 SPI Data Transfer Operations Slave Transfer Preparation When enabled as a slave, the device prepares for a new transfer according to the function and actions described in Table 6-1. The following steps illustrate the SPI receive or transmit DMA sequence in an SPI slave in response to a master command: 1.
Page 393: Changing Spi Configuration
Serial Peripheral Interface Ports transmit port operates according to the state of the SENDZ in the registers. SPICTLx = 1 and the DMA buffer is empty, the device SENDZ repeatedly transmits zeros on the pin. If = 0 and MISO SENDZ the DMA buffer is empty, it repeatedly transmits the last word it transmitted before the DMA buffer became empty.
Page 394 SPI Data Transfer Operations configuration. In this case, the slave is always selected. Data cor- ruption can be avoided by enabling the slave only after configuring both the master and slave devices. When performing transmit operations with the SPI port, disabling the SPI port prematurely can cause data corruption and/or faulty transmission.
Page 395: Switching From Transmit To Receive Dma
Serial Peripheral Interface Ports 3. Wait for the SPI shift register to finish transferring the last word. This is done when the bit (bit 0 of the registers), SPIF SPISTATx becomes one. 4. Disable the SPI ports by setting the bit (bit 0 of the SPIEN SPICTLx...
Page 396: Switching From Receive To Transmit Dma
SPI Data Transfer Operations 3. Clear all errors by writing to the W1C-type bits in the SPISTATx registers. This ensures that no interrupts occur due to errors from a previous DMA operation. 4. Reconfigure the register to remove the clear condition on SPICTL registers.
Page 397: Dma Error Interrupts
Serial Peripheral Interface Ports Without disabling the SPI: 1. Clear the registers and the buffer status without dis- RXSPIx TXSPIx abling the SPI by ORing 0xc0000 with the present value in the registers. Use the (bit 19) and (bit 18) bits SPICTLx RXFLSH TXFLSH...
Page 398 SPI Data Transfer Operations With disabling the SPI: 1. Disable the SPI port by writing 0x00 to the registers. SPICTLx 2. Disable DMA and clear the FIFO by writing 0x80 to the SPIDMACx registers. This ensures that any data from a previous DMA opera- tion is cleared before configuring a new DMA operation.
Page 399: Dma Chaining
Serial Peripheral Interface Ports 5. Configure DMA by writing to the DMA parameter registers and register. SPIDMACx DMA Chaining For information about chaining, refer to “Setting Up and Starting Chained DMA over the SPI” on page 2-42. SPI Transfer Formats The SPI ports support four different combinations of serial clock phases and polarity.
Page 400 SPI Transfer Formats When = 0, the slave select line, , must be inactive ( CPHASE SPIDS HIGH between each word in the transfer. When = 1, may either CPHASE SPIDS remain active ( ) between successive transfers or be inactive ( HIGH Figure 6-5 shows the SPI transfer protocol for...
Page 401: Beginning And Ending An Spi Transfer
Serial Peripheral Interface Ports CLO CK CYCLE NUMBE R SP ICLK CLKPL=0 (SP I MODE 1 ) SP ICLK CLKPL=1 (SP I MODE 3 ) MOSI MS B FROM MASTE R MISO FROM SLAVE MS B SP IDS TO SLAVE * = UNDEF INED Figure 6-6.
Page 402 SPI Transfer Formats bit defines when the receive buffer can be read. The defines when the transmit buffer can be filled. The end of a single word transfer occurs when the bit is set. This indicates that a new word has been received and latched into the receive buffer, .
Page 403: Spi Word Lengths
Serial Peripheral Interface Ports SPI Word Lengths The processor’s SPI port can transmit and receive the word widths described in the following sections. 8-Bit Word Lengths Programs can use 8-bit word lengths when transmitting or receiving. When transmitting, the SPI port sends out only the lower eight bits of the word written to the SPI buffer.
Page 404: 16-Bit Word Lengths
SPI Word Lengths 16-Bit Word Lengths Programs can use 16-bit word lengths when transmitting or receiving. When transmitting, the SPI port sends out only the lower 16 bits of the word written to the SPI buffer. For example, if the processor executes the following instructions: r0 = 0x12345678 dm(TXSPI) = r0;...
Page 405: Spi Interrupts
Serial Peripheral Interface Ports When the SPI port is transmitting, two eight-bit words are unpacked from one 32-bit word. When receiving, words are packed into one 32-bit word from two eight-bit words. An example of unpacking the data before transmitting: The value (where is any random value and...
Page 406 SPI Interrupts During IOP-driven transfers (DMA), an SPI interrupt is triggered: 3. At the completion of a single DMA transfer, 4. At the completion of a number of DMA sequences (if DMA chain- ing is enabled), 5. When a DMA error has occurred. Again, the register must be initialized properly to enable DMA SPIDMAC...
Page 407: Error Signals And Flags
Serial Peripheral Interface Ports • See “Interrupt Registers” on page B-6 register IRPTL LIRPTL bit descriptions. • See “SPI DMA Configuration Registers (SPIDMAC, SPID- MACB)” on page A-62 register bit descriptions. SPIDMAC Error Signals and Flags This section describes the error signals and flags that determine the cause of transmission errors for an SPI port.
Page 408 Error Signals and Flags The SPI ports are able to respond appropriately to this situation. To enable this feature, set the bit in the register. As soon as this ISSEN SPICTL error is detected, the following actions are taken: 1. The control bit in is cleared, configuring the SPI SPIMS...
Page 409: Transmission Error Bit (Tunf)
Serial Peripheral Interface Ports Transmission Error Bit (TUNF) bit is set in the register when all of the conditions of TUNF SPISTAT transmission are met and there is no new data in the buffer ( TXSPI TXSPI empty). In this case, the transmission contents depend on the state of the bit in the register.
Page 410: Programming Notes
Programming Notes Programming Notes The following sections provide information to help the programmer use the SPI in an ADSP-21367/8/9 and ADSP-2137x processor system. Routing SPI Signals Using The DPI All signals of both SPI ports are routed to the DPI pins using the SRU2. Special considerations must be made when routing the signals, especially with regards to using the correct pin enables that work with the SPI mode being used.
Page 411 Serial Peripheral Interface Ports Listing 6-1. SPI Master Mode Core-Driven Transmit /* SPI Control Registers */ #define SPICTL (0x1000) #define SPIFLG (0x1001) #define SPIBAUD (0x1005) #define TXSPI (0x1003) /*SPICTL bits*/ #define TIMOD1 (0x0001) /* Use TX buffer for transfers */ #define DMISO (0x0020) /* Disable MISO pin */...
Page 412 Programming Examples /* Main code section */ .global _main; .SECTION/PM seg_pmco; _main: /* Init SPI MASTER TX */ r0=0; dm(SPICTL) = r0; dm(SPIFLG) = r0; /* Set up DAG registers */ i4 = tx_buf; m4 = 1; ustat3 = DMISO| /* Disable MISO on transfers */ WL32| /* 32-bit words */...
Page 413 Serial Peripheral Interface Ports Listing 6-2. SPI Master Mode DMA-Driven Transmit /* SPI Control registers #define SPICTL (0x1000) /* SPI Control register #define SPIFLG (0x1001) /* SPI Flag register #define SPIBAUD (0x1005) /* SPI baud setup register /* SPI DMA registers #define IISPI (0x1080) /* Internal DMA address...
Page 414 Programming Examples /* Application code */ .global _main; .segment/pm seg_pmco; _main: /* Init SPI MASTER TX DMA */ r0 = 0; dm(SPICTL) = r0; dm(SPIFLG) = r0; dm(SPIDMAC) = r0; r0 = DS0EN; dm(SPIFLG) = r0; /*use flag0 as spi device select */ ustat3 = src_buf;...
Page 415 Serial Peripheral Interface Ports Listing 6-3. SPI DMA Chaining Example /* SPI Control registers */ #define SPICTL (0x1000) /* SPI Control register #define SPIFLG (0x1001) /* SPI Flag register #define SPIBAUD (0x1005) /* SPI baud setup register /* SPI DMA registers */ #define IISPI (0x1080) /* Internal DMA address...
Page 416 Programming Examples #define CPHASE (0x0400) /* if 1, data's sampled on second (middle) edge of SPICLK cycle*/ /*========================================================*/ .section/dm seg_dmda; /* Destinations for incoming data */ .var dest_bufC[8]; .var dest_bufB[8]; .var dest_bufA[8]; /* Transfer Control Blocks (TCB's) .var first_tcb[] = (0x7FFFF&second_tcb + 3), /* for CPSPI (next tcb) */ LENGTH(dest_bufB),...
Page 417 Serial Peripheral Interface Ports /* setup first DMA in chain */ ustat3 = 8; dm(CSPI) = ustat3; /* count = 8 words ustat3 = 1; dm(IMSPI) = ustat3; /* step size = 1 ustat3 = dest_bufA; dm(IISPI) = ustat3; /* point to dest_bufA */ /* set the SPI baud rate to CCLK/8*64 (650.39KHz @ 333MHz)*/ ustat3 = 0x80;...
Page 418 Programming Examples 6-46 ADSP-21368 SHARC Processor Hardware Reference...
Page 419: Input Data Port
7 INPUT DATA PORT The signal routing unit (SRU) provides paths among both on-chip and off-chip peripherals. To make this feature effective in a real-world system, a low overhead method of making data from various serial and parallel for- mats and routing them back to the main core memory is needed. The input data port (IDP) provides this mechanism for a large number of asynchronous channels.
Page 420 PARALLEL DATA HANDLING PDAP HOLD Serial DATA Parallel SMODE0 Converter Serial DATA Parallel SMODE1 Converter Serial DATA Parallel SMODE2 Converter Serial FIFO DATA Parallel (8x32) SMODE3 Converter DATA IDP_FIFO (8x3) CH. I/O Serial DATA Parallel SMODE4 Converter Serial DATA Parallel SMODE5 Converter Serial...
Page 421: Serial Inputs
Input Data Port DATA [31:12] [19:0] PACKING DAI PINS UNIT [20:1] FIFO SERIAL INPUT PARALLEL DATA ACQUISITION PORT PDAP ENABLE Figure 7-2. Detail of IDP Channel 0 The IDP’s DMA engine implements DMA for all eight channels. Each of the eight channels has a set of DMA parameter registers for directing the data to memory location.
Page 422 Serial Inputs An audio signal that is normally 24 bits wide is contained within the 32-bit word. Four more bits are available for status and formatting data (compliant with the IEC 90958, S/PDIF, and AES3 standards). An addi- tional bit identifies the left/right one-half of the frame. If the data is not in IEC standard format, the serial data can be any data word up to 28 bits wide.
Page 423 Input Data Port Table 7-1. Serial Modes Bit Field Values Mode IDP_SMODEx Left-justified sample pair Left-justified 32 bits. This is a single data and not a left/right channel pair. It can be read as 32-bit data. S-32 bit. This is a single data and not a left/right channel pair.
Page 424 Serial Inputs Channel 20-Bit Spare Bits (11–4) Encoding Audio Set to LOW Bits (2–0) Data (31–12) L/R Encoding Figure 7-6. FIFO Data Packing for Right-Justified (20-Bit Data) Channel 18-Bit Spare Bits (13–4) Encoding Audio Set to LOW Bits (2–0) Data (31–14) L/R Encoding Figure 7-7.
Page 425 Input Data Port Figure 7-10 shows the relationship between frame sync, serial clock, and left-justified sample pair data. SERIAL CLOCK IDPx_CLK_I FRAME SYNC (L/R) IDPx_FS_I LEFT-JUSTIFIED SAMPLE PAI R LSB n-1 MSB n LSB n MSB n SERIAL DATA IDPx_DAT_I FRAME [n-1] F RAME [n] FRAME [n]...
Page 426 Parallel Data Acquisition Port (PDAP) Parallel Data Acquisition Port (PDAP) The input to channel 0 of the IDP is multiplexed, and may be used either in the serial mode, described in “Serial Inputs” on page 7-3, or in a direct parallel input mode.
Page 427: Masking
Input Data Port (bit 26 in the register) selects between the two sets of pins that IDP_PP_CTL may be used as the parallel input port. When is set (= 1), IDP_PORT_SELECT the data bits are read from and the control signals come from DATA31–12 .
Page 428: Packing Mode 11
Parallel Data Acquisition Port (PDAP) MODE 11 1x20-bit RESERVED 12 11 MODE 10 2x16-bit 16 15 MODE 01 tri-word 21 20 10 9 MODE 00 4x8-bit 24 23 16 15 Figure 7-13. Packing Modes in PDAP This mode sends one 32-bit word to FIFO for each input clock cycle—the DMA transfer rate matches the PDAP input clock rate.
Page 429: Packing Mode 10
Input Data Port Packing Mode 01 Mode 01 packs three acquired samples together. Since the resulting 32-bit word is not divisible by three, up to 10 bits are acquired on the first clock edge and up to 11 bits are acquired on each of the second and third clock edges: •...
Page 430: Packing Mode 00
Parallel Data Acquisition Port (PDAP) Clocking Edge Selection Notice that in all four packing modes described, data is read on a clock edge, but the specific edge used (rising or falling) is not indicated. Clock edge selection is configured using the bit (bit 29 of the IDP_PDAP_CLKEDGE register).
Page 431 Input Data Port PDAP_CLK PDAP_DAT[19:12] PDAP_HOLD PDAP_CLK PDAP_DAT[19:12] PDAP_HOLD Figure 7-14. Hold Timing for Four 8-Bit Words to 32 Bits (Mode 00) ADSP-21368 SHARC Processor Hardware Reference 7-13...
Page 432: Pdap Strobe
Parallel Data Acquisition Port (PDAP) PDAP_CLK PDAP_DAT[19:4] PDAP_HOLD PDAP_CLK PDAP_DAT[19:4] PDAP_HOLD Figure 7-15. Hold Timing for Two 16-Bit Words to 32 Bits (Mode 10) As shown in Figure 7-15, are driven by the PDAP_DATA PDAP_HOLD inactive edges of the clock (falling edge in the above figures) and these sig- nals are sampled by the active edge of the clock (rising edge in the above figures).
Page 433: Fifo Control And Status
Input Data Port FIFO Control and Status Several bits can be used to control and monitor FIFO operations: • IDP Enable. The bit (bit 7 of the register) IDP_ENABLE IDP_CTL0 enables the IDP. This is a global control bit. This bit and the corre- sponding IDP channel enable bit ( ) in the IDP_ENx...
Page 434: Fifo To Memory Data Transfer
FIFO to Memory Data Transfer bit (= 1) prevents the core from hanging on reads from an empty IDP_BHD register. Clearing this bit (= 0) causes the core to hang under the IDP_FIFO conditions described previously. bits track the number of words in the FIFO. This 4-bit IDP_FIFOSZ field identifies the number of valid data samples in the IDP FIFO.
Page 435: Idp Transfers Using The Core
Input Data Port A mechanism is provided to generate an interrupt when more than a specified number of words are in the FIFO. This interrupt signals the core to read the register. IDP_FIFO This method of moving data from the IDP FIFO is described in the next section, “IDP Transfers Using the Core”.
Page 436: Starting An Interrupt-Driven Transfer
FIFO to Memory Data Transfer Starting an Interrupt-Driven Transfer To start an interrupt-driven transfer: 1. Clear and halt FIFO by setting (= 1) and clearing (= 0) the bit (bit 7 in the register). IDP_ENABLE IDP_CTL0 2. Set the required values for: •...
Page 437 Input Data Port 6. Set the bit (bit 8 of the register) IDP_FIFO_GTN_INT DAI_IRPTL_RE and set the corresponding bit in the register HIGH DAI_IRPTL_FE to low to unmask the interrupt. Set bit 8 of the reg- DAI_IRPTL_PRI ister ( ) as needed to generate a high priority or IDP_FIFO_GTN_INT low priority core interrupt when the number of words in the FIFO is greater than the value of N set.
Page 438: Idp Transfers Using Dma
FIFO to Memory Data Transfer • When the data transfer to the core is 32 bits, as in the case of PDAP data or I S and left-justified modes with 32 bits, there is no channel information in the data. Therefore, PDAP or I S and left-justified 32 bit modes can not be used with other channels in the core/interrupt-driven mode.
Page 439 Input Data Port • Index registers ( IDP_DMA_Ix • Modifier registers ( IDP_DMA_Mx • Counter registers ( IDP_DMA_Cx For each of these registers, x is 0 to 7. Refer to “DMA Channel Parameter Registers” on page 7-27. 3. Keep the clock and the frame sync input of the serial inputs and/or the PDAP connected to low, by setting proper values in the , and registers.
Page 440: Ping-Pong Dma
FIFO to Memory Data Transfer 6. Enable DMA, IDP, and PDAP (if required) by setting each of the following bits = 1: • bit (bit 5 of the register) IDP_DMA_EN IDP_CTL0 • bits in register to enable the DMA of IDP_DMA_ENx IDP_CTL1 the selected channel...
Page 441 Input Data Port Starting Ping-Pong DMA Transfers To start a ping-pong DMA transfer from the FIFO to memory: 1. Clear and halt the FIFO by setting (= 1) and then clearing (= 0) the bit (bit 7 in the register). IDP_ENABLE IDP_CTL0 2.
Page 442 FIFO to Memory Data Transfer • bits in the register to specify IDP_Pxx_PDAPMASK IDP_PP_CTL the input mask, if the PDAP is used. For more information, see “Parallel Data Acquisition Port Control Register (IDP_PP_CTL)” on page A-74. • bits in the register to specify IDP_PORT_SELECT IDP_PP_CTL...
Page 443: Dma Transfer Notes
Input Data Port DMA Transfer Notes The following items provide general information about DMA transfers. • A DMA can be interrupted by changing the bit in the IDP_DMA_EN register. None of the other control settings (except for IDP_CTL0 bit) should be changed. Clearing the IDP_ENABLE IDP_DMA_EN bit (= 0) does not affect the data in the FIFO, it only stops DMA...
Page 444 FIFO to Memory Data Transfer When an overflow occurs, incoming data from IDP channels is not accepted into the FIFO, and data values are lost. New data is only accepted once space is again created in the FIFO. • For serial input channels, data is received in an alternating fashion from left and right channels.
Page 445: Dma Channel Parameter Registers
Input Data Port register. Reading these DAI shadow registers DAI_IRPTL_L ) does not destroy the con- DAI_IRPTL_H_SH DAI_IRPTL_L_SH tents of the registers. DAI_IRPTL_H DAI_IRPTL_L • The IDP can run both simple and ping-pong DMAs in different channels. When running simple DMA, initialize the corresponding , and registers.
Page 446: Idp (Dai) Interrupt Service Routines For Dmas
FIFO to Memory Data Transfer The IDP DMA parameter registers have these functions: • Internal index registers ( IDP_DMA_Ix IDP_DMA_AIx IDP_DMA_BIx Index registers provide an internal memory address, acting as a pointer to the next internal memory location where data is to be written.
Page 447 Input Data Port The following steps describe how an IDP ISR is handled. 1. When the DMA for a channel completes, an interrupt is generated and program control jumps to the ISR. 2. The program clears the bit in the register IDP_DMA_EN IDP_CTL0...
Page 448: Fifo Overflow
FIFO to Memory Data Transfer 5. Read the registers to see if more inter- DAI_IRPTL_L DAI_IRPTL_H rupts have been generated. • If the value(s) are not zero, repeat step 4. • If the value(s) are zero, continue to step 6. 6.
Page 449: Input Data Port Programming Example
Input Data Port Input Data Port Programming Example Listing 7-1 shows a data transfer using an interrupt service routine (ISR). The transfer takes place through the digital applications interface (DAI). This code implements the algorithm outlined in “FIFO to Memory Data Transfer”...
Page 450 Input Data Port Programming Example dm(IDP_CTL0) = r0; /*************************************************/ /* Connect the clock, data and frame sync of IDP */ channel 0 to DAI pin buffers 10, 11 and 12. */ /*************************************************/ Connect IDP0_CLK_I to DAI_PB10_O (SRU_CLK1[19:15] = 01001) Connect IDP0_DAT_I to DAI_PB11_O (SRU_DAT3[11:6] = 001010) Connect IDP0_FS_I to DAI_PB12_O (SRU_FS1[19:15] = 01011)
Page 451 Input Data Port r0 = dm(IDP_CTL0); /* N_SET = 6 */ r0 = BSET r0 BY 0; r0 = BSET r0 BY 1; r0 = BSET r0 BY 2; r0 = BCLR r0 BY 3; dm(IDP_CTL0) = r0; r0 = dm(DAI_IRPTL_RE); /* Unmask for rising edge */ r0 = BSET r0 BY IDP_FIFO_GTN_INT;...
Page 452 Input Data Port Programming Example 7-34 ADSP-21368 SHARC Processor Hardware Reference...
Page 453: Pulse Width Modulation
8 PULSE WIDTH MODULATION Pulse width modulation (PWM) is a technique for controlling analog cir- cuits with a microprocessor’s digital outputs. PWM is employed in a wide variety of applications, ranging from measurement to communications to power control and conversion. One of the advantages of PWM is that the signal remains digital all the way from the processor to the controlled system;...
Page 454: Edge-Aligned Mode
PWM Implementation PWMGSTAT GLOBAL REGISTERS PWMGCTL PWMSTAT CONFIGURATION DUTY CYCLE REGISTERS REGISTERS PWMCHA PWMTM PWMDT PWMCHB PWMCTRL PWMSEG PHB BUS PWMSEG PWM_AH Gate Output Dead PWM_AL Drive Control Time Timing PWM_BH Unit Unit Control Unit PWM_BL Unit SYNC SYNC SR RESET Interrupt Control Unit PWM_SYNC_IRQ...
Page 455: Center-Aligned Mode
Pulse Width Modulation of period, it is equal to period ÷ 2 (rounded up). Therefore, for a duty value programmed in two’s-complement, the PWM pulse width is given ÷ Width period duty To generate constant logic high on PWM output, program the duty regis- ter with the value ≥...
Page 456 PWM Implementation Center-aligned, paired mode. Generates complementary signals on two outputs. Center-aligned, non-paired mode. Generates complementary signals on independent signals. In paired mode, the two’s-complement integer value in the 16-bit read/write duty cycle registers, ( ), control the duty cycles PWMAx PWMBx of the four PWM output signals on the...
Page 457: Switching Frequencies
Pulse Width Modulation registers of that group. The period completion status bits in the PWM_GSTAT register are set independently of the corresponding bit, but PWM_IRQEN interrupt generation depends on the bit. PWM_IRQEN Switching Frequencies The 16-bit read/write PWM period registers, ( ), control the PWMPERIOD3–0 PWM switching frequency.
Page 458: Dead Time
PWM Implementation The largest value that can be written to the 16-bit register is PWMPERIODx 0xFFFF = 65,535 which corresponds to a minimum PWM switching fre- quency of: × ----------------------- - 763Hz × ) min 65535 Also note that values of 0 and 1 are not defined and should not PWMPERIOD be used when the PWM outputs or PWM sync is enabled.
Page 459: Duty Cycles
Pulse Width Modulation maximum value they can contain is 0x3FF (= 1023) which corresponds to a maximum programmed dead time of: 9 – × × × × × T d max 1023 1023 20.5μs PCLK This equates to an f rate of 100 MHz.
Page 460: Duty Cycles And Dead Time
PWM Implementation Duty Cycles and Dead Time A typical pair of PWM outputs (in this case for ) from pwm_ah pwm_al the timing unit are shown in Figure 8-2 for operation in single-update mode. All illustrated time values indicate the integer value in the associ- ated register and can be converted to time by simply multiplying by the fundamental time increment, (t ) and comparing this to the...
Page 461 Pulse Width Modulation PWMPERIOD PWMPERIOD PWMPERI OD count PWMCHA PWMCHA pwm_ ah pwm_a l PWMSYNCWT + 1 2xPWMDT 2xPWMDT pw m_pwm sync_out PWMP HASE PWMPERIOD PWMPERIOD Figure 8-2. Center-Aligned Paired PWM in Single-Update Mode, Low Polarity The resulting on-times (active low) of the PWM signals over the full PWM period (two half periods) produced by the PWM timing unit and illustrated in Figure 8-3 on page 8-11...
Page 462 PWM Implementation The range of T × × – PWMPERIOD t PCLK and the corresponding duty cycles are: – PWMCHA PWMDT -------------------------------------------------- - ------- - -- - PWMPERIOD – PWMCHA PWMDT -------------------------------------------------- - ------ - -- - PWMPERIOD The minimum permissible value of T and T is zero, which corre- sponds to a 0% duty cycle, and the maximum value is T...
Page 463 Pulse Width Modulation PWMPERIOD 1 PWMPERIOD 1 PWMPERI OD 2 PWMPERIOD 2 count PWMCHA 1 PWMCHA 2 pwm_ ah pwm_a l 2xPWMDT 1 2xPWMDT 2 pw m_pwm sync_out PWMSYNCWT 1 + 1 PWMSYNCWT 2 + 1 PWMP HASE PWMPERIOD 1 PWMPERIOD 2 Figure 8-3.
Page 464: Over Modulation
PWM Implementation where subscript 1 refers to the value of that register during the first half cycle and subscript 2 refers to the value during the second half cycle. The corresponding duty cycles are: – – PWMCHA PWMCHA PWMDT PWMDT --------- - -- - ---------------------------------------------------------------------------------------------------------------------------------------...
Page 465 Pulse Width Modulation • Full on. The PWM for any pair of PWM signals is said to operate in full on when the desired high side output of the three-phase tim- ing unit is in the on state (low) between successive rising PWMSYNC edges.
Page 466 PWM Implementation Figure 8-4 illustrates two examples of such transitions. In Figure 8-4 (A), when transitioning from normal modulation to full on at the half cycle boundary in double-update mode, no special action is needed. However, Figure 8-4 (B), when transitioning into full off at the same boundary, an additional emergency dead time is necessary.
Page 467: Update Modes
Pulse Width Modulation Update Modes Update modes determine the frequency with which the waveforms are sampled. Single Update In this mode, duty cycle values are programmable only once per PWM period, so that the resultant PWM patterns are symmetrical about the midpoint of the PWM period.
Page 468: Pwm Pins And Signals
PWM Implementation PWM Pins and Signals The entire PWM module has four groups of four PWM outputs, for a total of 16 PWM outputs. The modules are controlled by the PWM_AH pins which produce high side drive signals and the PWM_BH PWM_AL pins which produce low side drive signals.
Page 469: Pwm Accuracy
Pulse Width Modulation unit so that the signal ultimately appears at the pin. The corresponding low side output of the timing unit is also diverted to the complementary high side output of the output control unit so that the signal appears at pin.
Page 470: Pwm Registers
PWM Registers Table 8-1. PWM Accuracy in Single and Double-Update Modes (Cont’d) Resolution (bits) Single-Update Mode Double-Update Mode PWM Frequency (kHz) PWM Frequency (kHz) 24.4 48.8 12.2 24.4 12.2 3.05 PWM Registers The registers described below control the operation and provide the status of pulse width modulation on the ADSP-21367/8/9 and ADSP-2137x processors.
Page 471: Duty Cycles
Pulse Width Modulation • PWM period registers. The registers are 16-bit, PWMPERIOD3–0 read/write registers that control the period of the four PWM groups. • PWM dead time registers. The registers are 16-bit, PWMDT3–0 read/write registers that are used to set the switching dead time. •...
Page 472: Output Enable
PWM Registers • The two’s-complement integer value in the registers controls PWMAx the duty cycle of the signals on the pins. pwm_ah pwm_al • The two’s-complement integer value in the registers control PWMBx the duty cycle of the signals on pins.
Page 473: Programming Example
Pulse Width Modulation Programming Example The following program shows the four steps used to configure a PWM module. Listing 8-1. Generic PWM Configuration Example #include "def21369.h" .global start; /* define for PWM frequency used in PWMPERIOD0 */ #define fPWM 0x1388; /* 200MHz/2(20kHz) =>...
Page 474 Programming Example /* 1. Configure frequency */ ustat3=fPWM; /* fPCLK/2xfPWM */ dm(PWMPERIOD0)=ustat3; /* PWM Period Register for switching frequency (unsigned integer) */ /* 2. Configure duty cycles Width=[period/2] + duty program in the two’s-complement of the high side width for individual con- trol this only programs AH signal.
Page 475 Pulse Width Modulation /* PWM enables */ PWM_enables: ustat3=dm(SYSCTL); /* System Control Register */ bit set ustat3 PWM0EN | PPFLGS; dm(SYSCTL)=ustat3; /* Selects AD11–8 in PWM0 mode instead of PP mode */ ustat3=dm(PWMSEG0); /* PWM Output Enable. Should probably be changed to PWM Output Disable since you write it to disable it.
Page 476 Programming Example 8-24 ADSP-21368 SHARC Processor Hardware Reference...
Page 477 9 S/PDIF TRANSMITTER/RECEIVER S/PDIF (Sony/Philips Digital Interface) is a standard audio data transfer format that allows the transfer of digital audio signals from one device to another without having to be converted to an analog signal. The ADSP-21367/8/9 and ADSP-2137x processors have AES3-compliant S/PDIF receivers/transmitters that allow programs to interface to other S/PDIF devices.
Page 478: Aes3/Spdif Stream Format
AES3/SPDIF Stream Format • In regards to handling channel status information, the SPDIF transmitter can operate in standalone and full serial modes. In stan- dalone mode, channel status bits, user bits, and validity bits are taken from the corresponding buffers or control register. In full serial mode, all these bits are transferred with data bits from the pin.
Page 479: Subframe Format
S/PDIF Transmitter/Receiver A frame is uniquely composed of two subframes. The first subframe nor- mally starts with preamble X. However, the preamble changes to preamble Z once every 192 frames. This defines the block of frames structure used to organize the channel status information. The second subframe always starts with preamble Y.
Page 480 AES3/SPDIF Stream Format 24-BIT AUDIO WORD 20-BIT AUDIO WORD Figure 9-2. Subframe Format and the for channel 2) bit is set in the VALIDITY_A VALIDITY_B register. This bit is also set if the corresponding bit SPDIF_TX_CTL given with the sample is set. 2.
Page 481: Channel Coding
S/PDIF Transmitter/Receiver Channel status information is organized in 192-bit blocks, subdi- vided into 24 bytes. The first bit of each block is carried in the frame with preamble Z. For convenience, the first five bytes of the channel status may be written all at once to control registers for both channels A and B , and ).
Page 482: Preambles
AES3/SPDIF Stream Format Each bit to be transmitted is represented by a symbol comprising two con- secutive binary states. The first state of a symbol is always different from the second state of the previous symbol. The second state of the symbol is identical to the first if the bit to be transmitted is logic 0.
Page 483: S/Pdif Transmitter
S/PDIF Transmitter/Receiver A set of three preambles, shown in Table 9-1, are used. These preambles are transmitted in the time allocated to four time slots at the start of each subframe (time slots 0 to 3) and are represented by eight successive states. The first state of the preamble is always different from the second state of the previous symbol (representing the parity bit).
Page 484 S/PDIF Transmitter The S/PDIF transmitter output may be routed to an output pin through SRU1 and then routed to another S/PDIF receiver or to components for off-board connections to other S/PDIF receivers. The output is also avail- able to the S/PDIF receiver for loop-back testing through SRU1. TRANSMITTER CONTROL REGISTER...
Page 485: Channel Status
S/PDIF Transmitter/Receiver In SCDF mode, the transmitter sends successive audio samples of the same signal across both subframes, instead of channel A and B. This mode also allows programs to select which channel is sent when using bits in the S/PDIF transmit control register.
Page 486: Sru1 Signals For The S/Pdif Transmitter
S/PDIF Transmitter SRU1 Signals for the S/PDIF Transmitter To use the transmitter, route the five required inputs using SRU1 as described below. Also, use SRU1 to connect the two outputs, bi-phase encoded output, and block start to the desired DAI (digital audio inter- face) pin.
Page 487 S/PDIF Transmitter/Receiver DIT_HFCLK_I is the oversampling clock. This clock is divided down according to the bit in the transmitter control register to gener- FREQMULT ate the bi-phase clock. It can also be selected from various sources since it is routed through SRU1. The input to the S/PDIF transmitter is TX_CLK controlled by the 5-bit clock routing (SRU1 group A) register field...
Page 488: Modes Of Operation
S/PDIF Transmitter S/PDIF Transmitter Registers The SPDIF transmitter contains registers that are used to enable/disable the transmitter, to manage its operation, and to report status. The regis- ters are described below. • DITCTL is the S/PDIF transmit control register. This 32-bit read/write register is located at address 0x24A0.
Page 489: Standalone Mode
S/PDIF Transmitter/Receiver Standalone Mode This mode is selected by setting bit 9 in the register. In this mode, DITCTL the block start bit (indicating start of a frame) is generated internally. The channel status bits come from the channel status buffer registers ( DITCHA- ).
Page 490: Structure Of The Serial Input Data
S/PDIF Transmitter Structure of the Serial Input Data Figure 9-5 shows the format of data that is sent to the S/PDIF transmitter using a 24-bit I S interface. The upper 24 bits (bits 8 through 31) contain the audio data. Bits 3–7 are used to transmit status information and to generate preambles and or headers.
Page 491 S/PDIF Transmitter/Receiver Bits 27–8: 20-Bit Audio Data BITS 3–0 Validity Bit User Data Channel Status Block Status Padding (zero) Figure 9-7. Data Packing for Right-Justified Format, 20 Bits Bits 27–10: 18-Bit Audio Data BITS 5–0 Validity Bit User Data Channel Status Block Status Padding (zero) Figure 9-8.
Page 492: S/Pdif Receiver
S/PDIF Receiver S/PDIF Receiver The S/PDIF receiver is compliant with all common serial digital audio interface standards including IEC-60958, IEC-61937, AES3, and AES11. These standards define a group of protocols that are commonly associated with the S/PDIF interface standard defined by AES3, which was devel- oped and is maintained by the Audio Engineering Society.
Page 493: S/Pdif Receiver Registers
S/PDIF Transmitter/Receiver The receiver also detects errors in the S/PDIF stream. These error bits are stored in the status register, which can be read by the core. Optionally, an interrupt may be generated to notify the core on error conditions. The extracted serial data is transmitted on the data pin in I S format.
Page 494: Sru1 Receiver Signals
S/PDIF Receiver SRU1 Receiver Signals The bi-phase encoded data and the external PLL clock inputs to the receiver are routed through the signal routing unit (SRU1). The extracted clock, frame sync, and data are also routed through SRU1. The SRU1 inputs to the S/PDIF receiver are configured through the fol- lowing signals.
Page 495: Phase-Locked Loop
PLL. There are various performance characteristics to consider when configuring for analog PLL mode, and more information can be found on the Analog Devices Web site. Channel Status Decoding The S/PDIF receiver processes compressed as well as non-linear audio data according to the supported standards.
Page 496: Compressed Or Non-Linear Audio Data
Channel Status Decoding Compressed or Non-Linear Audio Data The AES3/SPDIF receiver is required to detect compressed or non-linear audio data according to the AES3, IEC60958, and IEC61937 standards. Bit 1 of byte 0 in the register indicates whether the audio data DIR_B0CHAN is linear PCM, (bit 1 = 0), or non-PCM audio, (bit 1 = 1).
Page 497: Emphasized Audio Data
S/PDIF Transmitter/Receiver can be detected by adding the sync detection logic in software by using a software counter to check for the DTS header every 2048 and 4096 frames respectively. Emphasized Audio Data The receiver must indicate to the program whether the received audio data is emphasized using the channel status bits as detailed below.
Page 498: Error Handling
Error Handling Bits 0–3 of channel status byte 1 are decoded by the receiver to determine one of the following: • 0111 = single-channel, double-frequency mode • 1000 = single-channel, double-frequency mode – stereo left • 1001 = single-channel, double-frequency mode – stereo right Error Handling The following five types of errors can occur in the receiver and are reported on the error flag bits.
Page 499 S/PDIF Transmitter/Receiver audio sample and slowly and linearly decrementing it to zero, over a period of 4096 frames. During this time, the PLL three-states the charge pump until the soft mute has been completed. If non-linear PCM audio data is in the AES3/SPDIF stream when the bit is asserted, the NOSTREAM receiver sends out zeros after the last valid sample.
Page 500: Interrupts
Interrupts Interrupts The following error/status bits can be used to interrupt the processor core. • The bits can DIR_LOCK DIR_VALID DIR_NOSTREAM DIR_NOAUDIO generate interrupts. Parity errors and bi-phase errors are ORed together to form a interrupt. Whenever PARITY_BIPHASE_ERROR there is a change in channel status information, a interrupt occurs.
Page 501: Sru1 Programming For Input And Output Streams
S/PDIF Transmitter/Receiver SRU1 Programming for Input and Output Streams Signal routing unit 1 (SRU1) is used to connect the S/PDIF transmitter bi-phase data out to the output pins or to the S/PDIF receiver. The serial data input and the over sampling clock input also needs to be routed through SRU1.
Page 502: Sru1 Programming
DAI Programming Examples SRU1 Programming The SRU1 needs to be programmed in order to connect the S/PDIF receiver to the output pins or any other peripherals and also for the input bi-phase stream. Program the corresponding SRU1 registers to connect the above outputs to the required destination.
Page 503: Interrupted Data Streams On The Receiver
S/PDIF Transmitter/Receiver Interrupted Data Streams on the Receiver When using the SPDIF receiver with data streams that are likely to be interrupted, (in other words unplugged and reconnected), it is necessary to take some extra steps to ensure that the SPDIF receiver’s digital PLL will re lock to the stream.
Page 504 DAI Programming Examples /* Enable Hi-priority DAI interrupt */ dm(DAI_IRPTL_PRI) = ustat1; /* If more than 1 DAI interrupt is being used, it is neces- sary to determine which interrupt occurred here */ /* Interrupt Service Routine for the DAI Hi-Priority Inter- rupt.
Page 505: Asynchronous Sample Rate Converter
S/PDIF receiver. The SRC contains four blocks (SRC0–3). It also is the same core that is used in the Analog Devices AD1896 192 kHz Stereo Asynchronous Sam- ple Rate Converter. The top-level block diagram of the SRC module is...
Page 506: Theory Of Operation
Theory of Operation multiplexing (TDM) mode for daisy-chaining multiple SRCs to a proces- sor. The serial output data is dithered down to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data is selected. Theory of Operation The SRC sample rate converts the data from the serial input port to the sample rate of the serial output port.
Page 507 Asynchronous Sample Rate Converter Normally, the signal is connected to the signal. The MUTE_OUT MUTE_IN signal is used to softly mute the SRC upon assertion and softly MUTE_IN stop muting the SRC when it is deasserted. The sample rate ratio circuit is used to scale the filter length of the FIR fil- ter for decimation.
Page 508: Conceptual Model
Theory of Operation ZERO-ORDER HOLD f S_I N = 1/T1 f S_OUT = 1/T2 ORIGINAL SIGNAL SAMPLED AT f S_I N SIN(X)/X OF ZERO-ORDER HOLD SPECTRUM OF ZERO-ORDER HOLD OUTPUT SPECTRUM OF f S_OUT SAMPLING 2 × f S_OUT f S_OUT FREQUENCY RESPO NSE OF f S_OUT CONVOLVED WITH ZERO-ORDER HOLD SPECTRUM Figure 10-1.
Page 509 Asynchronous Sample Rate Converter INTERPOLATE LOW-PASS ZERO-ORDER BY N FILTER HOLD f S_IN f S_OUT TIME DOMAIN OF f S_IN SAMPLES TIME DOMAIN OUTPUT OF THE LOW-PASS FILTER TIME DOMAIN OF f S_OUT RESAMPLING TIME DOMAIN OF THE Z ERO-ORDER HOLD OUTPUT Figure 10-2.
Page 510 Theory of Operation F is the frequency of the worst-case image which is: S_IN × ± ----------- - S_IN and f S_INTERP × S_IN The following worst-case images would appear for f = 192 kHz: S_IN Image at f – 96 kHz = –125.1 dB S_INTERP Image at f + 96 kHz = –125.1 dB...
Page 511: Hardware Model
Asynchronous Sample Rate Converter Hardware Model The output rate of the low-pass filter of Figure 10-2 is the interpolation × 192 kHz = 201.3 GHz. Sampling at a rate of 201.3 GHz is rate, 2 clearly impractical, not to mention the number of taps required to calcu- late each interpolated sample.
Page 512: Sample Rate Converter Architecture
Sample Rate Converter Architecture anti-aliasing filter, the coefficients are dynamically altered and the length of the convolution is increased by a factor of (f ). This tech- S_IN S_OUT nique is supported by the Fourier transform property that if f(t) is F(ω), then f(k ×...
Page 513 Asynchronous Sample Rate Converter LRCLK_I SCLK_I DE-EMPHASIS FILTER SDATA_I SERIAL SAMPLE INPUT RATE SMODE_IN2-0 MUTE_OUT PORT CONVERTER HARD_MUTE_IN MUTE_IN DE-EMPHASIS1-0 SRC_RATIO14-0 TDM_OUT MCLK SMODE_OUT1-0 SDATA_O WLENGTH_OUT1-0 LRCLK_O SERIAL OUTPUT 21BIT_DITHER SCLK_O PORT TDM_IN MATCHED_PHASED_MODE Figure 10-4. Sample Rate Converter Block Diagram The FIFO receives the left and right input data and adjusts the amplitude of the data for both the soft muting of the SRC and the scaling of the input data by the sample rate ratio before storing the samples in RAM.
Page 514 Sample Rate Converter Architecture RIGHT DATA IN ROM A HIGH FIFO LEFT DATA IN ORDER ROM B INTERP ROM C ROM D f S_IN DIGITAL FIR FILTER SERVO LOOP COUNTER L/R DATA OUT SAMPLE RATE RATIO f S_ IN SAMPLE RATE RATIO f S_OUT EXTERNAL...
Page 515 Asynchronous Sample Rate Converter The digital-servo loop is implemented with a multi-rate filter. To settle the digital-servo loop filter quickly at startup or at a change in the sample rate, a fast mode has been added to the filter. When the digital-servo loop starts up or the sample rate is changed, the digital-servo loop kicks into fast mode to adjust and settle on the new sample rate.
Page 516: Group Delay
SRC Operation differences in their ratios from 0 to 4 f period counts. The S_OUT ratio adjusts the filter length of the SRC, which corresponds S_OUT S_IN directly with the group delay. Thus, the magnitude in the phase difference depends upon the resolution of the f and f counters.
Page 517: Enabling The Src
Asynchronous Sample Rate Converter Enabling the SRC When the bit (bit 31 in the SRC control registers) is set SRCx_ENABLE (= 1), the SRC begins its initialization routine where all locations in the FIFO are initialized to zero, is cleared, and any output pins are MUTE_OUT enabled.
Page 518 SRC Operation Table 10-1. Serial Data Input Port Mode SRCx_SMODE_0:2 Interface Format Left-justified RESERVED Right-justified, 16 bits Right-justified, 18 bits Right-justified, 20 bits Right-justified, 24 bits Table 10-3. When the output word width is less than 24 bits, dither is added to the truncated bits.
Page 519: Time-Division Multiplex (Tdm) Output Mode
Asynchronous Sample Rate Converter Table 10-3. Word Width SRCx_LENOUT_0:1 Interface Format 24 bits 20 bits 18 bits 16 bits Time-Division Multiplex (TDM) Output Mode In TDM output mode, several SRCs can be daisy-chained together and connected to the serial input port of an ADSP-21367/8/9 and ADSP-2137x processor or other processor (Figure 10-6).
Page 520: Tdm Input Mode
SRC Operation TDM Input Mode In TDM input mode, several SRCs can be daisy-chained together and connected to the serial input port of an ADSP-21367/8/9 and ADSP-2137x processor or other processor (Figure 10-7). The SRC con- tains a 64-bit parallel load shift register. When the pulse arrives, LRCLK_I each SRC parallel loads its left and right data into the 64-bit shift register.
Page 521 Asynchronous Sample Rate Converter Figure 10-8. The master device can have both its serial ports in slave mode as depicted, or either one in master mode. The slave SRCs must have their bits set to 1, respectively. The MATASE_2 LRCLK_I LRCLK_O signals may be asynchronous with respect to each other in this mode.
Page 522: Bypass Mode
SRC Operation MATCHED-PHASE AUDIO DATA RIGHT MATCHED-PHASE AUDIO DATA LEFT CHANNEL, CHANNEL, 24 BITS DATA, 8 BITS 24 BITS DATA, 8 BITS Left-Justified, I S, and TDM Mode MATCHED-PHASE AUDIO DATA LEFT MATCHED-PHASE AUDIO DATA RIGHT CHANNEL, 16 BITS - 24 BITS CHANNEL, 16 BITS - 24 BITS DATA, 8 BITS DATA, 8 BITS...
Page 523: Mute Control
Asynchronous Sample Rate Converter • 10 – 44.1 kHz sample rate de-emphasis filter • 11 – 48 kHz sample rate de-emphasis filter After the audio data is passed from the de-emphasis filter to the SRC, the SRC converts the audio data from the input sample rate to the output sample rate.
Page 524: Soft Mute
SRC Operation Muting can also be controlled in software using the bits MUTE ) in the SRC control SRCx_SOFTMUTE SRCx_HARD_MUTE SRCx_AUTO_MUTE register ( ) as described below. For more information, see “SRC SRCCTL Registers” on page 10-21. Soft Mute When the bit in the register is set, the sig-...
Page 525: Src Registers
Asynchronous Sample Rate Converter SRC Registers The SRC uses five 32-bit registers to configure and operate the SRC module. • SRCCTL0, SRC control 0. This read/write register is used to con- trol the operating modes, filters, and data formats used in the SRC0 and SRC1 modules.
Page 526: Programming The Src Module
Programming the SRC Module Programming the SRC Module Use the following guidelines when developing programs that include the SRC module. SRC Control Register Programming Initially, programs configure the SRC control registers SRCCTL0 . The register contains control parameters for the SRC0 SRCCTL1 SRCCTL0 and SRC1 modules and the...
Page 527: Src Mute-Out Interrupt
Asynchronous Sample Rate Converter For information on using the SRU, see “Making Connections in the SRUs” on page 4-15, and “DAI/SRU1 Connection Groups” on page 4-18. SRC Mute-Out Interrupt Once the SRC is locked (after 4K input samples), the corresponding bit in the register is set.
Page 528 Programming the SRC Module In multichannel, or matched-phase modes, the TDM signals must also be connected. (See Table 10-1 on page 10-14 Table 10-2 on page 10-14.) 2. Initialize the register to enable the SRCs. SRCCTLx 10-24 ADSP-21368 SHARC Processor Hardware Reference...
Page 529: 11 Uart Port Controller
11 UART PORT CONTROLLER The universal asynchronous receiver/transmitter (UART) is a full-duplex peripheral compatible with the PC-style, industry-standard UART. The UART converts data between serial and parallel formats. The serial format follows an asynchronous protocol that supports various word lengths, stop bits, and parity generation options.
Page 530: Serial Communications
Serial Communications Serial Communications The UART follows an asynchronous serial communication protocol with these options: • 5 – 8 data bits • 1 or 2 stop bits • None, even, or odd parity /(16 × divisor), where • Baud rate = is the system clock fre- PCLK PCLK...
Page 531: Uart Control And Status Registers
UART Port Controller UART Control and Status Registers The processor provides a set of PC-style, industry-standard control and status registers for each UART. These memory-mapped registers (MMRs) are byte-wide registers that are mapped as half-words with the most signif- icant byte zero-filled. Consistent with industry-standard interfaces, multiple registers are mapped to the same address location.
Page 532: Uartxlsr Register
UART Control and Status Registers UARTxLSR Register The UART line status register ( ) contains UART status informa- UARTxLSR tion as shown in Figure A-49 on page A-120. The break interrupt ( ), overrun error ( ), parity error UARTBI UARTOE ), and framing error ( ) bits are cleared when the UART line...
Page 533: Uartxrbr Register
UART Port Controller This 32-bit write only register uses only 18-bits. The other bits are filled with zeros during writes. In no-pack mode (default), only the lower byte is used—all other bits are zero filled. However in pack mode, both the high and low bytes are used (Figure 11-2).
Page 534 UART Control and Status Registers ZERO-FILLED RX9D1 HIGHER BYTE ZERO-FILLED RX9D0 LOWER BYTE Figure 11-3. Receive Buffer Register (Packing Enabled) A sampling clock equal to 16 times the baud rate samples the data as close to the midpoint of the bit as possible. Because the internal sample clock may not exactly match the asynchronous receive data rate, the sampling point drifts from the center of each bit.
Page 535: Uartxier Register
UART Port Controller UARTxIER Register The UART interrupt enable registers ( ) are used to enable UARTxIER requests for system handling of empty or full states of UART data regis- ters. Unless polling is used as a means of action, the and/or UARTRBFIE bits in this register are normally set.
Page 536 UART Control and Status Registers programmed through the register using the code select value for the PICR UART receive interrupt (0x13 for UART0 interrupt and 0x14 for UART1 receive interrupt). Similar to I/O mode, both the transmit and receive interrupts are mapped to the receive interrupt. Then the register UARTxIER can be used to select the transmit or receive interrupt respectively for I/O...
Page 537: Uartxiir Register
UART Port Controller For information on using the UART for DMA transfers, see “UART DMA” on page 2-44, “DAI/DPI Interrupt Controller” on page 4-65, and “Peripheral Interrupt Priority Control Registers” on page A-164. Even though the UART has two interrupts for receive and trans- mit, in I/O mode, all interrupts are grouped as a single receive interrupt.
Page 538 UART Control and Status Registers interrupt priority using the peripheral interrupt priority control registers. For more information, see “Peripheral Interrupt Priority Control Regis- ters” on page A-164. Table 11-1. IIR Register in I/O Mode Bit Status NINT Interrupt Interrupt Type Cleared When...
Page 539: Uartxdll And Uartxdlh Registers
UART Port Controller If software stops transmission, it must read the register to reset UARTxIIR the interrupt request. As long as the register reads 0x04 or 0x06 UARTxIIR (indicating that another interrupt of higher priority is pending), the UAR- empty latch cannot be cleared by reading the register.
Page 540: Uartxscr Register
UART Control and Status Registers The 16-bit divisor formed by the registers UARTxDLH UARTxDLL resets to 0x0001, resulting in the highest possible clock frequency by default. If the UART is not used, disabling the UART clock saves power (see bits 13 and 14 in the “Power Management Con- trol Register (PMCTL)”...
Page 541: Uartxmode Register
UART Port Controller For information on UART DMA registers, see “UART DMA” on page 2-44. UARTxMODE Register The UART mode register controls miscellaneous settings such as packing and address detection. For more information, see “Mode Registers (UAR- TxMODE)” on page A-126. I/O Mode In I/O mode, data is moved to and from the UART by the processor core.
Page 542 I/O Mode Software can write up to two words into the register before UARTxTHR enabling the UART clock. As soon as the UART DMA engine is enabled, those two words are sent. Alternatively, UART writes and reads can be accomplished by interrupt service routines (ISRs).
Page 543: Packing Mode
UART Port Controller Packing Mode The UART provides packed and unpacked modes of data transfer to and from the internal memory of the ADSP-21367/8/9 and ADSP-2137x pro- cessors. This mode is set using the bit (bit 0) in the UARTPACK UARTxMODE register.
Page 544 Packing Mode register must be read before reading the register, UARTxRBR because the latter clears the bit. Reading the register UARTxRBR clears both the address-detect and the data-ready interrupts. In non-packed mode, when the address-detect interrupt is generated, it means that the data is ready in the buffer while in packed mode, this is not the case.
Page 545: Two Wire Interface Controller
12 TWO WIRE INTERFACE CONTROLLER The two wire interface (TWI) controller allows a device to interface to an inter-IC bus as specified by the Philips I C Bus Specification version 2.1 dated January 2000. Overview The TWI is fully compatible with the widely used I C bus standard.
Page 546: Architecture
Architecture • Separate multiple-byte receive and transmit FIFOs • Low interrupt rate • Individual override control of data and clock lines in the event of a bus lockup • Input filter for spike suppression Table 12-1 shows the pins for the TWI. Two bidirectional pins externally interface the TWI controller to the I C bus.
Page 547 Two Wire Interface Controller TRANSMIT SHIFT REGISTER FIFO ARBITRATION RECEIVE SHIFT REGISTER ADDRESS COMPARE PERIPHERAL PRESCALER INTERFACE REGISTERS CLOCK GENERATION Figure 12-1. TWI Block Diagram The transmit shift register serially shifts its data out externally off chip. The output can be controlled to generate acknowledgements or it can be manually overwritten.
Page 548: Register Descriptions
Register Descriptions The clock generation module is used to generate an external serial clock ) when in master mode. It includes the logic necessary for synchroni- zation in a multimaster clock configuration and clock stretching when configured in slave mode. Register Descriptions The TWI controller has 16 registers which are described in the following sections.
Page 549: Twidiv Register
Two Wire Interface Controller TWIDIV Register During master mode operation, the serial clock divider register ( TWIDIV values are used to create the high and low durations of the serial clock ). Serial clock frequencies can vary from 400 kHz to less than 20 kHz. The resolution of the generated clock is 1/10 MHz or 100 ns.
Page 550: Slave Mode Address Register
Register Descriptions Slave Mode Address Register The TWI slave mode address register ( ) holds the slave mode TWISADDR address, which is the valid address that the slave-enabled TWI controller responds to. The TWI controller compares this value with the received address during the addressing phase of a transfer.
Page 551: Master Mode Status Register
Two Wire Interface Controller controller appends the read/write bit as appropriate based on the state of bit in the master mode control register. For more information, MDIR see “Master Address Register (TWIMADDR)” on page A-139. Master Mode Status Register The TWI master mode status register ( ) holds information dur- TWIMSTAT ing master mode transfers and at their conclusion.
Page 552: Interrupt Enable Register
Register Descriptions After servicing the interrupt source associated with a bit, programs must clear that interrupt source bit. All bits are sticky and W1C-type. For more information, see “Interrupt Source Register (TWIIRPTL)” on page A-147. Interrupt Enable Register The TWI interrupt enable register ( ) allows interrupt sources to TWIIMASK assert the interrupt output.
Page 553: 8-Bit Receive Fifo Register
Two Wire Interface Controller bus access times, a double byte transfer data access can be performed. Two data bytes can be written, effectively filling the transmit FIFO buffer with a single access. The data is written in little-endian byte order as shown in Figure 12-2, where byte 0 is the first byte to be transferred and byte 1 is the second byte...
Page 554: 16-Bit Receive Fifo Register
Data Transfer Mechanics 16-Bit Receive FIFO Register The TWI 16- bit FIFO receive register ( ) holds a 16-bit data value RXTWI16 read from the FIFO buffer. Although peripheral bus reads are 32 bits, a read access to the register can only access two receive data bytes RXTWI16 from the FIFO buffer.
Page 555: Clock Generation And Synchronization
Two Wire Interface Controller To better understand the mapping of TWI controller register contents to a basic transfer, Figure 12-4 details the same transfer as above noting the corresponding TWI controller bit names. In this illustration, the TWI controller successfully transmits one byte of data. The slave has acknowl- edged both address and data.
Page 556: Bus Arbitration
Data Transfer Mechanics HIGH COUNT COUNT TWI CONTROLLER CLOCK SECOND MASTER CLOCK RESULT Figure 12-5. TWI Clock Synchronization Bus Arbitration The TWI controller initiates a master mode transmission ( ) only TWIMEN when the bus is idle. If the bus is idle and two masters initiate a transfer, arbitration for the bus begins.
Page 557 Two Wire Interface Controller SCL (BUS) TWI CONTROLLER DATA SECOND MASTER DATA SDA (BUS) ARBITRATION LOST START Figure 12-6. TWI Bus Arbitration SCL (BUS) SDA (BUS) STOP START Figure 12-7. TWI Start and Stop Conditions The TWI controller’s special-case start and stop conditions include: •...
Page 558: General Call Support
Data Transfer Mechanics • TWI controller addressed as a slave-transmitter If the master asserts a stop condition during the data phase of a transfer, the TWI controller concludes the transfer ( ) and TWISCOMP indicates a slave transfer error ( TWISERR •...
Page 559: Programming Examples
Two Wire Interface Controller Programming Examples The following sections include programming examples for general setup, slave mode, and master mode, as well as guidance for repeated start condi- tions. For an example of programming the TWI using the digital peripheral interface and SRU2, see “Configuring the Two Wire Interface”...
Page 560 Programming Examples 2. Program the register. These are the initial data TXTWI8 TXTWI16 values to be transmitted in the event the slave is addressed as a transmitter. This is an optional step. If no data is written and the slave is addressed and a transmit is required, the serial clock ( ) is stretched and an interrupt is generated.
Page 561: Master Mode Clock Setup
Two Wire Interface Controller Master Mode Clock Setup Master mode operation is set up and executed on a per-transfer basis. An example of programming steps for a receive and for a transmit are given separately in following sections. The clock setup programming step listed here is common to both transfer types.
Page 562: Master Mode Receive
Programming Examples 5. Program the register. This prepares and enables master TWIMCTL mode operation. As an example, programming the value 0x0201 enables master mode operation, generates a 7-bit address, sets the direction to master-transmit, uses standard mode timing, and transmits 8 data bytes before generating a stop condition. Table 12-3 shows what the interaction between the TWI controller and the processor might look like using this example.
Page 563: Repeated Start Condition
Two Wire Interface Controller 4. Program the register. Ultimately this prepares and enables TWIMCTL master mode operation. As an example, programming the value 0x0201 enables master mode operation, generates a 7-bit address, sets the direction to master-receive, uses standard mode timing, and receives 8 data bytes before generating a stop condition.
Page 564 Programming Examples REPEATED START STOP START 7-BIT ADDRESS 8-BIT DATA 7-BIT ADDRESS 8-BIT DATA TWIRXINT INTERRUPT TWITXINT INTERRUPT TWIMCOM INTERRUPT TWIMCOM INTERRUPT Shaded region indicates slave to master transmission. Figure 12-8. Transmit/Receive Data Repeated Start The tasks performed at each interrupt are: •...
Page 565: Receive/Transmit Repeated Start Sequence
Two Wire Interface Controller • Re-program with the desired number of bytes to DCNT receive. • interrupt TWISERR This interrupt is generated due to the arrival of a byte into the receive FIFO. Simple data handling is all that is required. Receive/Transmit Repeated Start Sequence Figure 12-9 illustrates a repeated start data receive followed by a data...
Page 566: Electrical Specifications
Electrical Specifications • interrupt TWIMCOMP This interrupt has occurred due to the completion of the data receive transfer. At this time the data transmit transfer begins. The field should be set to reflect the number of bytes to be TWIDCNT transmitted.
Page 567: Precision Clock Generators
13 PRECISION CLOCK GENERATORS The precision clock generators (PCG) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. The units, A B, C, and D, are identical in functionality and operate independently of each other.
Page 568 The core phase-locked loop (PLL) has been designed to provide clocking for the processor core. Although the performance specifications of this PLL are appropriate for the core, they have not been optimized or speci- fied for precision data converters where jitter directly translates into time quantization errors and distortion.
Page 569: Clock Outputs
Precision Clock Generators being a clock and frame sync slave. The clock generated by the SPORT is sufficient for most of the serial communications, but it is suboptimal for analog/digital conversion. Therefore, all precision data converters should be synchronized to a clock generated by the PCG or to a clean (low jitter) clock that is fed into SRU1 off-chip through a pin.
Page 570: Frame Sync Outputs
Frame Sync Outputs bit (bit 31 in the registers) specifies the input CLKASOURCE PCG_CTLA1 source for the clock of the respective units (A, B, C, and D). When this bit is cleared (= 0), the input is sourced from the external oscillator, as shown Figure 13-1.
Page 571: Normal Mode
Precision Clock Generators Frame sync generation from a unit is independently enabled and con- trolled. Sources for the frame sync generation can be either from the crystal buffer output, , or an external pin source. There is only one PCLK external source pin for both frame sync and clock output for a unit.
Page 572: Bypass Mode
Frame Sync Outputs sync appears to lead the clock. If the phase is only slightly less than the divisor, then the frame sync appears to lag the clock. The frame sync phase should not be greater than the divisor. Bypass Mode In bypass mode, the frame sync divisor is either 0 or 1.
Page 573: Frame Sync Output Synchronization With An External Clock
Precision Clock Generators Frame Sync Output Synchronization With an External Clock The frame sync output may be synchronized with an external clock by programming the registers (shown in PCG_SYNC PCG_SYNC2 Figure A-77 on page A-160) and the PCG control registers ( PCG_CTLA0–1 , and ) appropriately.
Page 574: Frame Sync
Frame Sync Output Synchronization With an External Clock MCLK EXT CLK FSA OUTPUT Figure 13-2. Clock Output Synchronization With External Clock Frame Sync For a given frame sync, the output is determined by the following: • Divisor. A 20-bit divisor of the input clock that determines the period of the frame sync.
Page 575: Phase Shift
Precision Clock Generators The frequency of the frame sync output is determined by: Frequency of Clock Input Frame Sync Divisor When the divisor is set to any value other than 0 or 1, the processors oper- ate in normal mode. The frame sync divisors ( bits) are specified in bits 19–0 of the cor- FSxDIV...
Page 576: Phase Shift Settings
Phase Shift When using a clock and frame sync as a synchronous pair, the units must be enabled in a single atomic instruction before their parame- ters are modified. Both units must also be disabled in a single atomic instruction. Phase Shift Settings The phase shift between clock and frame sync outputs may be pro- grammed under these conditions:...
Page 577 Precision Clock Generators CLO CK INPUT (FOR BOTH CLOCK AND FRAME SYNC) CLOCK OUTPUT FRAME SYNC OUTPUT (PHASE SHIFT = PERIOD -1) FRAME SYNC OUT PUT (PHASE SHIFT = 0) FRAME SYNC OUT PUT (PHASE SHIFT = 1) FRAME SYNC OUT PUT (PHASE SHIFT = 2) ENABLE OTHER VALUES:...
Page 578: Bypass Mode
Phase Shift Bypass Mode When the divisor for the frame sync has a value of 0 or 1, the frame sync is in bypass mode, and the registers have different func- PCG_PW PCG_PW2 tionality than in normal mode. Two bit fields determine the operation in this mode.
Page 579: Bypass As A One-Shot
Precision Clock Generators Bypass mode also enables the generation of a strobe pulse (one-shot). Strobe usage ignores the counter and looks to SRU1 to provide the input signal. Bypass as a One-Shot When the bits (bit 0, bit 16 of the register) or STROBEA STROBEB...
Page 580: Programming Examples
Programming Examples CLOCK INPUT FOR FRAME SYNC MISCA2_I FRAME SYNC OUTPUT (INVFSA = 0, STROBEA = 1) FRAME SYNC OUTPUT (INVFSA = 1, STROBEA = 1) Figure 13-5. One-Shot (Synchronous Clock Input and MISCA2_I) The second bit (bit 1) of the pulse width control register ( INVFSA PCG_PW determines whether the falling or rising edge is used.
Page 581 Precision Clock Generators PCG Setup for I S or Left-Justified DAI This example shows how to set up two precision clock generators using the S/PDIF receiver and an asynchronous sample rate converter (SRC) to interface to an external audio DAC. In this example an input clock ) of 33.330 MHz is assumed and the PCG is configured to provide CLKIN a fixed SRC/DAC output sample rate of 65.098 kHz.
Page 582 Programming Examples Table 13-2. Precision Clock Generator Division Ratios (33.330 CLKIN) PCG Divisors PCG CLOCK SCLK FSYNC Sample Rate kHz) INPUT 130.195 65.098 43.398 32.549 1024 26.039 1280 21.699 1536 18.599 1792 1 The frame sync divisor should be an even integer in order to produce a 50% duty cycle waveform.
Page 583 Precision Clock Generators The combined PCGs can provide a selection of synchronous clock frequencies to support alternate sample rates for the SRCs and external DACs. However, the range of choices is limited by CLKIN and the ratio of which is normally fixed at PCG_CLKx_O:SCLK:FSYNC 256:64:1 to support digital audio, left-justified, I S, and right-jus-...
Page 584 Programming Examples FS OUT = 65.1 kHz ADSP-21369 24-BIT, LEFT-JUSTIFIED PLAYER SDATA OUT DAI_P8 RxSCLK SDATA IN DAI_P19 DAI_P9 RxLRCLK S/PDIF LRCLK IN SDATA IN DAI_P10 S/PDIF IN SCLK IN (FS IN , 44.1 kHz FSYNC A (FS OUT ) ÷ 512 = 65.1 kHz STEREO DAC PCG A SCLK A (64 FS OUT ) ÷...
Page 585 Precision Clock Generators Listing 13-1. PCG Initialization /*********************************************************** Required Output Sample Rate = 65.098 kHz Function Control Phase/ Reg Hex Address Divisor Contents FS_A_Ph_Hi/FS_A_Div PCG_CTLA0 0x24C0 0/512 0xC00/00200 FS_A_Ph_Lo/CLK_A_Div PCG_CTLA1 0x24C1 0x004/00008 -------------------------------------------------------------- FS_B_Ph_Hi/FS_B_Div PCG_CTLB0 0x24C2 0x800/00000 FS_B_Ph_Lo/CLK_B_Div PCG_CTLB1 0x24C3 0x000/00002 PW_FS_B/PW_FS_A PCG_PW...
Page 586: Clock And Frame Sync Divisors Pcg Channel B
Programming Examples /* Enable PCGA SCLK & FSYNC and set FSYNC_A divisor */ r0 = (ENCLKA | ENFSA | PCGA_FS_DIVISOR); dm(PCG_CTLA0) = r0; /* Set PCGB SCLK & FSYNC Source first to Xtal Buffer and set SCLK_B divisor */ r0 = ((PCGB_FS_PHASE_LO << 20) | PCGB_CLK_DIVISOR); dm(PCG_CTLB1) = r0;...
Page 587 Precision Clock Generators Listing 13-2. PCG Channel B Output Example /* Register Definitions */ #define SRU_CLK4 0x2434 #define SRU_PIN0 0x2460 #define SRU_PBEN0 0x2478 #define PCG_CTLB0 0x24C2 #define PCG_CTLB1 0x24C3 #define PCG_PW 0x24C4 /* SRU Definitions */ #define PCG_CLKB_P 0x39 #define PCG_FSB_P 0x3B #define PBEN_HIGH_Of 0x01...
Page 588 Programming Examples /* Enable DAI Pins 1 & 2 as outputs */ r0 = PBEN_HIGH_Of|(PBEN_HIGH_Of<<DAI_PB02); dm(SRU_PBEN0) = r0; r0 = (100<<PCG_PWB); /* PCG Channel B FS Pulse width = 100 */ dm(PCG_PW) = r0; r2 = 1000; /* Define 20-bit Phase Shift */ r0 = (ENFSB|ENCLKB| /*Enable PCG Channel B Clock and FS*/ 1000000);...
Page 589: Pcg Channel A And B Output Example
Precision Clock Generators PCG Channel A and B Output Example Listing 13-3 uses two PCG channels. Channel A is set up to only generate a clock signal. This clock signal is used as the input to channel B through SRU1. The clock and frame sync are routed to DAI pins 1 and 2, respec- tively, in the same manner as Listing 13-1.
Page 590 Programming Examples /* Bit Definitions */ #define ENCLKA 0x80000000 #define ENFSB 0x40000000 #define ENCLKB 0x80000000 #define CLKBSOURCE 0x80000000 #define FSBSOURCE 0x40000000 /* Main code section */ .global _main; /* Make main global to be accessed by ISR */ .section/pm seg_pmco; _main: /*Route PCG Channel A clock to PCG Channel B Input via SRU*/ r0 = (PCG_CLKA_O<<PCG_EXTB_I);...
Page 591 Precision Clock Generators r0 = (ENFSB|ENCLKB|10); /*Enable PCG Channel B Clock and FS*/ /* FS Divisor = 10, FS Phase 10-19 = 0 */ dm(PCG_CTLB0) = r0; r0 = (CLKBSOURCE|FSBSOURCE|10); /* Clk Divisor = 10 */ /* FS Phase 0-9 = 0, Use SRU_MISC4 as clock source */ dm(PCG_CTLB1) = r0;...
Page 592 Programming Examples 13-26 ADSP-21368 SHARC Processor Hardware Reference...
Page 593: 14 System Design
14 SYSTEM DESIGN The ADSP-21367/8/9 and ADSP-2137x processors support many system design options. The options implemented in a system are influenced by cost, performance, and system requirements. This chapter provides the following system design information: • “Processor Pin Descriptions” on page 14-2 •...
Page 594: Processor Pin Descriptions
Processor Pin Descriptions Before proceeding with this chapter it is recommended that you become familiar with the ADSP-21367/8/9 and ADSP-2137x pro- cessor’s core architecture. This information is presented in the ADSP-2136x SHARC Processor Programming Reference. Processor Pin Descriptions Refer to the processor-specific data sheet for pin information, including package pinouts for the currently available package options.
Page 595 System Design The processors also include the multiplexers for pins. The FLAG0–3 pins can act as core , and the pin can act FLAG0–2 FLAGS0–2 IRQ0–2 FLAG3 as a core or as the signal of the system timer. FLAG3 TMREXPEN Table 14-1 on page 14-7 shows the register bit settings for the dif-...
Page 596 Processor Pin Descriptions F LA G S3 - 0 3 - 0 P W M 3 - 0 FLA G S 7 - 4 7 - 4 P W M 7 - 4 FLA G S/P W M 15 - 0 FLA G S1 1 - 8 1 1 - 8 P W M 1 1 - 8...
Page 597 System Design FLAG0 FLAG0 PIN IRQ0 FLAG1 PIN FLAG1 IRQ1 FLAG0 FLAG1 FLAG2 FLAG3 FLA2 FLAG2 PIN IRQ2 FLAG0 FLAG3 PIN TIMEXP FLAGS3 - 0 PWM3 - 0 3 - 0 FLAGS7 - 4 PWM7 - 4 7 - 4 FROM EXTERNAL FLAGS/PWM15 - 0 PORT...
Page 598: Choosing Ep Data Mode
Processor Pin Descriptions Choosing EP Data Mode (0, 1, 2, 3) and pins are completely independent. FLAG DATA31–0 Any mode of programming in one group does not affect the other. Case 1 If 32-bit external SDRAM/FLASH/SRAM is used, then all data pins should be connected to the memory device so that no other functionality can be programmed in the data pins.
Page 599 System Design Case 5 If no external memory is used, and if the PDAP data lines are connected to DATA pins, and if 8 flags are required, then use MODE 6. Connect the PADP control lines to the DATA pins, and program the flag direction in the register.
Page 600: Interrupt And Timer Pins
Processor Pin Descriptions • pin is not used DATA9 • pin acts as (output) DATA8 PDAP STROBE Interrupt and Timer Pins The processor’s external interrupt pins, flag pins, and timer pin can be used to send and receive control signals to and from other devices in the system.
Page 601: Programming Flags
System Design When the bit (bit 30 in the register) is set (= 1 which SPIPDN PMCTL shuts down the clock to the SPI), the pins cannot be used FLAGx (through the register bits) because the pins are syn- FLAGS7–0 FLAGx chronized with the clock.
Page 602 Processor Pin Descriptions 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FLAGS FLG15O FLG8 FLAG15 Output Select FLAG8 Value FLG15 FLG8O FLAG15 Value FLAG8 Output Select FLG14O FLG9 FLAG14 Output Select FLAG9 Value FLG14 FLG9O FLAG14 Value...
Page 603 System Design 2. 32 data pins • All 16 flags can be mapped. • Can be mapped only in groups of four. • Should be programmed through the register. SYSCTL more information, see “System Control Register (SYSCTL)” on page A-5. 3.
Page 604: Jtag Interface Pins
Processor Pin Descriptions And for FLAGS4–15 • In output mode, if the same flag is mapped to both data pins and DPI pins, then the output comes from both pins. • In input mode, if the same flag is mapped to both data pins and DPI pins, the input from data pins is given priority.
Page 605: Clock Derivation
A detailed discussion of JTAG and its uses can be found in Engi- neer-to-Engineer Note EE-68, Analog Devices JTAG Emulation Technical Reference. This document is available on the Analog Devices Web site at www.analog.com/processors. Clock Derivation...
Page 606: Power Management Control Register
Clock Derivation Power Management Control Register The ADSP-21367/8/9 and ADSP-2137x processors have a power manage- ment control register ( ) that allows programs to determine the PMCTL amount of power dissipated. This includes the ability to program the PLL dynamically in software, achieving a slower core instruction rate that min- imizes power use.
Page 607 System Design Listing 14-2. PMCTL Example Code ENABLING CLKOUT: ustat2 = dm(PMCTL); bit set ustat2 CLKOUTEN; /* switch pin function from Reset Out (RSTOUT) to CLKOUT */ dm(PMCTL) = ustat2; PLL Divisor modification: ustat2 = dm(PMCTL); bit clr ustat2 PLLM63|PLLD8; /* clear old multiplier and divisor*/ bit set ustat2 DIVEN|PLLD8;...
Page 608: Pll Programming Examples
Clock Derivation When the PLL is programmed using a multiplier and a divisor, the DIVEN bits should NOT be programmed in the same core clock cycle. PLLBP There should be a delay of at least one core clock cycle between program- ming these bits.
Page 609 System Design dm(PMCTL) = ustat2; waiting_loop: r0 = 4096; /* wait for PLL to lock at new rate (requirement for modifying multiplier only) */ lcntr = r0, do pllwait until lce; pllwait: nop; ustat2 = dm(PMCTL); bit clr ustat2 PLLBP; /* take PLL out of Bypass, PLL is now at CLKIN*4 (CoreCLK = CLKIN * M/N = CLKIN* 16/4) */...
Page 610 Clock Derivation Listing 14-4. PLL Programming Example 2 ustat2 = dm(PMCTL); bit clr ustat2 PLLM63|PLLD8; /* clear old multiplier and divisor*/ bit set ustat2 PLLBP | PLLD4 |PLLM16; /* set a multiplier of 16 and a divider of 4 and enable Bypass mode*/ ustat2 = dm(PMCTL);...
Page 611: Phase-Locked Loop Startup
System Design /* Core clock = (24.576 MHz * 27) /2 = 331.776 MHz */ pmctlsetting= SDCKR2|PLLM27|PLLD2|DIVEN; *pPMCTL= pmctlsetting; pmctlsetting|= PLLBP; *pPMCTL= pmctlsetting; pmctlsetting ^= DIVEN; /* Wait for around 4096 cycles for the pll to lock. */ for (i=0; i<4096; i++) asm("nop;");...
Page 612: Reset And Clkin
Clock Derivation RESET and CLKIN The processor receives its clock input on the pin. The processor uses CLKIN an on-chip, phase-locked loop (PLL) to generate its internal clock, which is a multiple of the frequency. Because the PLL requires some time CLKIN to achieve phase lock, must be valid for a minimum time period...
Page 613 System Design the application is to provide the highest permissible internal frequency for a given frequency. For more information on available clock rates, CLKIN see the processor-specific data sheet. Table 14-3. Selecting Core to CLKIN Ratio Typical Crystal and Clock Oscillators Inputs 12.500 16.667 25.000...
Page 614: Running Reset (Adsp-2137X)
Clock Derivation Running Reset (ADSP-2137x) All members of the SHARC processor family, including the ADSP-21375 and ADSP-21371, continue to support the hardware reset controlled with pin. The de-assertion of this hardware reset enables the PLL and RESET asserting it resets the PLL. In the time it takes the PLL to acquire lock (set to 4096 cycles), the processor, internal memory, and the peripherals CLKIN...
Page 615: System Design Considerations
System Design System Design Considerations It is important that an external 10 kΩ pull-up resistor is placed on the pin if it is intended to be used as an input for RESETOUT/CLKOUT/RUNRSTOUT initiating a running reset on the ADSP-2137x processor as shown in Figure 14-4.
Page 616 Clock Derivation There are several possible methods that can be used to implement running reset. The following illustrates one example of a running reset implemen- tation involving an ADSP-2137x processor and a host processor. External Host In an AVR (audio-video receiver) system, a host micro controller may communicate with the ADSP-2137x processor using the serial peripheral interface (SPI).
Page 617: Running Reset Control Register (Runrstctl)
System Design 2. The ADSP-2137x processor receives the command and completes any unfinished work which may also include writing to the RUN- register. RSTCTL 3. When the ADSP-2137x processor is ready to accept the running reset, it signals the host over the command interface. 4.
Page 618: Programming The Runrstctl Register
Clock Derivation Programming The RUNRSTCTL Register To configure running reset: 1. Set bit 0 (=1) to change pin direction to input. RESETOUT/CLKOUT 2. Ensure that the pin is driven to a proper state, RESETOUT/CLKOUT and then assert to sensitize logic to the state of the RUNRSTEN pin.
Page 619: Reset Generators
The signal should not only offer a suitable RESET delay, but it should also have a clean monotonic edge. Analog Devices has a range of microprocessor supervisory ICs with different features. Features include one or more of the following: •...
Page 620: Timing Specifications
Clock Derivation +1.2V DDINT +3.3V DDEXT 10µF V DDINT V DDEXT V CC ADM809-RART ADSP-213xx RESET RESET Figure 14-6. Simple Reset Generator Another part, the ADM706TAR, provides power on and optional RESET manual . It allows designers to create a more complete supervisory RESET circuit that monitors the supply voltage.
Page 621 System Design +3.3V DDEXT LINE SENSE DDEXT V t > 1.3V V CC ADSP-213xx V t > 1.3V RESET LL W ADM8697 3.3V FLAGx OSCSEL OSCIN IRQx RESET Figure 14-7. Reset Generator and Power Supply Monitor To determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider control of each port ( DIVx for the serial ports).
Page 622 Clock Derivation 160 MHz < VCO_OUT < 800 MHz CCLK LOOP ÷1, 2, 4, 8 100 MHz – FILTER ÷2 CLKIN 400 MHz (see data sheet) PLLBP[15] DIVEN[9] INDIV[8] ÷1 PLLD[7..6] PCLK ÷2 MULTIPLIER (IOP) XTAL BLOCK ÷2, 2.5, PLLM[5..0] SDCLK BOOT CLKCFG[]->PLLM[] CFG 3, 3.5, 4...
Page 623 System Design Table 14-6. Clock Relationships Timing Description Requirements CLKOUT Clock Period PLL Input Clock PLLICK Core Clock Period (Processor) CCLK Peripheral Clock Period = 2 × t PCLK CCLK ) × SR Serial Port Clock Period = (t SCLK PCLK SPI Clock Period = (t ) * SPIR...
Page 624: Input Synchronization Delay
Conditioning Input Signals Input Synchronization Delay The processor has several asynchronous inputs— RESET TRST IRQ2–0 , and (when configured as inputs). These inputs can be MS3–0 FLAG16-0 asserted in arbitrary phase to the processor clock, . The processor CLKIN synchronizes the inputs prior to recognizing them. The delay associated with recognition is called the synchronization delay.
Page 625: Reset Input Hysteresis
System Design RESET Input Hysteresis Hysteresis is used only on the input signal. Hysteresis causes the RESET switching point of the input inverter to be slightly above 1.4 V for a rising edge and slightly below 1.4 V for a falling edge. The value of the hysteresis is approximately ±...
Page 626: Other Recommendations And Suggestions
Designing for High Frequency Operation Keep the portions of the system that operate at different frequencies as physically separate as possible. The clock supplied to the processor must have a rise time of 3 ns or less and must meet or exceed a high and low voltage of 2 V and 0.4 V, respectively.
Page 627: Decoupling Capacitors And Ground Planes
System Design Decoupling Capacitors and Ground Planes Extended copper planes must be used for the ground and power supplies. Designs should use an absolute minimum of 12 bypass capacitors (four 0.1 μF, four 10 nF and four 1 nF ceramic) for each VDDEXT VDDINT supply.
Page 628: Recommended Reading
Designing for High Frequency Operation ADSP-213xx CASE 1: CASE 2: BYPASS CAPACITORS ON NON-COMPONENT BYPASS CAPACITORS ON COMPONENT (TOP) (BOTTOM) SIDE OF BOARD, BENEATH DSP SIDE OF BOARD, AROUND DSP PACKAGE PACKAGE Figure 14-9. Bypass Capacitor Placement Recommended Reading The text High-Speed Digital Design: A Handbook of Black Magic is recom- mended for further reading.
Page 629: Booting
System Design • Ground Planes and Layer Stacking • Terminations • Vias • Power Systems • Connectors • Ribbon Cables • Clock Distribution • Clock Oscillators High-Speed Digital Design: A Handbook of Black Magic, Johnson & Gra- ham, Prentice Hall, Inc., ISBN 0-13-395724-1. Booting When a processor is initially powered up, its internal SRAM is undefined.
Page 630 Booting 2. The DMA completes and the interrupt associated with the periph- eral that the processor is booting from is activated. The processor jumps to the applicable interrupt vector location and executes the code located there. (Typically, the first instruction at the interrupt vector is a return from interrupt ( ) instruction.) 3.
Page 631: External Port Booting
System Design External Port Booting The ADSP-21367/8/9 processors allow booting through the external port. There are two options, which are described in the following sections. Booting Through the AMI The asynchronous memory interface (AMI) supports an 8-bit user boot called AMI boot. Only the signal is used for AMI(FLASH/EEPROM) booting.
Page 632: Shared Memory Booting
Booting Shared Memory Booting To boot multiple processors from a single EPROM/FLASH, the processor performs the following steps. 1. Arbitrate for the bus. 2. Receive through DMA the 256-word boot kernel, after becoming bus master. 3. Release the bus, allowing the next processor access to the EPROM/FLASH.
Page 633 System Design ADDR DATA ADSP-21368 ADDR ADDR DATA DATA ADSP-21368 EPROM ADDR DATA ADSP-21368 ADDR DATA ADSP-21368 Figure 14-10. Alternating Booting From an EPROM ADSP-21368 SHARC Processor Hardware Reference 14-41...
Page 634: Spi Port Booting
Booting SPI Port Booting The ADSP-21367/8/9 and ADSP-2137x processors support booting from a host processor through the SPI slave ( = 00), and booting BOOT_CFG1–0 from an SPI flash, SPI PROM, or a host processor through SPI master mode ( = 01).
Page 635: 32-Bit Spi Host Boot
System Design For 16-bit SPI devices, two words shift into the 32-bit receive shift regis- ter ( ) before a DMA transfer to internal memory occurs. For 8-bit SPI RXSR devices, four words shift into the 32-bit receive shift register before a DMA transfer to internal memory occurs.
Page 636: 16-Bit Spi Host Boot
Booting The following example shows a 48-bit instructions executed. [0x90000] 0x112233445566 [0x90001] 0x7788AABBCCDD 0x90000 Internal Memory 0x900FF MOSI Figure 14-13. 32-Bit SPI Host Packing The 32-bit SPI host packs or prearranges the data as: SPI word 1 = 0x33445566 SPI word 2 = 0xCCDD1122 SPI word 3 = 0x7788AABB...
Page 637 System Design The following example shows a 48-bit instructions executed. [0x90000] 0x112233445566 [0x90001] 0x7788AABBCCDD 0x90000 Internal Memory (Loader Kernel) 0x900FF MOSI Figure 14-14. 16-Bit SPI Host Packing The 16-bit SPI host packs or prearranges the data as: SPI word 1 = 0x5566 SPI word 2 = 0x3344...
Page 638: 8-Bit Spi Host Boot
Booting 8-Bit SPI Host Boot Figure 14-15 shows 8-bit SPI host packing of 48-bit instructions executed at PM addresses 0x90000 and 0x90001. For 8-bit hosts, four 8-bit words pack into the shift register to generate a 32-bit word. The 32-bit word shifts to internal program memory during the load of the 256-instruction word kernel.
Page 639: Slave Boot Mode
System Design SPI word 9 = 0xBB SPI word 10 = 0xAA SPI word 11 = 0x88 SPI word 12 = 0x77 The initial boot of the 256-word loader kernel requires an 8-bit host to transmit 1536 8-bit words. The SPI DMA count value of 0x180 is equal to 384 words.
Page 640: Master Boot
Booting Table 14-11. SPI Slave Boot Bit Settings (Cont’d) Setting Comment DMISO Set (= 1) MISO MISO disabled SENDZ Cleared (= 0) Send last word SPIRCV Set (= 1) Receive DMA enabled CLKPL Set (= 1) Active low SPI clock CPHASE Set (= 1) Toggle SPICLK at the beginning of the first bit...
Page 641 System Design Master boot mode is used when the processor is booting from an SPI-compatible serial PROM, serial FLASH, or slave host processor. The specifics of booting from these devices are discussed individually. On reset, the interface starts up in master mode performing a 384 32-bit word DMA transfer.
Page 642 Booting Table 14-14. Parameter Initialization Value for Master Boot (Cont’d) Parameter Register Initialization Value Comment SPIDMAC 0x0000 0007 Enable receive, interrupt on completion IISPI 0x0008 0000 Start of block 0 normal word memory IMSPI 0x0000 0001 32-bit data transfers CSPI 0x0000 0180 0x100 instructions = 0x180 32-bit words From the perspective of the processor, there is no difference between boot-...
Page 643: Booting From An Spi Flash
System Design Following that, a 24-bit address (all zeros) is always driven by the proces- sor. On the following cycle (cycle 32), the processor expects the SPICLK first bit of the first word of the boot stream. This transfer continues until the kernel has finished loading the user program into the processor.
Page 644: Booting From An Spi Prom (16-Bit Address)
Data Delays, Latencies, and Throughput Booting From an SPI PROM (16-Bit address) Figure 14-16 shows the initial 32-bit word sent out from the processor from the perspective of the serial PROM device. As shown in Figure 14-16, SPI EEPROMS only require an 8-bit opcode and a 16-bit address.
Page 645: Execution Stalls
System Design Table 14-15. Latencies and Throughput Operation Minimum Data Maximum Throughput Delay (cycles) (cycles/ transfer) Interrupts (IRQ2-0) DMA chain initialization 7–11 Serial ports 1 Processor-to -processor transfers using 32-bit words. Execution Stalls The following events can cause an execution stall for the ADSP-21367/8/9 and ADSP-2137x SHARC processors: •...
Page 646: Dag Stalls
Data Delays, Latencies, and Throughput Instruction 3: Instruction involving post-modify addressing involv- ing same register such as . This last instruction R0 = DM(I1,M2); stalls the processor for one cycle. • Any read reference to a memory-mapped register located physically within the core (registers like , which are not situated in the SYSCTL...
Page 647: Iop Register Stalls
System Design When a new external memory instruction fetch occurs on the ADSP-2137x processor due to a jump from internal to external memory, or after a cache hit while executing instructions from external memory, there is one stall cycle present in the fetch1 stage. This stall avoids resource conflicts at the cache interface.
Page 648: Dma Stalls
Data Delays, Latencies, and Throughput DMA Stalls • One cycle if an access to a DMA parameter register conflicts with the DMA address generation (for example, writing to the register while a register update is taking place) or reading while a DMA register conflicts with DMA chaining.
Page 649: Register Reference
REGISTER REFERENCE The ADSP-21367/8/9 and ADSP-2137x processors have general-purpose and dedicated registers in each of their functional blocks. The register ref- erence information for each functional block includes bit definitions, initialization values, and memory-mapped addresses (for I/O processor registers). Information on each type of register is available at the following locations: •...
Page 650: I/O Processor Registers
For convenience and consistency, Analog Devices provides a header file that provides these bit and registers definitions. An...
Page 651: Notes On Reading Register Drawings
Register Reference When there is contention among the buses for access to registers in the same I/O processor register group, the processor arbitrates register access as follows: • Data memory (DM) bus accesses • Program memory (PM) bus accesses • I/O processor (IO) bus (lowest priority) accesses The bus with highest priority gets access to the I/O processor register group, and the other buses are held off from accessing that I/O processor register group until that access has been completed.
Page 652 I/O Processor Registers 3. In cases where there are multiple registers that have the same bits (such as serial ports), one register drawing is shown and the names and addresses of the others are simply listed. 4. The bit descriptions are intentionally brief. More detailed informa- tion can be found in the tables that follow the register drawings and in the chapters that describe the particular module.
Page 653: System Control Register (Sysctl
Register Reference System Control Register (SYSCTL) register configures memory use, interrupts, and many aspects SYSCTL of pin multiplexing. (For more information, see “Pin Multiplexing” on page 14-2.) This register’s address is 0x30024. The reset value for this reg- ister is 0. Bit descriptions for this register are shown in Figure A-1 Figure A-2, and described in...
Page 654 I/O Processor Registers 15 14 13 12 11 10 SYSCTL (0x30024) SRST Reserved Software Reset 1=Software reset IMDW3 0=No software reset Internal Memory Block 3 Data Width Reserved 1=Data bus width is 48 bits 0=Data bus is 32 bits IIVT Internal Interrupt Vector IMDW2 Table...
Page 655 Register Reference Table A-1. SYSCTL Register Bit Descriptions (Cont’d) Name Description RBPR Rotating Priority Bus Arbitration. This bit enables or disables prior- ity rotation among DMA channels. Permits core writes. 0 = Arbiter uses fixed priority 1 = Arbiter uses rotating priority Reserved IMDW0 Internal Memory Data Width 0.
Page 656 I/O Processor Registers Table A-1. SYSCTL Register Bit Descriptions (Cont’d) Name Description TMREXPEN Flag Timer Expired Mode. 0 = Flag3 pin is a general-purpose I/O pin. Permits core writes. 1 = Flag3 pin output is timer expired signal (TIMEXP). MSEN Memory Select.
Page 657: System Status Register (Systat
Register Reference System Status Register (SYSTAT) register’s address is 0x180F. The reset value has all bits initial- SYSTAT ized to zero, except for the , and fields, which are set from CRBM CRAT values on the ADSP-21367/8/9 and ADSP-2137x’s pins. This register is shown in Figure A-3 and described in...
Page 658: External Port Registers
External Port Registers Table A-2. System Status Register (SYSTAT) Bit Descriptions (Cont’d) Name Description Reserved (reset value =0) 10–8 ID Code. These bits indicate the state of the ID pins on the proces- sor. The reset value of IDC is undefined. 31-11 Reserved (reset value =0) External Port Registers...
Page 659 Register Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EPCTL (0x1801) DATE Reserved DATA Enable In no pack mode, masks those bits of the data lane with zeros. 15 14 13 12 11 10 B0SD DATE Bank 0 SDRAM...
Page 660 External Port Registers Table A-3. EPCTL Register Bit Descriptions (Cont’d) Name Description B2SD Select Bank 2 SDRAM. 1 = Bank 2 SDRAM 0 = Bank 2 Non-SDRAM B3SD Select Bank 3 SDRAM. 1 = Bank 3 SDRAM 0 = Bank 3 Non-SDRAM 5–4 EPBR External Port Bus Priority.
Page 661 Register Reference Table A-3. EPCTL Register Bit Descriptions (Cont’d) Name Description 18–15 DATE Data Enable. In no pack mode of the sdram/ami memory controller, masks those bits of the data lane with zeros. The data lane is 8 bits. The 32-bit data bus has four data lanes. DATA31–0 is mapped to {dl3, dl2, dl1, dl0} For example, If DATE is 1010, then dl3 and dl1 are masked with zeros.
Page 662: External Port Dma Control Registers (Dmacx
External Port Registers External Port DMA Control Registers (DMACx) registers control the DMA function of their respective DMA DMAC0–1 channels. These registers are shown in Figure A-5 and described in Table A-4. DMAC0 (0x180B) DMAC1 (0x180C) 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 Reserved DIRS...
Page 663 Register Reference Table A-4. External Port DMA Register Bit Descriptions Name Description DMAEN DMA Enable. 0 = External port channel x DMA is disabled 1 = Enable External port DMA for channel x DMADR DMA Direction 0 = Write to internal memory (external reads) 1 = Read from internal memory (external writes) Note: If delay line DMA is enabled then the DMADR bit doesn’t have any effect.
Page 664 External Port Registers Table A-4. External Port DMA Register Bit Descriptions (Cont’d) Name Description DMA Chaining Status (read-only). 0 = DMA chain loading is not active 1 = DMA chain loading is active Tap List Loading Status (read-only). 0 = Tap list loading is not active 1 = Tap list loading is active Delay Line Write Pointer Write Back Status (read-only).
Page 665: Ami Control Registers (Amictlx
Register Reference AMI Control Registers (AMICTLx) registers control the mode of operations for the four banks AMICTL0–3 of external memory. These registers are shown in Figure A-6 described in Table A-5. AMICTL0 (0x1804) AMICTL1 (0x1805) 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 AMICTL2 (0x1806) AMICTL3 (0x1807)
Page 666 External Port Registers Table A-5. AMICTLx Register Bit Descriptions Name Description AMIEN AMI Enable. 0 = AMI is disabled 1 = AMI is enabled 2–1 External Data Bus Width. 00 = 8 bits 01 = 16 bits 10 = 32 bits 11 = Reserved PKDIS Disable Packing/Unpacking.
Page 667 Register Reference Table A-5. AMICTLx Register Bit Descriptions (Cont’d) Name Description 16–14 Bus Idle Cycle. Idle cycle to be inserted whenever read from exter- nal memory is followed by a write to external memory – to avoid contention. 'IC' EP clock cycles are ensured between a read to write.
Page 668: Ami Status Register (Amistat
External Port Registers AMI Status Register (AMISTAT) This 32-bit, read-only register provides status information for the AMI interface and can be read at any time. This register is shown in Figure A-7. AMISTAT (0x180A) 15 14 13 12 11 10 AMIMS Reserved (Bits 31–4) AMI Master...
Page 669: Sdram Control Register (Sdctl
Register Reference SDRAM Control Register (SDCTL) The SDRAM memory control register includes all programmable parame- ters associated with the SDRAM access timing and configuration. This 32-bit register is located at address 0x1800 and is shown in Figure A-8 and described in Table A-6.
Page 670 External Port Registers 15 14 13 12 11 10 SDCL SDSRF CAS Latency SDRAM Self Refresh Enable 00, 01=Reserved 1=Starts self refresh mode 10=2 cycles, 11=3 cycles 0=No effect DSDCTL SDPSS Disable SDCLK and Control Sig- SDRAM Power-up Sequence Start nals 1=Enable power-up on next 1=Disable...
Page 671 Register Reference Table A-6. SDRAM Control Register Bit Descriptions (Cont’d) Name Description 7–4 SDTRAS tRAS Specification. Based on the system clock frequency and the timing specifications of the SDRAM used. Programmed parame- ters apply to all four banks in the external memory. See t on page 3-35.
Page 672 External Port Registers Table A-6. SDRAM Control Register Bit Descriptions (Cont’d) Name Description X16DE SDRAM External Data Path Width. Selects whether the SDRAM interface is 32 or 16 bits wide. If X16DE = 0, DATA31–0 should be connected to the SDRAM. If X16DE = 1, DATA15–0 should be connected to the SDRAM and 16 to 32-bit packing is performed.
Page 673 Register Reference Table A-6. SDRAM Control Register Bit Descriptions (Cont’d) Name Description 29–27 SDRAW Row Address Width. 000=8, 001=9 010=10, 011=11 100=12, 101=13 110=14, 111=15 PGSZ 128 Program the SDRAM Controller for Page Size of 128 Words. This bit allows programs to configure the SDC for a page size of 128 words (7 bits) which supports most available 32 Mb SDRAMs.
Page 674: Sdram Control Status Register (Sdstat
External Port Registers SDRAM Control Status Register (SDSTAT) The SDRAM control status register provides information on the state of the SDC. This information can be used to determine when it is safe to alter SDC control parameters or as a debug aid. This register is located at address 0x1803 and is shown in Figure A-10.
Page 675 Register Reference 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 SDRRC (0x1802) SDROPT Reserved SDRAM Optimization 1=Enable SDMODIFY 0=Disable Used for Predictive Addressing (0–15) 15 14 13 12 11 10 Reserved RDIV Delay (SDCLK cycles) between consecutive refresh counter time-outs Figure A-11.
Page 676: Memory-To-Memory Dma Register
Memory-to-Memory DMA Register Memory-to-Memory DMA Register The memory-to-memory (MTM) DMA register ( ) allows programs MTMCTL to transfer blocks of 64-bit data from one internal memory location to another. This transfer method uses two DMA channels, one for reading data and one for writing data. These transfers are controlled using the register shown in Figure A-12.
Page 677: Serial Port Registers
Register Reference Serial Port Registers The following section describes serial port (SPORT) registers. SPORT Serial Control Registers (SPCTLx) The SPORT serial control registers’ addresses are: SPCTL0 – 0xC00 SPCTL1 – 0xC01 SPCTL2 – 0x400 SPCTL3 – 0x401 SPCTL4 – 0x800 SPCTL5 –...
Page 678 Serial Port Registers Table A-7. SPORT Operation Modes Bits OPMODE LAFS FRFS MCEA MCEB SLENx Operating Modes Standard DSP Serial Mode 0, 1 3-32 S (Tx/Rx on Left Channel 8-32 First) S (Tx/Rx on Right Channel 8-32 First) Packed I S Mode A Channel 3-32 Packed I...
Page 679 Register Reference SPCTL0 (0xC00) SPCTL1 (0xC01) SPCTL2 (0x400) SPCTL3 (0x401) SPCTL4 (0x800) SPCTL5 (0x800) SPCTL6 (0x4800) SPCTL7 (0x4801) 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 DXS_A Data Buffer Channel A Status Active Low Frame Sync 11=Full, 10=Partially Full, 00=Empty 1=Active low 0=Active high...
Page 680 Serial Port Registers SPCTL0 (0xC00) SPCTL1 (0xC01) SPCTL2 (0x400) SPCTL3 (0x401) SPCTL4 (0x800) SPCTL5 (0x801) SPCTL6 (0x4800) SPCTL7 (0x4801) 15 14 13 12 11 10 DIFS SPEN_A Data Independent TX FS SPORT Enable A (if SPTRAN=1) or RX FS (if 1=Enable SPTRAN=0) 0=Disable...
Page 681 Register Reference SPCTL0 (0xC00) SPCTL1 (0xC01) SPCTL2 (0x400) SPCTL3 (0x401) SPCTL4 (0x800) SPCTL5 (0x801) SPCTL6 (0x4800) SPCTL7 (0x4801) 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 DXS_A FRFS Data Buffer Channel A Status Table 5-1 on page 5-11 11=Full, 10=Partially Full, 00=Empty LAFS...
Page 682 Serial Port Registers SPCTL0 (0xC00) SPCTL1 (0xC01) SPCTL2 (0x400) SPCTL3 (0x401) SPCTL4 (0x800) SPCTL5 (0x801) SPCTL6 (0x4800) SPCTL7 (0x4801) 15 14 13 12 11 10 DIFS SPEN_A Data Independent Frame Sync SPORT Enable A 1=Data independent 1=Enable 0=Data dependent 0=Disable Reserved Reserved OP MODE...
Page 683 Register Reference SPCTL0 (0xC00) SPCTL1 (0xC01) SPCTL2 (0x400) SPCTL3 (0x401) SPCTL4 (0x800) SPCTL5 (0x801) SPCTL6 (0x4800) SPCTL7 (0x4801) 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 DXS_A LMFS Data Buffer Channel A Status Active Low Multichannel Frame 11=Full 10=Partially full 00=Empty Sync...
Page 684 Serial Port Registers SPCTL0 (0xC00) SPCTL1 (0xC01) SPCTL2 (0x400) SPCTL3 (0x401) SPCTL4 (0x800) SPCTL5 (0x801) SPCTL6 (0x4800) SPCTL7 (0x4801) 15 14 13 12 11 10 Reserved Reserved DTYPE IMFS Data Type Internally Generated Multichannel 00=Right-justify, fill MSB with 0’s Frame Sync 01=Right-justify, sign-extend MSB 1=Internal frame sync 10=Compand υ-law...
Page 685 Register Reference Table A-8. SPCTLx Register Bit Descriptions Name Description SPEN_A Enable Channel A Serial Port. 0 = Serial port A channel disabled 1 = Serial port A channel enabled This bit is reserved when the SPORT is in packed I S and multichan- nel modes.
Page 686 Serial Port Registers Table A-8. SPCTLx Register Bit Descriptions (Cont’d) Name Description CKRE Clock Rising Edge Select. Determines clock signal to sample data and the frame sync selection. 0 = Falling edge 1 = Rising edge CKRE is reserved when the SPORT is in I S and left-justified sample pair modes.
Page 687 Register Reference Table A-8. SPCTLx Register Bit Descriptions (Cont’d) Name Description SDEN_B Enable Channel B Serial Port DMA. 0 = Disable serial port channel B DMA 1 = Enable serial port channel B DMA SCHEN_B Enable Channel B Serial Port DMA Chaining. 0 = Disable serial port channel B DMA chaining 1 = Enable serial port channel B DMA chaining FS_BOTH...
Page 688: Sport Multichannel Control Registers (Spmctlx
Serial Port Registers Table A-8. SPCTLx Register Bit Descriptions (Cont’d) Name Description DERR_A Channel A Error Status (sticky, read-only). Indicates if the serial (TUVF_A or transmit operation has underflowed or a receive operation has over- ROVF_A) flowed in the channel A data buffer. 31–30 DXS_A Channel A Data Buffer Status (read-only).
Page 689 Register Reference SPMCTL0 (0xC04) SPMCTL1 (0xC17) SPMCTL2 (0x404) SPMCTL3 (0x417) SPMCTL4 (0x804) SPMCTL5 (0x817) SPMCTL6 (0x4804) SPMCTL7 (0x4817) 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 DMACHSxB SPORTx Channel B Status CHNL DMA Chaining Status Current Channel Status x = 0,2,4,6 (read-only)
Page 690 Serial Port Registers Table A-9. SPMCTLx Register Bit Descriptions Name Description MCEA Multichannel Mode Enable. Standard and multichannel modes only. One of two configuration bits that enable and disable mul- tichannel mode on serial port channels. See OPMODE bit on page A-37.
Page 691: Sport Transmit Buffer Registers (Txspx
Register Reference Table A-9. SPMCTLx Register Bit Descriptions (Cont’d) Name Description 22–16 CHNL Current Channel Selected (read-only, sticky). Identify the cur- rently selected transmit channel slot (0 to 127). MCEB Multichannel Enable, B Channels. 0 = Disable 1 = Enable 27–24 DMASxy DMA Status.
Page 692: Sport Receive Buffer Registers (Rxspx
Serial Port Registers SPORT Receive Buffer Registers (RXSPx) The 32-bit registers hold the input data from serial port receive RXSPx operations. The reset value for these registers is undefined. For more information on how receive buffers work, see “Transmit and Receive Data Buffers (TXSPxA/B, RXSPxA/B)”...
Page 693: Sport Count Registers (Spcntx
Register Reference • Bits 31–16 are . These bits select the frame sync divisor for FSDIV internally-generated as follows: SCLK -------------- - 1 – FSDIV 31 30 29 28 27 26 24 23 22 21 20 19 18 17 16 FSDIV Frame Sync Divisor 15 14 13 12 11 10...
Page 694: Sport Active Channel Select Registers (Spxcsy
Serial Port Registers SPORT Active Channel Select Registers (SPxCSy) Each bit, 31–0, set (= 1) in one of the four registers corresponds to SPxCSy the active channel, 127–0, on a multichannel mode serial port. When the registers activate a channel, the serial port transmits or receives the SPxCSy word in that channel’s position of the data stream.
Page 695: Sport Compand Registers (Spxccsy
Register Reference SPORT Compand Registers (SPxCCSy) Each bit, 31–0, set (= 1) in one of the four registers corresponds SPxCCSy to a companded channel, 127–0, on a multichannel mode serial port. When the register activates companding for a channel, the serial SPxCCSy port applies the companding from the serial port’s selection to the...
Page 696: Sport Error Control Register (Sperrctlx
Serial Port Registers SPORT Error Control Register (SPERRCTLx) registers control and report the status of the interrupts SPERRCTLx generated by each SPORT (see Figure A-21). SPERRCTL0 (0xC18), SPERRCTL1 (0xC19) SPERRCTL2 (0x418), SPERRCTL3 (0x419) SPERRCTL4 (0x818), SPERRCTL5 (0x819) SPERRCTL6 (0x4818), SPERRCTL7 (0x4819) 15 14 13 12 11 10 DERRA_EN Reserved...
Page 697: Sport Error Status Register (Sperrstat
Register Reference SPORT Error Status Register (SPERRSTAT) In the ADSP-21367/8/9 and ADSP-2137x processors, there is one global interrupt status register, , that checks the status of SPORT SPERRSTAT interrupts. This read-only register is located at address 0x2300 and is 24 bits wide (see Figure A-22).
Page 698: Sport Dma Index Registers (Iispx
Serial Port Registers SPORT DMA Index Registers (IISPx) register is 19 bits wide. It holds an address and acts as a pointer IISPx to memory for a DMA transfer. For more information, see “I/O Proces- sor” on page 2-1. The addresses of the registers are: IISPx IISP0A –...
Page 699: Sport Dma Count Registers (Cspx
Register Reference SPORT DMA Count Registers (CSPx) registers are 16 bits wide and they hold the word count for a CSPx DMA transfer. For more information, see “I/O Processor” on page 2-1 The reset value for these registers is undefined. The addresses of the CSPx registers are: CSP0A –...
Page 700: Serial Peripheral Interface Registers
Serial Peripheral Interface Registers Serial Peripheral Interface Registers The following sections describe the registers associated with the two serial peripheral interfaces (SPIs). The SPI B port is routed through the DAI. SPI Control Registers (SPICTL, SPICTLB) The addresses of these registers are 0x1000 and 0x2800 ( ).
Page 701 Register Reference 15 14 13 12 11 10 SPICTL (0x1000) SPICTLB (0x2800) PACKEN TIMOD 8-Bit Packing Enable Transfer Initiation Mode 1=8- to 16-bit packing 00=Initiate transfer by read of 0=No packing receive buffer 01=Initiate transfer by write of SPIEN transmit buffer SPI System Enable 10=Enable DMA transfer mode 1=Enable...
Page 702 Serial Peripheral Interface Registers Table A-10. SPICTL Register Bit Descriptions Name Description 1–0 TIMOD Transfer Initiation Mode. Defines transfer initiation mode and interrupt generation. 00 = Initiate transfer by read of receive buffer. Interrupt active when receive buffer is full. 01 = Initiate transfer by write to transmit buffer.
Page 703 Register Reference Table A-10. SPICTL Register Bit Descriptions (Cont’d) Name Description CPHASE Clock Phase. Selects the transfer format. 0 = SPICLK starts toggling at the middle of 1st data bit. 1 = SPICLK starts toggling at the start of 1st data bit. CLKPL Clock Polarity.
Page 704: Spi Port Status (Spistat, Spistatb) Registers
Serial Peripheral Interface Registers Table A-10. SPICTL Register Bit Descriptions (Cont’d) Name Description ILPBK Internal Loop Back. 0 = No internal loopback 1 = Internal loopback enabled 31–21 Reserved SPI Port Status (SPISTAT, SPISTATB) Registers These registers’ addresses are 0x1002 and 0x2802 ( ).
Page 705 Register Reference Table A-11. SPISTAT Register Bit Descriptions Name Description SPIF SPI Transmit or Receive Transfer Complete. SPIF is set when an SPI single-word transfer is complete. Multimaster Error or Mode-Fault Error. MME is set in a master device when some other device tries to become the master. TUNF Transmission Error.
Page 706: Spi Port Flags Registers (Spiflg, Spiflgb
Serial Peripheral Interface Registers SPI Port Flags Registers (SPIFLG, SPIFLGB) These registers’ addresses are 0x1001 and 0x2801 ( ). The reset SPIFLGB value is 0x0F80.The registers, shown in Figure A-25 SPIFLG SPIFLGB and described in Table A-12, are used to enable individual SPI slave-select lines when the SPI is enabled as a master.
Page 707: Spi Receive Buffer Registers (Rxspi, Rxspib
Register Reference SPI Receive Buffer Registers (RXSPI, RXSPIB) These registers’ addresses are 0x1004 (for ) and 0x2804 (for RXSPI RXSPIB The reset values are undefined. These are 32-bit, read-only registers acces- sible by the core or DMA controller. At the end of a data transfer, RXSPIx is loaded with the data in the shift register.
Page 708: Spi Baud Rate Registers (Spibaud, Spibaudb
Serial Peripheral Interface Registers SPI Baud Rate Registers (SPIBAUD, SPIBAUDB) These registers’ addresses are 0x1005 (for ) and 0x2805 (for SPIBAUD ) and their reset values are undefined (Table A-13). These SPI SPIBAUDB registers are 16-bit, read-write registers that are used to set the bit transfer rate for a master device.
Page 709: Spi Dma Registers
Register Reference Table A-14. SPI Master Baud Rate Example (Cont’d) BAUDR SPI CLock Divide Factor Baud Rate for CCLK (Decimal Value) 13.9 MHz 10.4 MHz 32,767, (0x7FFF) 262136 1.3 KHz SPI DMA Registers There are ten SPI DMA-specific registers: • “SPI DMA Configuration Registers (SPIDMAC, SPIDMACB)”...
Page 710 Serial Peripheral Interface Registers SPI DMA Configuration Registers (SPIDMAC, SPIDMACB) These registers addresses are 0x1084 (for ) and 0x2884 (for SPIDMAC SPID- ) and their reset value is undefined. These 17-bit SPI registers, shown MACB Figure A-26 and described in Table A-15, are used to control DMA transfers.
Page 711 Register Reference Table A-15. SPIDMAC, SPIDMACB Register Bit Descriptions Name Description SPIDEN DMA Enable. 0 = Disable 1 = Enable SPIRCV DMA Write/Read. 0 = Memory write (SPI transmit) 1 = Memory read (SPI receive) INTEN Enable DMA Interrupt on Transfer. 0 = Disable 1 = Enable Reserved...
Page 712 Serial Peripheral Interface Registers Table A-15. SPIDMAC, SPIDMACB Register Bit Descriptions (Cont’d) Name Description 13–12 SPISx DMA FIFO Status. 00 = FIFO empty 11 = FIFO full 10 = FIFO partially full 01 = Reserved SPIERRS DMA Error Status. 0 = Successful DMA transfer 1 = Errors during DMA transfer SPIDMAS DMA Transfer Status.
Page 713: Input Data Port Registers
Register Reference SPI DMA Chain Pointer Registers (CPSPI, CPSPIB) The reset values for these registers are undefined. These 20-bit, read-write SPI registers contain the address of the next TCB when DMA chaining is enabled. Their addresses are 0x1083 (for ) and 0x2883 (for CPSPI CPSPIB Input Data Port Registers...
Page 714: Input Data Port Control Register 0 (Idp_Ctl0
Input Data Port Registers Input Data Port Control Register 0 (IDP_CTL0) Use the registers to configure and enable the input data port and IDP_CTL0 each of its channels. This register is shown in Figure A-27 and described Table A-16. The IDP may also be routed through the DAI using its bits. more information, see “DAI/DPI Registers”...
Page 715 Register Reference Table A-16. IDP_CTL0 Register Bit Descriptions Name Description 3–0 IDP_NSET Monitors number of FIFO entries where N > samples raises interrupt controller bit 8. IDP_BHD IDP Buffer Hang Disable. Reads of an empty FIFO or writes to a full FIFO make the core hang. This condi- tion continues until the FIFO has valid data (in the case of reads) or the FIFO has at least one empty location (in the case of writes).
Page 716: Input Data Port Control Register 1 (Idp_Ctl1
Input Data Port Registers Input Data Port Control Register 1 (IDP_CTL1) Use the register to configure and enable individual IDP chan- IDP_CTL1 nels. This register is shown in Figure A-28 and described in Table A-17. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDP_CTL1 (0x24B2) IDP_PINGx IDP_FFCLI...
Page 717: Input Data Port Fifo Register (Idp_Fifo
Register Reference Input Data Port FIFO Register (IDP_FIFO) This register (shown in Figure A-29) provides information about the out- put of the IDP FIFO. Normally, is used only to read and remove IDP_FIFO the top sample from the FIFO. However, the core may also write to this register.
Page 718: Input Data Port Dma Control Registers
Input Data Port Registers Table A-18. IDP_FIFO Register Bit Descriptions Name Description 2–0 IDP Channel Encoding. These bits indicate the serial input port channel number that provided this serial input data. Note: This information is not valid when data comes from the PDAP. LR_STAT Left/Right Channel Status.
Page 719: Idp_Dma_Mx
Register Reference Table A-19. IDP_DMA_Ix Registers (Cont’d) Register Address Reset State Description IDP_DMA_I6 0x2406 0x00000 IDP channel 6 DMA index register IDP_DMA_I7 0x2407 0x00000 IDP channel 7 DMA index register IDP_DMA_Mx Table A-20 provides information about the IDP DMA modifier registers. Table A-20.
Page 720: Input Data Port Ping-Pong Dma Registers
Input Data Port Registers Table A-21. IDP_DMA_Cx Registers (Cont’d) Register Address Reset State Description IDP_DMA_C3 0x2423 0x00000 IDP channel 3 DMA count register IDP_DMA_C4 0x2424 0x00000 IDP channel 4 DMA count register IDP_DMA_C5 0x2425 0x00000 IDP channel 5 DMA count register IDP_DMA_C6 0x2426 0x00000...
Page 721: Idp Ping-Pong Count Registers (Idp_Dma_Pcx
Register Reference Table A-22. IDP_DMA_IxA Registers (Cont’d) Register Address Reset State Description IDP_DMA_I7A 0x240F 0x00000 IDP channel 7 index A ping-pong DMA register IDP_DMA_I0B 0x2418 0x00000 IDP channel 0 index B ping-pong DMA register IDP_DMA_I1B 0x2419 0x00000 IDP channel 1 index B ping-pong DMA register IDP_DMA_I2B 0x241A 0x00000...
Page 722: Parallel Data Acquisition Port Control Register (Idp_Pp_Ctl
Input Data Port Registers Parallel Data Acquisition Port Control Register (IDP_PP_CTL) Setting enables either the 20 DAI pins or the IDP_PP_CTL[31] DATA31–8 pins to be used as a parallel input channel. These parallel words may be packed into 32-bit words for efficiency. The data then flows through the FIFO and is transferred by a dedicated DMA channel into the core’s memory, as with any IDP channel.
Page 723 Register Reference IDP_PP_CTL (0x24B1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDP_PDAP_EN IDP_P17_PDAPMASK IDP_PDAP_RESET IDP_P18_PDAPMASK IDP_PDAP_CLKEDGE IDP_P19_PDAPMASK IDP_PDAP_PACKINGX IDP_P20_PDAPMASK IDP_PORT_SELECT Reserved 15 14 13 12 11 10 IDP_P16_PDAPMASK IDP_P01_PDAPMASK IDP_P15_PDAPMASK IDP_P02_PDAPMASK IDP_P14_PDAPMASK IDP_P03_PDAPMASK IDP_P13_PDAPMASK...
Page 724 Input Data Port Registers Table A-24. IDP_PP_CTL Register Bit Descriptions (Cont’d) Name Description IDP_P05_PDAPMASK Parallel Data Acquisition Port Mask. 0 = Input data from DAI_05/DATA0 is masked 1 = Input data from DAI_05/DATA0 is unmasked IDP_P06_PDAPMASK Parallel Data Acquisition Port Mask. 0 = Input data from DAI_06/DATA1 is masked 1 = Input data from DAI_06/DATA1 is unmasked IDP_P07_PDAPMASK...
Page 725 Register Reference Table A-24. IDP_PP_CTL Register Bit Descriptions (Cont’d) Name Description IDP_P16_PDAPMASK Parallel Data Acquisition Port Mask. 0 = Input data from DAI_16/ADDR3 is masked 1 = Input data from DAI_16/ADDR3 is unmasked IDP_P17_PDAPMASK Parallel Data Acquisition Port Mask. 0 = Input data from DAI_17/ADDR4 is masked 1 = Input data from DAI_17/ADDR4 is unmasked IDP_P18_PDAPMASK Parallel Data Acquisition Port Mask.
Page 726: Pulse Width Modulation Registers
Pulse Width Modulation Registers Table A-24. IDP_PP_CTL Register Bit Descriptions (Cont’d) Name Description IDP_PDAP_RESET PDAP Reset. Setting this bit (=1) causes the PDAP reset circuit to strobe, then this bit is cleared auto- matically. This bit always returns a value of zero when read. IDP_PDAP_EN PDAP Enable.
Page 727: Pwm Global Status Register (Pwmgstat
Register Reference 15 14 13 12 11 10 PWMGCTL (0x3800) PWM_SYNCDIS3 PWM_EN0 PWM Group 3 Disable PWM Group 0 Enable PWM_SYNCEN3 PWM_DIS0 PWM Group 3 Enable PWM Group 0 Disable PWM_SYNCDIS2 PWM_EN1 PWM Group 2 Disable PWM Group 1 Enable PWM_SYNCEN2 PWM_DIS1 PWM Group 2 Enable...
Page 728: Pwm Control Register (Pwmctlx
Pulse Width Modulation Registers PWM Control Register (PWMCTLx) These registers, described in Table A-26, are used to set the operating modes of each PWM block. These registers also allow programs to disable interrupts from individual groups. These registers addresses are: PWMCTL0 —...
Page 729: Pwm Status Registers (Pwmstatx
Register Reference PWM Status Registers (PWMSTATx) These 16-bit read-only registers, described in Table A-27, report the sta- tus of the phase and mode for each PWM group. The addresses for these registers are: PWMSTAT0 — 0x3001 PWMSTAT1 — 0x3011 PWMSTAT2 — 0x3401 PWMSTAT3 —...
Page 730: Pwm Output Disable Registers (Pwmsegx
Pulse Width Modulation Registers PWM Output Disable Registers (PWMSEGx) These 16-bit read/write registers, described in Table A-28, control the output signals of the four PWM groups. The addresses for these registers are: PWMSEG0 — 0x3008 PWMSEG1 — 0x3018 PWMSEG2 — 0x3408 PWMSEG3 —...
Page 731: Pwm Polarity Select Registers (Pwmpolx
Register Reference PWM Polarity Select Registers (PWMPOLx) These registers, described in Table A-29, control the polarity of the four PWM groups which can be set to either active hi or active lo. The addresses for these registers are: PWMPOL0 — 0x300F PWMPOL1 —...
Page 732: Pwm Channel Duty Control Registers (Pwmax, Pwmbx
Pulse Width Modulation Registers PWM Channel Duty Control Registers (PWMAx, PWMBx) The duty cycle control registers, described in Table A-30, directly control the duty cycles of the two pairs of PWM signals. These 16-bit, read/write registers are located at addresses: PWMA0 —...
Page 733: Pwm Dead Time Registers (Pwmdtx
Register Reference Table A-31. PWMALx/PWMBLx Register Bit Descriptions Name Description 15–0 PWMALx Channel AL Duty Cycle. Program a two’s complement duty cycle with a value of 0x0000 through 0xFFFF. Default = 0 15–0 PWMBLx Channel BL Duty Cycle. Program a two’s complement duty cycle with a value of 0x0000 through 0xFFFF.
Page 734: Sony/Philips Digital Interface Registers
Sony/Philips Digital Interface Registers Sony/Philips Digital Interface Registers The following sections describe the registers that are used to configure, enable and report status information for the S/PDIF transceiver. Transmitter Control Register (DITCTL) The S/PDIF transmit control register ( ) is a 32-bit, read/write reg- DITCTL ister located at address 0x24A0.
Page 735 Register Reference 15 14 13 12 11 10 DIT_EN DIT_EXT_SYNCEN Transmitter Enable External Sync Enable 0=Transmitter disabled 0=Internal frame counter not 1=Transmitter enabled set to zero at the next LRCLK DIT_MUTE rising edge 1=Internal frame counter is Mute Serial Data Output set to zero at the next LRCLK 0=Not muted rising edge...
Page 736 Sony/Philips Digital Interface Registers Table A-33. DITCTL Register Bit Descriptions (Cont’d) Name Description 3–2 DIT_FREQ Frequency Multiplier. Sets the oversampling ratio to the fol- lowing: 00 = 256 x Frame sync 01 = 384 x Frame sync 10 = 512 x Frame sync 11 = 768 x Frame sync DIT_SCDF Transmit Single-Channel, Double-Frequency Enable.
Page 737: Left Channel Status For Subframe A Registers (Ditchanax
Register Reference Table A-33. DITCTL Register Bit Descriptions (Cont’d) Name Description DIT_USERS User Bits Status. This bit is high if user bits buffer has been written but data has not been transmitted completely. Reserved DIT_EXT_SYNCEN External Sync Enable. When this bit is set, the internal frame counter is set to zero at the next LRCLK rising edge.
Page 738: Right Channel Status For Subframe B Registers (Ditchanbx
Sony/Philips Digital Interface Registers Right Channel Status for Subframe B Registers (DITCHANBx) There are six channel status buffer registers associated with subframe B. These registers are listed with their locations in Table A-35. Table A-35. DITCHANBx Registers Register (Address) Bits 7–0 Bits 15–8 Bits 23–16 Bits 31–24...
Page 739: User Bits Buffer Registers For Subframe B Registers (Ditusrbitbx
Register Reference User Bits Buffer Registers for Subframe B Registers (DITUSRBITBx) There are six user bits buffer registers associated with subframe B (right channel). These registers are listed with their locations in Table A-37. Table A-37. DITUSRBITBx Registers Register (Address) Bits 7–0 Bits 15–8 Bits 23–16...
Page 740: Receiver Control Register (Dirctl
Sony/Philips Digital Interface Registers Receiver Control Register (DIRCTL) This 32-bit read/write register is used to set up error control and sin- gle-channel, double-frequency mode. The register is located at address 0x24A8. The register’s bits are shown in Figure A-34 and described in Table A-38.
Page 741 Register Reference Table A-38. DIRCTL Register Bit Descriptions Name Description 1–0 DIR_BIPHASE Parity Biphase Error Control. 00 = No action taken 01 = Hold last valid sample 10 = Replace invalid sample with zeros 11 = Reserved 3–2 DIR_LOCK Lock Error Control. 00 = No action taken 01 = Hold last valid sample 10 = Send zeros after the last valid sample...
Page 742: Receiver Status Register (Dirstat
Sony/Philips Digital Interface Registers Receiver Status Register (DIRSTAT) This 32-bit, read-only register is used to store the error bits. The error bits are sticky on read. Once they are set, they remain set until the register is read. This register also contains the lower byte of the 40-bit channel status information.
Page 743 Register Reference Table A-39. DIRSTAT Register Bit Descriptions Name Description DIR_NOAUDIOL Non-Audio Subframe Mode Channel 1. Based on SMPTE 337M. 0 = Not non-audio subframe mode 1 = Non-audio subframe mode, Channel 1 DIR_NOAUDIOR Non-Audio Subframe Mode Channel 2. Based on SMPTE 337M.
Page 744: Left Channel Status For Subframe A Register (Dirchanl
Sony/Philips Digital Interface Registers Left Channel Status for Subframe A Register (DIRCHANL) This register ( , described in Table A-40) is a 32-bit, read/write DIRCHANL register located at address 0x24AA. Table A-40. DIRCHANL Register Name Description 7–0 DIR_B1CHANL Channel status byte 1 for subframe A 15–8 DIR_B2CHANL Channel status byte 2 for subframe A...
Page 745: Sample Rate Converter Registers
Register Reference Sample Rate Converter Registers The sample rate converter (SRC) is composed of five registers which are described in the following sections. SRC Control Registers (SRCCTLx) These registers (read/write) control the operating modes, filters, and data formats used in the SRCs and are shown in Figure A-36 through Figure A-39...
Page 746 Sample Rate Converter Registers 15 14 13 12 11 10 SRCCTL0 (0x2490) SRC0_RESET SRC0_HARD_MUTE SRC0 Hard Mute Enable SRC0 Reset 1=Enabled 1=SRC enabled 0=Disabled 0=SRC disabled SRC0_MPHASE SRC0_AUTO_MUTE SRC0 Matched-Phase Mode SRC0 Auto Hard Mute 1=Enabled Enable (from SPDIF RX) 0=Disabled 1=Enabled 0=Disabled...
Page 747 Register Reference Table A-42. SRCCTL0 Register Bit Descriptions (Cont’d) Name Description 4–2 SRC0_SMODEIN Serial Input Format. Selects the serial input format for SRC 0 as follows. 000 = Default, format is left-justified 001 = I 010 = TDM 100 = 24-bit right-justified 101 = 20-bit right-justified 110 = 18-bit right-justified 111 = 16-bit right-justified...
Page 748 Sample Rate Converter Registers Table A-42. SRCCTL0 Register Bit Descriptions (Cont’d) Name Description 13–12 SRC0_LENOUT Output Word Length Select. Selects the serial output word length on SRC 0 as follows: 00 = 24 bits 01 = 20 bits 10 = 18 bits 11 = 16 bits Any word length less than 24 bits will have dither added to the unused LSBs if SRCx_DITHER is enabled (= 1).
Page 749 Register Reference Table A-42. SRCCTL0 Register Bit Descriptions (Cont’d) Name Description 23–22 SRC1_DEEMPHASIS De-emphasis Filter Select. Enables deemphasis on incoming audio data for SRC 1. 00 = No de-emphasis 01 = 33 kHz 10 = 44.1 kHz 11 = 48 kHz SRC1_SOFTMUTE Soft Mute.
Page 750 Sample Rate Converter Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRCCTL1 (0x2491) SRC3_HARD_MUTE SRC3_ENABLE SRC 3 Hard Mute Enable SRC 3 Enable 1=Enabled 1=SRC enabled 0=Disabled 0=SRC disabled SRC3_AUTO_MUTE SRC3_MPHASE SRC 3 Auto Hard Mute SRC 3 Matched-Phase Mode Enable (from SPDIF RX)
Page 751 Register Reference 15 14 13 12 11 10 SRCCTL1 (0x2491) SRC2_RESET SRC2_HARD_MUTE SRC 2 Hard Mute Enable SRC0, 2 Reset 1=Enabled 1=SRC enabled 0=Disabled 0=SRC disabled SRC2_MPHASE SRC2_AUTO_MUTE SRC 2 Matched-Phase Mode SRC 2 Auto Hard Mute 1=Enabled Enable (from SPDIF RX) 0=Disabled 1=Enabled 0=Disabled...
Page 752 Sample Rate Converter Registers Table A-43. SRCCTL1 Register Bit Descriptions (Cont’d) Name Description 4–2 SRC2_SMODEIN Serial Input Format. Selects the serial input format for SRC 2 as follows. 000 =Default, format is left-justified 001 = I 010 = TDM 100 = 24-bit right-justified 101 = 20-bit right-justified 110 = 18-bit right-justified 111 = 16-bit right-justified...
Page 753 Register Reference Table A-43. SRCCTL1 Register Bit Descriptions (Cont’d) Name Description 13–12 SRC2_LENOUT Output Word Length Select. Selects the serial output word length on SRC 2 as follows: 00 = 24 bits 01 = 20 bits 10 = 18 bits 11 = 16 bits Any word length less than 24 bits will have dither added to the unused LSBs if SRCx_DITHER is enabled (= 1).
Page 754 Sample Rate Converter Registers Table A-43. SRCCTL1 Register Bit Descriptions (Cont’d) Name Description 23–22 SRC3_DEEMPHASIS De-emphasis Filter Select. Enables de-emphasis on incoming audio data for SRC 3. 00 = No de-emphasis 01 = 33 kHz 10 = 44.1 kHz 11 = 48 kHz SRC3_SOFTMUTE Soft Mute.
Page 755: Src Mute Register (Srcmute
Register Reference SRC Mute Register (SRCMUTE) This read-write register, described in Table A-44, connects an SRCx mute input and output (when cleared) to automatically mute input while the SRC is initializing. Bit 0 controls , bit 1 controls , bit 2 controls SRC0 SRC1 , and bit 3 controls...
Page 756: Src Ratio Registers (Srcratx
Sample Rate Converter Registers SRC Ratio Registers (SRCRATx) These read-only status registers (shown in Figure A-40) report the mute and I/O sample ratio as follows: the register reports for SRC0 and SRCRAT0 1 and the register reports the mute and I/O sample ratio for SRCRAT1 SRC2 and 3.
Page 757: Dai/Dpi Registers
Register Reference DAI/DPI Registers The registers that are described in the following sections are contained within the digital audio and digital peripheral interfaces. The bits in these registers are used to enable the connection of peripherals and to view sta- tus of data transfers.
Page 758 DAI/DPI Registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DAI_STAT (0x24B8) Reserved IDP_DMA0_STAT IDP_FIFOSZ IDP_DMA1_STAT Number of Valid Data in IDP FIFO IDP_DMA2_STAT Reserved IDP_DMA3_STAT IDP_DMA7_STAT IDP_DMA4_STAT IDP_DMA6_STAT DMA Active Status for IDP_DMA5_STAT IDP Channel 15 14 13 12 11 10...
Page 759: Dai Resistor Pull-Up Enable Register (Dai_Pin_Pullup
Register Reference Table A-45. DAI_STAT Register Bit Descriptions (Cont’d) Name Description 24–17 IDP_DMAx_STAT Input Data Port DMA Status. 0 = DMA is not active 1 = DMA is active 27–25 Reserved 31–28 IDP_FIFOSZ IDP FIFO Size. Number of samples in the IDP FIFO. DAI Resistor Pull-up Enable Register (DAI_PIN_PULLUP) This 20-bit, read/write register is shown in...
Page 760: Dai Pin Buffer Status Register (Dai_Pin_Stat
DAI/DPI Registers DAI Pin Buffer Status Register (DAI_PIN_STAT) This 20-bit, read-only register is shown in Figure A-43. Bits 19–0 of this register indicate the status of . Reads from bits 31–20 always DAI_PB[20:1] return 0. This register is updated at one-half the core clock rate. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DAI_PIN_STAT (0x24B9) DAI_PB17...
Page 761 Register Reference The DAI interrupt controller is configured using three registers. Each of the 32 interrupt lines can be independently configured to trigger based on the incoming signal’s rising edge, falling edge, both, or neither. Setting a bit in enables that interrupt level on the DAI_IRPTL_RE DAI_IRPTL_FE rising and falling edges, respectively.
Page 762 DAI/DPI Registers DAI_IRPTL_RE(0x2480) DAI_IRPTL_FE(0x2481) DAI_IRPTL_PRI(0x2484) DAI_IRPTL_H(0x2488) DAI_IRPTL_L(0x2489) DAI_IRPTL_HS(0x248C) DAI_IRPTL_LS(0x248D) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRU_EXTMISCA3_INT IDP_DMA6_INT SRU_EXTMISCA2_INT IDP_DMA7_INT SRU_EXTMISCA1_INT SRC0_MUTE_INT SRC1_MUTE_INT SRU_EXTMISCA0_INT SRC2_MUTE_INT SRU_EXTMISCB5_INT SRC3_MUTE_INT SRU_EXTMISCB4_INT ISRU_EXTMISCB0_INT SRU_EXTMISCB3_INT ISRU_EXTMISCB1_INT ISRU_EXTMISCB2_INT 15 14 13 12 11 10 IDP_DMA5_INT...
Page 763: Dpi Resistor Pull-Up Enable Register (Dpi_Pin_Pullup
Register Reference Table A-46. DAI Interrupt Registers (Cont’d) Register Description Address DAI_IRPTL_RE Rising Edge Interrupt Mask Register 0x2481 DAI_IRPTL_FE Falling Edge Interrupt Mask Register 0x2480 DPI Resistor Pull-up Enable Register (DPI_PIN_PULLUP) This 16-bit read/write register is shown in Figure A-45. Bits 13–0 of this register control the enabling/disabling 22.5 KΩ...
Page 764: Dpi Pin Buffer Status Register (Dpi_Pin_Stat
DAI/DPI Registers DPI Pin Buffer Status Register (DPI_PIN_STAT) This 16-bit, read-only register is shown in Figure A-46. Bits 13–0 of this register indicate the status of . Reads from bits 15–14 always DPI_PB[14:1] return 0. This register is updated at one-half the core clock rate. DPI_PIN_STAT (0x1C31) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved...
Page 765 Register Reference All of the DPI interrupt registers are used primarily to provide the status of the interrupt controller. These registers are shown in Figure A-47 listed in Table A-47. Note that for each of these registers the bit names and numbers are the same.
Page 766: Uart Control And Status Registers
UART Control and Status Registers UART Control and Status Registers The processor provides a set of PC-style, industry-standard control and status registers for each UART. These memory-mapped registers (MMRs) are byte-wide registers that are mapped as half-words with the most signif- icant byte zero-filled.
Page 767 Register Reference 15 14 13 12 11 10 UART0LCR (0x3C03) UART1LCR (0x4003) Reserved UARTWLS Word Length Select UARTDLAB 00=5-bit word(UARTWLS5) Divisor Latch Access 01=6-bit word(UARTWLS6) 1=Enable access to UARTxDLL and UARTxDLH 10=7-bit word(UARTWLS7) 0=Enable access to UARTxTHR, UARTxRBR, and 11=8-bit word(UARTWLS8) UART_IER UARTSTB UARTSB...
Page 768: Line Status Registers (Uartxlsr
UART Control and Status Registers Line Status Registers (UARTxLSR) The UART line status registers ( ) contain UART status informa- UARTxLSR tion as shown in Figure A-49. There are also shadow registers, , with the following addresses: (0x3C0A) and UARTxLSRSH UART0LSRSH (0x400A).
Page 769: Transmit Hold Registers (Uartxthr
Register Reference Transmit Hold Registers (UARTxTHR) In no pack mode (default), only the lower byte of these registers is used— all other bits are zero-filled. However in pack mode, both the high and low bytes are used. The are the 9th bit in 9-bit transmission TX9D RX9D mode.
Page 770: Receive Buffer Registers (Uartxrbr
UART Control and Status Registers Receive Buffer Registers (UARTxRBR) These read-only registers (shown in Figure A-51) are mapped to the same address as the write-only registers. To access UARTxTHR UARTxRBR bit in the register must be cleared. When the UARTDLAB UARTxLCR bit is cleared, writes to this address target the registers,...
Page 771: Interrupt Enable Registers (Uartxier
Register Reference Interrupt Enable Registers (UARTxIER) The UART interrupt enable registers ( ) are used to enable UARTxIER requests for system handling of empty or full states of UART data regis- ters. Unless polling is used as a means of action, the and/or UARTRBFIE bits in these registers are normally set.
Page 772: Interrupt Identification Registers (Uartxiir
UART Control and Status Registers Interrupt Identification Registers (UARTxIIR) For legacy reasons, the UART interrupt identification registers ( UARTxIIR shown in Figure A-53) still reflect the UART interrupt status. Legacy operation may require bundling all UART interrupt sources to a single interrupt channel and servicing them all by the same software routine.
Page 773: Divisor Latch Registers (Uartxdll, Uartxdlh
Register Reference Divisor Latch Registers (UARTxDLL, UARTxDLH) The bit rate is characterized by the system clock ( ) and the 16-bit SCLK divisor. The divisor is split into the UART divisor latch low byte register ) and the UART divisor latch high byte register ( UARTxDLL UARTxDLH both shown in...
Page 774: Scratch Registers (Uartxscr
UART Control and Status Registers Scratch Registers (UARTxSCR) The contents of the 8-bit UART scratch registers ( shown in UARTxSCR Figure A-55) is reset to 0x00. It is used for general-purpose data storage and does not control the UART hardware in any way. UART0SCR (0x3C07) UART1SCR (0x4007) 15 14 13 12 11 10...
Page 775: Uart Dma Registers
Register Reference Table A-48. UART Mode Register Bit Descriptions Name Description UARTPACK Packing Enable. 0 = No pack 1 = Packing enabled. Consecutive data words (example 0xAB and 0xCD) are packed as 0x00CD 00AB in the receiver, and 0x00CD 00AB is transmitted as two words of 0xAB and 0xCD successively from the transmitter.
Page 776: Dma Control Registers
UART Control and Status Registers DMA Control Registers (UARTxTXCTL, UARTxRXCTL) Use these registers (described in Table A-49 Table A-50) to enable DMA, DMA chaining, and to clear the transmit and receive buffers. The transmit and receive registers are read-write registers and their addresses are: UART0TXCTL –...
Page 777: Dma Status Registers
Register Reference DMA Status Registers (UARTxTXSTAT, UARTxRXSTAT) These read-only registers (described in Table A-51 Table A-52) pro- vide DMA status information and their addresses are: UART0TXSTAT – 0x3F05 UART1TXSTAT – 0x4305 UART0RXSTAT – 0x3E05 UART1RXSTAT – 0x4205 Table A-51. UARTxTXSTAT Register Bit Descriptions Name Description Reserved...
Page 778: Two Wire Interface Registers
Two Wire Interface Registers Apart from the DMA control and status registers there are index, modifier, count, and chain pointer registers for both the transmit and receive DMA channels. For more information on these regis- ters, see “Port, Buffer, and DMA Control Registers” on page 2-26, Table 2-13, “UART DMA Registers,”...
Page 779: Master Internal Time Register (Twimitr
Register Reference Table A-53. TWI Register Descriptions (Cont’d) Address Name Description 0x4488 RXTWI8 8-Bit FIFO Receive Register 0x448C RXTWI16 16-Bit FIFO Receive Register Master Internal Time Register (TWIMITR) The TWI control register ( , shown in Figure A-57 and described TWIMITR Table A-54) is used to enable the TWI module as well as to establish a...
Page 780: Clock Divider Register (Twidiv
Two Wire Interface Registers Table A-54. Master Internal Time Register Bit Descriptions Name Description 0–6 PRESCALE Prescale. The number of peripheral clock (PCLK) periods used in the generation of one internal time reference. The value of PRESCALE must be set to create an internal time reference with a period of 10 MHz.
Page 781: Slave Mode Control Register (Twisctl
Register Reference Table A-55. Clock Divider Register Bit Descriptions Name Description 7–0 CLKLOW Clock Low. Number of internal time reference periods the serial clock (SCL) is held low. Represented as an 8-bit binary value. 15–8 CLKHI Clock High. Number of internal time reference periods the serial clock (SCL) waits before a new clock low period begins (assuming a single master).
Page 782 Two Wire Interface Registers Table A-56. Slave Mode Control Register Bit Descriptions Name Description TWISEN Slave Enable. 0 = The slave is not enabled. No attempt is made to identify a valid address. If cleared during a valid transfer, clock stretching ceases, the serial data line is released and the current byte is not acknowledged.
Page 783: Slave Address Register (Twisaddr
Register Reference Slave Address Register (TWISADDR) The TWI slave mode address register ( , shown in Figure A-60) TWISADDR holds the slave mode address, which is the valid address that the slave-enabled TWI controller responds to. The TWI controller compares this value with the received address during the addressing phase of a transfer.
Page 784: Master Control Register (Twimctl
Two Wire Interface Registers Master Control Register (TWIMCTL) The TWI master mode control register ( , shown in Figure A-62 TWIMCTL and described in Table A-57) controls the logic associated with master mode operation. Bits in this register do not affect slave mode operation and should not be modified to control slave mode functionality.
Page 785 Register Reference Table A-57. Master Control Register Bit Descriptions Name Description TWIMEN Master Mode Enable. Clears itself at the completion of a transfer. This includes transfers terminated due to errors. 0 = Master mode functionality is disabled. If MEN is cleared during operation, the transfer is aborted and all logic associated with master mode transfers are reset.
Page 786 Two Wire Interface Registers Table A-57. Master Control Register Bit Descriptions (Cont’d) Name Description 13–6 TWIDCNT Data Transfer Count. Indicates the number of data bytes to transfer. As each data word is transferred, the data transfer count is decre- mented. When DCNT is zero, a STOP (or restart condition) is issued.
Page 787: Master Address Register (Twimaddr
Register Reference Master Address Register (TWIMADDR) During the addressing phase of a transfer, the TWI controller, with its master enabled, transmits the contents of the TWI master mode address register ( , shown in Figure A-63). When programming this regis- TWIMADDR ter, omit the read/write bit.
Page 788: Master Status Register (Twimstat
Two Wire Interface Registers Master Status Register (TWIMSTAT) The TWI master mode status register ( , shown in Figure A-64 TWIMSTAT and described in Table A-58) holds information during master mode transfers and at their conclusions. Generally, master mode status bits are not directly associated with the generation of interrupts but offer informa- tion on the current transfer.
Page 789 Register Reference Table A-58. Master Status Register Bit Descriptions Name Description TWIMPROG Master Transfer In Progress. 0 = Currently no transfer is taking place. This can occur once a transfer is complete or while an enabled master is waiting for an idle bus. 1 = A master transfer is in progress.
Page 790 Two Wire Interface Registers Table A-58. Master Status Register Bit Descriptions (Cont’d) Name Description TWIWERR Buffer Write Error. 0 = The current master receive has not detected a receive buffer write error. 1 = The current master transfer was aborted due to a receive buffer write error.
Page 791: Fifo Control Register (Twififoctl
Register Reference FIFO Control Register (TWIFIFOCTL) The TWI FIFO control register ( , shown in Figure A-65 TWIFIFOCTL described in Table A-59) affects only the FIFO and is not tied in any way with master or slave mode operation. TWIFIFOCTL (0x4428) 15 14 13 12 11 10 TWIBHD TWITXFLUSH...
Page 792 Two Wire Interface Registers Table A-59. TWIFIFOCTL Register Bit Descriptions Name Description TWITXFLUSH Transmit Buffer Flush. 0 = Normal operation of the transmit buffer and its status bits 1 = Flush the contents of the transmit buffer and update the status to indicate the buffer is empty.
Page 793: Fifo Status Register (Twififostat
Register Reference FIFO Status Register (TWIFIFOSTAT) The fields in the TWI FIFO status register ( , shown in TWIFIFOSTAT Figure A-66 and described in Table A-60) indicate the state of the FIFO buffers’ receive and transmit contents. The FIFO buffers do not discrimi- nate between master data and slave data.
Page 794 Two Wire Interface Registers Table A-60. FIFO Status Register Bit Descriptions Name Description 1–0 TWITXS Transfer FIFO Status. These read-only bits indicate the num- ber of valid data bytes in the FIFO buffer. The status is updated with each FIFO buffer write using the peripheral data bus or read access by the transmit shift register.
Page 795: Interrupt Source Register (Twiirptl
Register Reference Interrupt Source Register (TWIIRPTL) The TWI interrupt source register ( , shown in Figure A-67 TWIIRPTL described in Table A-61) contains information about functional areas requiring servicing. Many of the bits serve as an indicator to further read and service various status registers.
Page 796 Two Wire Interface Registers Table A-61. Interrupt Source Register Bit Descriptions Name Description TWISINIT Slave Transfer Initiated. 0 = A transfer is not in progress. An address match has not occurred since the last time this bit was cleared. 1 = The slave has detected an address match and a transfer has been initiated.
Page 797 Register Reference Table A-61. Interrupt Source Register Bit Descriptions (Cont’d) Name Description TWITXINT Transmit FIFO Service. 0 = No errors detected. 1 = The transmit FIFO buffer has one or two 8-bit locations avail- able to be written. If TWITXINT2 is 0, this bit is set each time TWITXS is updated to either 01 or 00.
Page 798: Interrupt Enable Register (Twiimask
Two Wire Interface Registers Interrupt Enable Register (TWIIMASK) The TWI interrupt enable register ( , shown in Figure A-68 TWIIMASK described in Table A-62) enables interrupt sources to assert the interrupt output. Each enable bit corresponds with one interrupt source bit in the TWI interrupt source register ( ).
Page 799 Register Reference Table A-62. Interrupt Mask Register Bit Descriptions Name Description TWISINIT Slave Transfer Initiate Interrupt Enable. 0 = The corresponding interrupt source is prevented from asserting the interrupt output. 1 = The corresponding interrupt source asserts the interrupt output. TWISCOMP Slave Transfer Complete Interrupt.
Page 800: 8-Bit Transmit Fifo Register (Txtwi8
Two Wire Interface Registers Table A-62. Interrupt Mask Register Bit Descriptions (Cont’d) Name Description TWITXINT Transmit FIFO Service Interrupt Enable. 0 = The corresponding interrupt source is prevented from asserting the interrupt output. 1 = The corresponding interrupt source asserts the interrupt output.
Page 801: 16-Bit Transmit Fifo Register (Txtwi16
Register Reference 16-Bit Transmit FIFO Register (TXTWI16) The TWI FIFO transmit 16-bit register ( , shown in Figure A-70) TXTWI16 holds a 16-bit data value written into the FIFO buffer. To reduce inter- rupt output rates and peripheral bus access times, a 16-bit transfer data access can be performed.
Page 802: 8-Bit Receive Fifo Register (Rxtwi8
Two Wire Interface Registers 8-Bit Receive FIFO Register (RXTWI8) The TWI FIFO receive data 8-bit register ( , shown in Figure A-71) RXTWI8 holds an 8-bit data value read from the FIFO buffer. Receive data is read from the corresponding receive buffer in a first-in first-out order. Although peripheral bus reads are 32 bits, a read access to can only RXTWI8...
Page 803: Precision Clock Generator Registers
Register Reference RXTWI16 (0x4484) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RCVDATA16[23:16] Byte1 15 14 13 12 11 10 RCVDATA16[7:0] Byte0 Figure A-72. 16-Bit Receive FIFO Register Precision Clock Generator Registers The precision clock generator (PCG) consists of four identical units.
Page 804 Precision Clock Generator Registers PCG_CTLA0 (0x24C0) PCG_CTLB0 (0x24C2) PCG_CTLC0 (0x24C6) PCG_CTLD0 (0x24C8) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FSAPHASE_HI ENCLKA Frame Sync A/B/C/D Phase Enable Clock A/B/C/D ENFSA Enable Frame Sync A/B/C/D 15 14 13 12 11 10 FSADIV Frame Sync A/B/C/D Divisor...
Page 805 Register Reference PCG_CTLA1 (0x24C1) PCG_CTLB1 (0x24C3) PCG_CTLC1 (0x24C7) PCG_CTLD1 (0x24C9) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CLKXSOURCE FSXPHASE_LO Clock A/B/C/D Source Frame Sync A/B/C/D Phase 9:0 FSXSOURCE Frame Sync A/B/C/D Source 15 14 13 12 11 10 CLKXDIV CLK A/B/C/D Divisor...
Page 806: Pcg Pulse Width Registers
Precision Clock Generator Registers PCG Pulse Width Registers Pulse width is the number of input clock periods for which the frame sync output is . Pulse width should be less than the divisor of the frame HIGH sync. The pulse width control registers are shown in Figure A-75 Figure A-76 and described in...
Page 807 Register Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PCG_PW (0x24C4) PCG_PW2 (0x24CA) Reserved STROBEB One Shot Frame INVFSB Sync B/D Active Low Frame Sync B/D 15 14 13 12 11 10 STROBEA One Shot Frame Reserved...
Page 808: Pcg Frame Synchronization Registers (Pcg_Syncx
Precision Clock Generator Registers PCG Frame Synchronization Registers (PCG_SYNCx) These registers, shown in Figure A-77, and Figure A-78 and described in Table A-67 Table A-68, allow programs to synchronize the clock frame syncs units with external frame syncs. For more information, see “Frame Sync”...
Page 809 Register Reference Table A-67. PCG_SYNC Register Bit Descriptions Name Description FSA_SYNC Enable synchronization of frame sync A with external frame sync. 0 = Frame sync disabled 1 = Frame sync enabled CLKA_SYNC Enable synchronization of clock A with external frame sync.
Page 810 Precision Clock Generator Registers PCG_SYNC2 (0x24CB) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FSD_SYNC FSD_SOURCE_IOP Enable frame sync D input source. Enable synchronization of 0 = XTAL buffer output selected for frame sync D FSD with external LRCLK 1 = EXT_CLKA_I selected for frame sync D CLKD_SYNC...
Page 811 Register Reference Table A-68. PCG_SYNC2 Register Bit Descriptions (Cont’d) Name Description FSC_SOURCE_IOP Enable frame sync C input source. 0 = XTAL buffer output selected for frame sync C 1 = EXT_CLKA_I selected for frame sync C FSD_SYNC Enable synchronization of frame sync D with external frame sync.
Page 812: Peripheral Interrupt Priority Control Registers
Peripheral Interrupt Priority Control Registers Peripheral Interrupt Priority Control Registers The following sections provide descriptions of the programmable inter- rupts that are used in the ADSP-21367/8/9 and ADSP-2137x processors. For information on the interrupt registers and the interrupt vector table, Appendix B, Interrupts.
Page 813 Register Reference Table A-69. Peripheral Interrupt Controller Routing Table Interrupt Vector Programmable Default Default Function Priority Name Address Interrupt Control Select Register (PICR) Value 0x2C PICR0[4:0] 0x00 DAI1I interrupt HIGHEST 0x30 PICR0[9:5] 0x01 SPIA interrupt 0x34 PICR0[14:10] 0x02 IOP GP timer-0 interrupt 0x38 PICR0[19:15] 0x03...
Page 814 Peripheral Interrupt Priority Control Registers Table A-69. Peripheral Interrupt Controller Routing Table (Cont’d) Interrupt Vector Programmable Default Default Function Priority Name Address Interrupt Control Select Register (PICR) Value UART0TxI 0x15 UART 0 transmit interrupt UART1TxI 0x16 UART 0 transmit interrupt TWII 0x17 Two wire interface interrupt...
Page 815: Peripheral Interrupt Priority0 Control Register (Picr0
Register Reference Peripheral Interrupt Priority0 Control Register (PICR0) This 32-bit, read/write register controls programmable peripheral inter- rupts 0–5 and the default sources shown in Figure A-79. This register is located at address 0x2200. The reset value of this register is 0x0A418820. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PICR0 (0x2200) RESET=0x0A418820...
Page 816: Peripheral Interrupt Priority1 Control Register (Picr1
Peripheral Interrupt Priority Control Registers Peripheral Interrupt Priority1 Control Register (PICR1) This register controls programmable peripheral interrupts 6–11 and the default sources shown in Figure A-80. This 32-bit, read/write register is located at address 0x2201. The reset value of this register is 0x16A4A0E6. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PICR1 (0x2201) RESET=0x16A4A0E6...
Page 817: Peripheral Interrupt Priority2 Control Register (Picr2
Register Reference Peripheral Interrupt Priority2 Control Register (PICR2) This register controls programmable peripheral interrupts 12–17 as well as the default sources shown in Figure A-81. This 32-bit, read/write register is located at address 0x2202. The reset value of this register is 0x2307B9AC.
Page 818: Peripheral Interrupt Priority3 Control
Power Management Control Register (PMCTL) Peripheral Interrupt Priority3 Control Register (PICR3) This register controls programmable peripheral interrupt 18 as shown in Figure A-82. This 32-bit, read/write register is located at address 0x2203. The reset value of this register is 0x00000012. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PICR3 (0x2203) RESET=0x00000012...
Page 819 Register Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PMCTL (0x2000) TIMEROFF CRAT0 Timer Enable/Disable PLL Clock Ratio Bit 0 SPIOFF CRAT1 Shut Down Clock to SPIs PLL Clock Ratio Bit 1 SP45POFF SDCKR Shut Down Clock to SPORT4–5...
Page 820 Power Management Control Register (PMCTL) Table A-70. PMCTL Register Bit Descriptions Name Description 5–0 PLLM PLL Multiplier (read/write). PLLM = 0 PLL multiplier = 64 0<PLLM<63 PLL multiplier = PLLM CLK_CFG1–0 reset value 00 = 0000110 01 = 100000 10 = 010000 11 = 000110 7–6 PLLDx...
Page 821 Register Reference Table A-70. PMCTL Register Bit Descriptions (Cont’d) Name Description UART1OFF UART1 Clock Enable. 0 = UART1 is in normal mode 1 = Shut down clock to UART1 PLLBP PLL Bypass Mode Indication. 0 = PLL is in normal mode 1 = Put PLL in bypass mode Reset value = 0 CRAT0...
Page 822 Power Management Control Register (PMCTL) Table A-70. PMCTL Register Bit Descriptions (Cont’d) Name Description SRCOFF SRC Off. 0 = SRC, SPDIF, SRU, PCG, DAI, IDP, PDAP blocks in nor- mal mode 1 = Turn OFF clock to SRC, SPDIF, SRU, PCG, DAI, IDP, PDAP PPPDN External Port Enable/Disable.
Page 823: Hardware Breakpoint Control Register
Register Reference Hardware Breakpoint Control Register register controls how breakpoints are used if bit 25, , is BRKCTL UMODE set. This user-accessible register, shown in Figure A-84 Figure A-85 and described in Table A-71, is located at address 0x30025. The register is a 32-bit, memory-mapped I/O register. The core can write into this register.
Page 824 Hardware Breakpoint Control Register 15 14 13 12 11 10 BRKCTL (0x30025) (Bits 15-0) NEGIA3 PA1MODE Negate Instruction Address PA1 Triggering Mode Breakpoint #3 00=Breakpoint disabled 1=Enable breakpoint 01=WRITE access 0=Disable breakpoint 10=READ access NEGIA2 11=Any access Negate Instruction Address DA1MODE Breakpoint #2 DA1 Triggering Mode...
Page 825 Register Reference Table A-71. BRKCTL Register Bit Descriptions Name Description 1–0 PA1MODE PA1Triggering Mode. 00 = Breakpoint disabled 01 = WRITE access 10 = READ access 11 = Any access 3–2 DA1MODE DA1 Triggering Mode. 00 = Breakpoint disabled 01 = WRITE access 10 = READ access 11 = Any access 5–4...
Page 826 Hardware Breakpoint Control Register Table A-71. BRKCTL Register Bit Descriptions (Cont’d) Name Description NEGIA1 Negate Instruction Address Breakpoint #1. 0 = Do not negate breakpoint 1 = Negate breakpoint NEGIA2 Negate Instruction Address Breakpoint #2. For more information, see NEGPA1 bit description. NEGIA3 Negate Instruction Address Breakpoint #3.
Page 827: Enhanced Emulation Status Register
Register Reference Table A-71. BRKCTL Register Bit Descriptions (Cont’d) Name Description UMODE User Mode Breakpoint Functionality Enable. Address Break- point 3. 0 = Disable user controlled breakpoint 1 = Enable user controlled breakpoint ENBIOY IOY Breakpoint Enable. 0 = Disable IOY breakpoint 1 = Enable IOY breakpoint 0 ENBIOX IOX Breakpoint Enable.
Page 828 Enhanced Emulation Status Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EEMUSTAT (0x30021) STATIOY Reserved IOY Memory Breakpoint Status 0= No breakpoint occurs 1= Breakpoint occurs 15 14 13 12 11 10 EEMUINENS STATPA EEMUIN Interrupt Enable...
Page 829 Register Reference Table A-72. EEMUSTAT Register Bit Descriptions Name Description STATPA Program Memory Data Breakpoint Hit. 0 = No program memory breakpoint occurs 1 = Program memory breakpoint occurs STATDA0 Data Memory Breakpoint Hit. 0 = No data memory #0 breakpoint occurs 1 = Data memory #0 breakpoint occurs STATDA1 Data Memory Breakpoint Hit...
Page 830 Enhanced Emulation Status Register Table A-72. EEMUSTAT Register Bit Descriptions (Cont’d) Name Description EEMUOUTFULL Enhanced Emulation EEMUOUT FIFO Status. 0 = EEMUOUT FIFO is not full 1 = EEMUOUT FIFO full EEMUINFULL Enhanced Emulation EEMUIN Register Status. 0 = EEMUIN register is empty 1 = EEMUIN register full EEMUENS Enhanced Emulation Feature Enable.
Page 831: Interrupt Vector Tables
B INTERRUPTS This chapter provides a complete listing of the registers that are used to configure and control interrupts. Table B-2 shows all the processor inter- rupts, listed according to their bit position in the , and IRPTL LIRPTL registers. Also shown are the addresses of the interrupt vectors. Each IMASK vector is separated by four memory locations.
Page 832 Interrupt Vector Tables Note that the SPI has only one interrupt for both transmit and receive operations and each serial port (SPORT) has only one interrupt for both transmit and receive. Table B-2. Interrupt Vector Addresses Interrupt Register IRPTL/ Vector Interrupt Function Number...
Page 833 Interrupts Table B-2. Interrupt Vector Addresses (Cont’d) Interrupt Register IRPTL/ Vector Interrupt Function Number LIRPTL/ Address Name MASK Bit# LIRPTL 0x4C Programmable interrupt 8 (SP4) LIRPTL 0x50 Programmable interrupt 9 (EPDMA0) LIRPTL 0x54 P10I Programmable interrupt 10 (GPTMR1) LIRPTL 0x58 P11I Programmable interrupt 11 (SP7) LIRPTL...
Page 834: Interrupt Priorities
Interrupt Vector Tables Table B-2. Interrupt Vector Addresses (Cont’d) Interrupt Register IRPTL/ Vector Interrupt Function Number LIRPTL/ Address Name MASK Bit# IRPTL 0xA0 SFT2I User software interrupt 2 IRPTL 0xA4 SFT3I User software interrupt 3 LOWEST PRIORITY 1 If configured for internal ROM boot mode, then the base address for the interrupt vector table is the starting address of internal ROM or 0x00080000.
Page 835 Interrupts Table B-3. Interrupt Selection Values (Cont’d) Interrupt Source Interrupt Select Comments Value (5-Bits) GPTMR1I 0x0A Genera-purpose Timer 1 interrupt SP7I 0x0B Serial port 7 interrupt 0x0C DAI low priority interrupt EP1I 0x0D External port channel 1 interrupt 0x0E DPI interrupt MTMDMAI 0x0F Memory-to-memory DMA interrupt...
Page 836: Interrupt Registers
Interrupt Registers Interrupt Registers This section provides information on the registers that are used to config- ure and control interrupts. These registers are: • “Interrupt Register (LIRPTL)” on page B-6 • “Interrupt Latch Register (IRPTL)” on page B-13 • “Interrupt Mask Register (IMASK)” on page B-18 •...
Page 837 Interrupts 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LIRPTL P12IMSK Reserved Programmable Interrupt 12 P18IMSKP Mask (DAI1 Interrupt Mask) Programmable Interrupt 18 Mask P13IMSK Pointer (SPI B Interrupt Mask Pointer) Programmable Interrupt 13 Mask (EPDMA1 Interrupt P17IMSKP Programmable Interrupt 17 Mask Pointer...
Page 838 Interrupt Registers LIRPTL 15 14 13 12 11 10 P11IMSK Programmable Interrupt 11 Programmable Interrupt 6 Mask (SPORT7 Interrupt Mask) (SPORT0 Interrupt 0x44) P10IMASK Programmable Interrupt 10 Mask Programmable Interrupt 7 (General-purpose IOP Timer1 (SPORT2 Interrupt 0x48) Interrupt Mask) P9IMSK Programmable Interrupt 8 Programmable Interrupt 9 Mask (SPORT4 Interrupt 0x4C)
Page 839 Interrupts Table B-4. LIRPTL Register Bit Descriptions (Cont’d) Name Description P8I (SP4I) Programmable Interrupt 8 (SPORT 4 Interrupt). Indicates if an SP4I interrupt is latched and is pending (if set, = 1), or no SP4I is pending (if cleared, = 0). An SP4I interrupt occurs two cycles after the last bit of an input/output serial word is latched into/from RXSP4A/TXSP4A, RXSP4B/TXSP4B.
Page 840 Interrupt Registers Table B-4. LIRPTL Register Bit Descriptions (Cont’d) Name Description P18I (SPIB) Programmable Interrupt 18 (SPI B Interrupt). Indicates if an SPIB interrupt is latched and pending (if set, = 1), or no SPIBI interrupt is pending (if cleared, = 0). P6IMSK Programmable Interrupt Mask 6 (SPORT0 Interrupt (SP0IMSK)
Page 841 Interrupts Table B-4. LIRPTL Register Bit Descriptions (Cont’d) Name Description P18IMSK Programmable Interrupt Mask 18 (SPI Interrupt Mask Sec- (SPIBMSK) ondary SPI Port). Unmasks the SPIB interrupt (if set, = 1), or masks the SPIB interrupt (if cleared, = 0). P6IMSKP Programmable Interrupt Mask Pointer 9 (SPORT0 Inter- (SP0IMSKP)
Page 842 Interrupt Registers Table B-4. LIRPTL Register Bit Descriptions (Cont’d) Name Description P13IMASKP Programmable Interrupt 13 Mask Pointer (External Port (EPDMA1IMSKP) DMA Channel 1 Interrupt Mask Pointer). When the processor is servicing another interrupt, this bit indicates if the EPDMA1I is unmasked (if set, = 1) or masked (if cleared, = 0).
Page 843: Interrupt Latch Register (Irptl
Interrupts Interrupt Latch Register (IRPTL) register is a non-memory-mapped, universal, system register IRPTL ). The reset value for this register is 0x0000 0000. The Ureg Sreg register indicates latch status for interrupts. Figure B-3, Figure B-4 IRPTL Table B-5 provide bit definitions for the register.
Page 844 Interrupt Registers 15 14 13 12 11 10 IRPTL (Bits 15-0) Programmable Interrupt 4 EMUI (SPORT 3 Interrupt 0x3C) Emulator Interrupt (Interrupt Vector Address 0x00) Programmable Interrupt 3 (SPORT RSTI 1 Interrupt 0x38) Reset (Reset 0x04) Programmable Interrupt 2 (Gen- IICDI eral-Purpose IOP Timer 0 Illegal Input Condition...
Page 845 Interrupts Table B-5. Interrupt Latch (IRPTL) Register Bit Descriptions (Cont’d) Name Description IICDI Illegal Input Condition Detected Interrupt. Indicates if an IICDI is latched and is pending (if set, = 1), or no IICDI is pending (if cleared, = 0). An IICDI occurs when a true results from the logical Oring of the illegal I/O processor register access (IIRA) and unaligned 64-bit memory access bits in the STKYx registers.
Page 846 Interrupt Registers Table B-5. Interrupt Latch (IRPTL) Register Bit Descriptions (Cont’d) Name Description IRQ1I IRQ1 Hardware Interrupt. Indicates if an IRQ1I is latched and is pending (if set, = 1), or no IRQ1I is pending (if cleared, = 0). An IRQ1I occurs when an external device asserts the FLAG1 pin config- ured as IRQ1.
Page 847 Interrupts Table B-5. Interrupt Latch (IRPTL) Register Bit Descriptions (Cont’d) Name Description P14I (DPI) Programmable Interrupt 14. Indicates if a DPI interrupt is latched and is pending (if set, = 1), or no DPI interrupt is pending (if cleared, = 0). P15I Programmable Interrupt 15 (MTMDMA Interrupt).
Page 848: Interrupt Mask Register (Imask
Interrupt Registers Table B-5. Interrupt Latch (IRPTL) Register Bit Descriptions (Cont’d) Name Description EMULI Emulator (Lower Priority) Interrupt. Indicates if an EMULI is latched and is pending (if set, = 1), or no EMULI is pending (if cleared, = 0). An EMULI occurs on reset and when an external device asserts the EMU pin.
Page 849 Interrupts Table B-6. IMASK Register Bit Descriptions Name Description EMUI Emulator Interrupt. This bit is set to 1 (unmasked). An EMUI occurs on reset and when an external device asserts the EMU pin. RSTI Reset Interrupt. This bit is set to 1 (unmasked). An RSTI occurs on reset as an external device asserts the RESET pin.
Page 850 Interrupt Registers Table B-6. IMASK Register Bit Descriptions (Cont’d) Name Description IRQ1I IRQ1 Hardware Interrupt. Unmasks the IRQ1I interrupt (if set, = 1), or masks the IRQ1I interrupt (if cleared, = 0). An IRQ1I occurs when an external device asserts the FLAG1 pin configured as IRQ1. IRQ0I IRQ0 Hardware Interrupt.
Page 851 Interrupts Table B-6. IMASK Register Bit Descriptions (Cont’d) Name Description CB7I DAG1 Circular Buffer 7 Overflow Interrupt. Unmasks the CB7I inter- rupt (if set, = 1), or masks the CB7I interrupt (if cleared, = 0). A circu- lar buffer overflow occurs when the DAG circular buffering operation increments the I register past the end of the buffer.
Page 852: Interrupt Mask Pointer Register (Imaskp
Interrupt Registers Interrupt Mask Pointer Register (IMASKP) register is a non-memory-mapped, universal, system register IMASKP ). The reset value for this register is 0x0000 0000. Each bit Ureg Sreg in the register corresponds to a bit with the same name in the IMASKP registers.
Page 853 Interrupts Table B-7. IMASKP Register Bit Descriptions Name Description EMUI Emulator Interrupt. When the processor is servicing another interrupt, this bit indicates if the EMUI interrupt is unmasked (if set, = 1), or masked (if cleared, = 0). An EMUI occurs on reset and when an external device asserts the EMU pin.
Page 854 Interrupt Registers Table B-7. IMASKP Register Bit Descriptions (Cont’d) Name Description BKPI Hardware Breakpoint Interrupt. When the processor is servicing another interrupt, this bit indicates if the BKPI interrupt is unmasked (if set, = 1), or masked (if cleared, = 0). Reserved IRQ2I IRQ2 Hardware Interrupt.
Page 855 Interrupts Table B-7. IMASKP Register Bit Descriptions (Cont’d) Name Description SP3I SPORT 3 Interrupt. When the processor is servicing another interrupt, this bit indicates if the SP3I interrupt is unmasked (if set, = 1), or masked (if cleared, = 0). An SP3I interrupt occurs two cycles after the last bit of an input/output serial word is latched into/from RXSP3A/TXSP3A, or RXSP3B/TXSP3B.
Page 856 Interrupt Registers Table B-7. IMASKP Register Bit Descriptions (Cont’d) Name Description FLTUI Floating-Point Underflow Interrupt. When the processor is servicing another interrupt, this bit indicates if the FLTUI interrupt is unmasked (if set, = 1), or masked (if cleared, = 0). FLTII Floating-Point Invalid Operation Interrupt.
Page 857: Index
INDEX Numerics addressing, 14-53 7-bit in TWI, 12-1, 12-15 128-channel TDM, general call in TWI, 12-14 16-bit to 32-bit word packing enable IOP, 2-29 (PACK), 5-62 pre-modify, 2-39 16-bit word lengths, 5-45, 6-32, 7-14 restrictions on external memory, 32-bit word lengths, 5-45, 6-32, 7-14 transfer phase in TWI, 12-6...
Page 858 Index AMI bits baud rate (continued) ACK pin enable (ACKEN), A-18 SPIBAUD (serial peripheral interface AMI enable (AMIEN), A-18 baud rate) register, 6-5, A-60 buffer flush (FLSH), A-19 UART, 11-4, 11-5, 11-12 bus hold cycle (HC), A-18 beginning and ending an SPI transfer, 6-29 bus idle cycle (HC), A-19...
Page 859 Index booting bus request, shared memory (BRx) pins, boot kernel, 14-37 3-81, 3-92 BOOT_CFGx (boot source bus synchronized (BSYN) bit, 3-89, 3-93, configuration) pins, 14-38 bootstrap loading, 14-37 bus transition cycle (BTC), 3-82 from SPI flash, 14-42 buses SPI port, 14-42 arbitration, 2-20, 3-79, 3-82...
Page 860 Index CAS latency channel B transmit status register bit (SDCL), A-22 (SPDIF_TX_CHSTB), A-90, A-91 definition, 3-32 channel double frequencey mode, single, setting, 3-40 catastrophic interrupts, 4-65 channel mode (SPDIF), two, CBR (CAS before RAS) definition, 3-33 channel number, encoded, 7-19 CBxI (circular buffer x overflow interrupt) channel selection registers, 5-31...
Page 861 Index clocks and system clocking (continued) connections frame sync bypass mode, direct bypass, group A, DAI, clock signals, 4-19 13-6 group A, DPI, input routing signals, frame sync bypass mode, one shot, 13-6 4-52 internal clock select (ICLK) bit, A-37 group B, DAI data signals, 4-25 jitter,...
Page 862 Index (continued) DAI registers (continued) clock routing control registers (group A), DAI_IRPTL_RE register as replacement 4-19 to IMASK register, 4-69 configurable interrupts, A-112 falling edge interrupt mask register configuration macro, 4-77 (DAI_IRPTL_FE), A-115 connecting peripherals with, high priority interrupt default configuration, 4-18 (DAI_IRPTL_H), A-113...
Page 863 Index data (continued) division multiplexed (TDM) mode, time, packing and unpacking, 5-45 9-19 data buffers, in serial ports, divisor data bus (DATA) pins, 3-20 clock output, 13-3 data direction control (SPTRAN) bit, 5-64, reset, UART, 11-12 A-39 SPORT (DIVx) registers, 5-6, A-44 data fetch, external port, 3-25...
Page 864 Index (continued) (continued) master mode operation, 6-15 default configuration, 4-51 memory-to-memory, 2-48 input routing (group A) signals, 4-52 multiple chain requests, 2-18 interrupts, 4-67 non-chained, 2-13 pin assignment (group B) signals, 4-56 parameter registers, 2-17 pin enable (group C) signals, 4-60 ping-pong, 7-22...
Page 865 Index enable equation (continued) breakpoint (ENBx) bit, A-178 PWM dead time, clock outputs, 13-3 PWM switching frequency, DMA, 7-20 SDRAM refresh rate, 3-50 DMA interrupt (INTEN) bit, 6-34 serial clock frequency, 5-70 external port (asynchronous memory serial port clock divisor, 5-70 interface), A-18...
Page 866 Index errors/flags, DMA, external port, host port, execution stalls, bus transition, 3-84 serial port, SPI port, UART port, 6-35 external data path width, setting, 3-43 examples external master clock, 14-21 bidirectional DAI pin buffer, 4-13 external memory DAI pin buffer, 4-10 access timing, 3-36...
Page 867 Index external port (continued) external port registers (continued) modes, setting, 3-24 length and base (ELEP, EBEP), 2-37 read hold cycle (RHC) bits, A-19 external port bits bank select (BxSD), A-11 FE (framing error) bit, 11-4 bus priority (EPBR), A-12 FIFO data enable (DATA), A-13 control and status in input data port,...
Page 868 Index frame sync (continued) glitch vulnerability (SPORTs), 5-10 both enable (FS_BOTH) bit, 5-64 GM (get more data) bit, 6-11, 6-20, 6-37, early vs. late, 5-40 A-54 equations, 13-11 ground plane, in PCB design, 14-34 frequencies, 5-69 groupings of signals in DAI/DPI, in multichannel mode, 5-28 internal vs.
Page 869 Index I/O processor (continued) (continued) chained DMA, 2-14 control bits, 5-21 configuring DMA, example for DAI, 13-15 count registers, 2-27, 2-31 mode, 5-74 DAI interrupt registers (DAI_IRPTL_H, mode (IDP), 7-3, 7-5, 7-21 DAI_IRPTL_L), SPCTLx control bits, 5-22 data (IOD) bus, 2-20 timing (IDP), data buffers in DMA,...
Page 870 Index IDP bits (continued) IDP bits (continued) clear buffer overflow (IDP_CLROVR), port select (IDP_PORT_SELECT), 7-8, 7-15, 7-16, 7-25, A-67 7-18, 7-21, A-77 DMA enable (IDP_DMA_EN), 7-20, reset (IDP_PDAP_RESET) bit, A-78 7-22, 7-25, A-67 IDP registers DMA status (IDP_DMAx_STAT), control (IDP_CTL0), 7-18, 7-19, 7-20, 7-26, A-111 A-66...
Page 871 Index IMASKP (interrupt mask pointer) register, internal memory (continued) B-22 DMA index (IISPx) registers, 2-27, 2-29, IMSPI (serial peripheral interface address A-50 modify) register, 6-16, 6-19, A-64 DMA modifier (IDP_DMA_Mx) IMSPx (SPORT DMA address modifier) registers, 7-28 registers, 2-27, 2-29, A-50 DMA modifier (IMSPx) registers, 2-27, INCLUDE directory,...
Page 872 Index interrupt mask (IMASK) control register, latching B-18 high and low priority (DAI/DPI), 4-69 interrupt vector, sharing, 5-72 interrupt latch (IRPTL) register, B-13 interrupts, B-15, B-19, B-24 status for interrupts, B-13 (enable RX status interrupt) bit, A-123 latchup, 14-32 assigning priority for UART, 11-11 latency catastrophic,...
Page 873 Index mode broadcast (SPI), making connections via the signal routing chain insertion, 2-14, 2-41 unit, 4-15 chained DMA, 2-41 manual left-justified (SPORT), 5-16 contents, xxxii left-justified sample pair (IDP), conventions, xliii loopback (SPORT), 5-6, A-42 new in this edition, xxxiv master (SPI), 6-38 related documents,...
Page 874 Index MTxCSx (serial port transmit select) OSPID (operating system process ID), 2-4, registers, A-46 A-182 multichannel A and B channels, A-30 OSPIDENS (operating system process ID) multichannel compand select (MTxCCSy register enable bit, A-182 and MRxCCSy) registers, 5-47 output control unit, PWM, 8-17 multichannel operation (SPORT), 5-25...
Page 875 Index (continued) peripherals frame sync input source enable memory mapped, 3-20 (CLKx_SOURCE_IOP) bit, A-161 overview, frame sync with external frame sync peripherals, processor specific, enable (FSx_SYNC) bit, A-161, phase shift of frame sync, 13-9 A-162 PICR (peripheral interrupt priority) frame syncs, 13-11 registers, A-164...
Page 876 Index polarity (continued) programmable interrupt registers (PICRx), PWM single update mode, A-164 A-170 SPDIF connections, programming examples SPI clock, 6-21, 6-27 input data port, 7-31 7-33 polling the I/O processor, 2-12 power management, 14-14 14-16 porting from previous SHARCs precision clock generators, 13-23 paged DRAM boundary, 3-22...
Page 877 Index (continued) receive data buffer status (RXS) bit, 6-30 period (PWMPERIOD) registers, 8-5, receive data, serial port (RXSPx) registers, A-81 2-25 period completion status bits, receive data, SPI (RXSPI) register, 6-37 polarity select (PWMPOL) registers, receive overflow error (SPIOVF) bit, 6-25, A-83 6-26, 6-34...
Page 878 Index restrictions (continued) RXSR (SPI receive shift) register, UART port controller, 11-11 right channel status for subframe B (DIRCHANR) register, A-96 S/PDIF right-justify format (SPORTs) audio standards, 9-16 companding, 5-61 biphase encoded data input, 9-18 setting, 5-46, A-37 biphase encoding, 9-11 rising and falling edge masks BLK_START signal,...
Page 879 Index S/PDIF (continued) S/PDIF bits (continued) serial clock input, 9-24 select single-channel, double-frequency serial data, 9-10 mode channel (DIT_SCDF_LR), single-channel, double-frequencey A-88 format, serial data input format SRU control registers, 9-8, 9-18 (DIT_SMODEIN), A-88 SRU routing, 9-11 single channel enable (TX_SCDF_EN), stream disconnected (DIR_NOSTREAM) bit, A-95...
Page 880 Index S/PDIF registers (continued) SDRAM bits (continued) extracted receiver frame sync output disable clock and control (DSDCTL), (SPDIF_RX_FS_O), 9-18 A-22 extracted receiver sample clock output external data path width (X16DE), A-24 (SPDIF_RX_CLK_O), 9-18 force auto refresh (Force AR), A-24 receive control (DIRCTL), 9-12 force load mode register write (Force receiver status (DIRSTAT),...
Page 881 Index SDRAM controller (continued) SDRAM controller commands definitions, 3-31 3-36 auto-refresh, 3-70 disable, 3-40 bank activate, 3-31, 3-65 external data path width, setting, 3-43 burst stop, 3-32, 3-69 external memory access timing, 3-36 command pin states, 3-72 forcing auto refresh, 3-45 load mode register, 3-64...
Page 882 Index shared memory signals (continued) See also external port pin buffers, 4-10 asynchronous access mode, 3-81 pin output routing, 4-12 bus arbitration, 3-79 pin routing, 4-10 code select (CSEL) bit, 3-82 read, 3-25 force sync of shared memory bus responding to, 4-71 (FSYNC) bit, rising edge,...
Page 883 Index software interrupt (SFT0x) bit, B-18, B-21, (continued) B-26 clock, sampling edge, defined, software interrupt x, user (SFTxI) bit, B-18, configuring and enabling, 6-15 B-21, B-26 data transfer operations, 6-13 software reset (SRST) bit, device select signal, SOVFI (stack overflow/full) bit, B-15, DMA, 6-14 to 6-27,...
Page 884 Index send zero (SENDZ) bit, 6-11, 6-37 SPI bits (continued) serial peripheral interface clock flush receive buffer (RXFLSH), 6-23, (SPICLK) signal, 6-25, A-55 slave mode, 6-11, 6-20 flush transmit buffer (TXFLSH), A-55 slave mode operation, 6-11 get more data (GM), 6-11, 6-37 slave select outputs (SPIDS0-3), input service select (ISSS),...
Page 885 Index SPI registers SPILI (SPI low priority interrupt) bit, 6-34 baud rate (SPIBAUDx), A-60 SPIMME bit, 6-35 DMA address modify (IMSPI), A-64 SPIOVF (SPI receive overflow error) bit, DMA chain pointer (CPSPI), A-65 6-25, 6-26, 6-34, 6-35 DMA configuration (SPIDMAC), 6-14, SPISTAT, SPISTATB (SPI status) 6-16, 6-19, 6-22, 6-23, 6-35, A-62...
Page 886 Index SPORT bits (continued) SPORT modes (continued) frame sync both (FS_BOTH), 5-64, operation mode (OPMODE) bit, 5-62 A-39 standard DSP, 5-11, A-30 frame sync required (FSR), A-38 SPORTs FS both enable (FS_BOTH), A-39 See also SPORT bits, modes, registers internal clock select (ICLK), 5-62, A-37 128-channel TDM, internal frame sync select (IFS), 5-63,...
Page 887 Index SPORTs (continued) SPORTs registers (continued) interrupts, priority of, 5-72 divisor (DIVx), latency in writes, 5-58 DMA parameter, 5-76 operation modes, 5-10, 5-11, 5-59 modify (IMSPx), A-50 pairing, 5-27 receive buffer (RXSPx), A-44 primary and secondary data buffers, SPCTLx (serial port control), A-29 pulse code modulation (PCM), 5-20...
Page 888 Index (continued) (continued) sample rate ratio, 10-2, 10-19 group C (frame sync) signals, 4-31 sample rates, input, 10-18 group D (pin assignments) signals, 4-36 servo loop, 10-2 group E (miscellaneous) signals, 4-43 time division multiplexing mode, 10-16, 4-46 10-18 group F signals, 4-47 tracking input and output rates, 10-2...
Page 889 Index STATPA (program memory data SYSCTL register (continued) breakpoint hit) bit, A-181 rotating priority bus arbitration (RBPR) STATUS field, 11-10 bit, strobe period, 13-13 SRST (software reset) bit, strobe pulse, 13-13 timer (flag) expired mode strobe, PDAP output, 7-14 (TMREXPEN) bit, STROBEA (one shot frame sync A) bit, system control register.
Page 890 Index system design (continued) timing (continued) recommendations and suggestions, SPORT framed vs. unframed data, 5-40 14-34 SPORT left-justified sample pair mode, RESET pin, 14-33 5-19 shared memory system diagram, 3-79 SPORT normal vs. alternate framing, stalls, 14-54 5-40 switching frequencies, 14-29 SPORT word select, 5-25...
Page 891 Index TWI controller (continued) slave transmit data valid (TWIDVAL), little endian word order, 12-9 A-134 prescale register, 12-4 TWI controller registers programming examples, 12-15 clock divider (TWIDIV), 12-5, A-132 start and stop conditions, 12-13 RXTWI16 (16-bit receive FIFO) transferring data, 12-10 register, 12-10...
Page 892 Index UART bits (continued) TSR and UARTxTHR empty UART, 11-1 (UARTTEMT), 11-4 assigning interrupt priority, 11-11 UARTNOINT (pending interrupt), baud rate, 11-4, 11-5 A-124 baud rate examples, 11-12 UARTSTAT (interrupt), A-124 data ready flag, 11-13 UART registers data word, 11-4 divisor latch (UARTxDLH), 11-11, divisor, 11-11, A-125...
Page 893 Index UART registers (continued) UARTPE (UART parity error), 11-9 UARTxLSR (line status register), 11-4, UMODE (user mode breakpoint) bit, A-120 A-175 UARTxRBR (receive buffer register), user mode breakpoint (UMODE), A-175 11-5 UARTxSCR (scratch register), 11-12, A-126 wait states, enabling (WS bit), A-18 UARTxTHR (transmit holding register), word length,...
Page 894 Index I-38 ADSP-21368 SHARC Processor Hardware Reference...

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