Analog Devices ADSP-SC58 Series Hardware Reference Manual page 858

Figure 18-12: Generated Blanking Preamble Sequence
Frame Synchronization in ITU-R 656 Modes
For interlaced video, the start of frame synchronization occurs when a high-to-low transition is detected in F, the
field indicator. For progressive video, the start of frame synchronization occurs when a high-to-low transition is de-
tected in V, the vertical blanking indicator. These transitions in F and V can occur only in the EAV sequence. A start
of line is detected on a low-to-high transition in H, the horizontal blanking indicator, which occurs in the EAV
sequence as well.
For interlaced video, the start of frame corresponds to the start of field 1. Therefore, up to two fields can be ignored
before the EPPI receives data. (For example, if field 1 started before the EPPI-to-camera channel was established).
For progressive video, the start of frame corresponds to the start of active video.
Because all H and V signaling is embedded in the data stream in ITU-R 656 modes, the EPPI ignores the count
registers (EPPI_HCNT, EPPI_VCNT). However, the EPPI still uses the
chronization errors. Therefore, program this MMR with the number of lines expected in each frame of video.
The EPPI monitors the number of EAV-to-SAV transitions that occur from the start of a frame until it decodes the
end of frame condition. (For example, a transition from F = 1 to F = 0 for interlaced video and a transition from V =
1 to V = 0 for progressive video).
At the end of frame condition, the actual number of lines processed is compared against the value in
EPPI_FRAME. If there is a mismatch, a frame track error is asserted in the
an SAV transition was missed, the current field only has NUM_ROWS – 1 rows. But, resynchronization occurs at
the start of the next frame. When the EPPI receives the entire field, the field status bit is toggled in the
EPPI_STAT register. This way, an interrupt service routine (ISR) can discern which field was previously read in.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
H
EAV HORIZONTAL BLANKING
EAV HORIZONTAL BLANKING
F1VB_BD
EAV HORIZONTAL BLANKING
X
EAV HORIZONTAL BLANKING
EAV HORIZONTAL BLANKING
F1_ACT EAV HORIZONTAL BLANKING
EAV HORIZONTAL BLANKING
EAV HORIZONTAL BLANKING
X
EAV HORIZONTAL BLANKING
F1VB_AD
EAV HORIZONTAL BLANKING
X
EAV HORIZONTAL BLANKING
F2VB_BD
EAV HORIZONTAL BLANKING
X
EAV HORIZONTAL BLANKING
EAV HORIZONTAL BLANKING
F2_ACT EAV HORIZONTAL BLANKING
EAV HORIZONTAL BLANKING
EAV HORIZONTAL BLANKING
X
EAV HORIZONTAL BLANKING
F2VB_AD EAV HORIZONTAL BLANKING
EAV HORIZONTAL BLANKING
EPPIx_HBL
SAV VERTICAL BLANKING
SAV VERTICAL BLANKING
SAV VERTICAL BLANKING
SAV ACTIVE DATA
SAV ACTIVE DATA
SAV ACTIVE DATA
SAV ACTIVE DATA
SAV ACTIVE DATA
SAV VERTICAL BLANKING
SAV VERTICAL BLANKING
SAV VERTICAL BLANKING
SAV VERTICAL BLANKING
SAV ACTIVE DATA
SAV ACTIVE DATA
SAV ACTIVE DATA
SAV ACTIVE DATA
SAV ACTIVE DATA
SAV VERTICAL BLANKING
SAV VERTICAL BLANKING
SAV VERTICAL BLANKING
EPPIx_AVPL
EPPI_FRAME
EPPI_STAT
EPPI Operating Modes
register to check for syn-
register. For example, if
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