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ADSP-SC58x TRU Register Descriptions
Error Address Register
The TRU error address register (TRU_ERRADDR) holds the address from the memory-mapped register access gen-
erating an access error of TRU registers.
Figure 8-2: TRU_ERRADDR Register Diagram
Table 8-6: TRU_ERRADDR Register Fields
Bit No.
(Access)
11:0
ADDR
(R/W)
8–16
15
14
13
0
0
0
ADDR (R/W)
Error Address
31
30
29
0
0
0
Bit Name
Error Address.
The TRU_ERRADDR.ADDR holds the address from the memory-mapped register ac-
cess generating an access error of TRU registers. These errors occur on access to the
TRU_SSR[n]
an invalid address. See the
more information about locking.
The
TRU_ERRADDR
of multiple errors occurring, the
first error. To re-enable the
(TRU_STAT.LWERR and TRU_STAT.ADDRERR) in the
be cleared.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
20
0
0
0
0
0
0
0
0
Description/Enumeration
or
TRU_MTR
registers when these registers are locked or on access to
TRU_SSR[n]
register holds the address of the first error to occur. In the event
TRU_ERRADDR
TRU_ERRADDR
4
3
2
1
0
0
0
0
0
0
19
18
17
16
0
0
0
0
0
and
TRU_MTR
register descriptions for
register contains the address of the
register for update, both status bits
TRU_STAT
register must
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