Analog Devices ADSP-SC58 Series Hardware Reference Manual page 801

Sharc+ processor
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UART Data Transfer Modes
Reception starts when the UART receiver detects a falling edge on the UART_RX input pin. The receiver attempts
to see a start bit. The data is shifted into the
processes the stop bit and copies the received data to the 8-stage receive FIFO. The
data reception.
The receiver samples data bits close to their midpoint. Because the receiver clock is typically asynchronous to the
data rate of the transmitter, the sampling point can drift relative to the center of the data bits. The sampling point is
synchronized again with each start bit, so the error accumulates only over the length of a single word. The polarity
of received data is selectable, using the UART_CTL.RPOLC bit.
NOTE:
The receiver checks for only a single stop bit. After the third sample of the first stop bit has been received
(at time 9/16th of the stop bit duration), the receiver immediately acts (status update). It then prepares for
new falling edge detection (start detection).
IrDA Transmit Operation
To generate the IrDA pulse transmitted by the UART, the normal NRZ output of the transmitter is first inverted if
the UART_CTL.TPOLC bit is configured for active-low operation. In this configuration, a zero is transmitted as a
high pulse of 16 UART clock periods and a one is transmitted as a low pulse for 16 UART clock periods. Then, six
UART clock periods delay the leading edge of the pulse. Similarly, eight UART clock periods truncate the trailing
edge of the pulse. For a 16-cycle UART clock period, this operation results in the final representation of the original
zero as a high pulse of only 3/16 clock periods. The IrDA Transmit Pulse figure shows how the pulse is centered
around the middle of the bit time. The final IrDA pulse is fed to the off-chip infrared driver.
This modulation approach ensures a pulse width output from the UART of three cycles high out of every 16 UART
clock cycles. As shown in the IrDA Transmit Pulse figure, the error terms associated with the bit rate generator are
small and well within the tolerance of most infrared transceiver specifications.
NOTE:
In IrDA mode, writes to the
INVERTED
Figure 17-7: IrDA Transmit Pulse
IrDA Receive Operation
The IrDA receiver function is more complex than the transmit function. The receiver must discriminate the IrDA
pulse and reject noise. The receiver looks for the IrDA pulse in a narrow window centered around the middle of the
expected pulse.
17–14
UART_RSR
UART_TAIP
0
NRZ
7/16
9/16
FINAL
IrDA
8/16
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register. After the ninth sample of the first, the receiver
register are equivalent to writes to the
1
16/16
16/16
UART_RSR
recovers for further
UART_THR
0
7/16
9/16
8/16
register.

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