Analog Devices ADSP-SC58 Series Hardware Reference Manual page 238

Sharc+ processor
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System Interface Disable Register
The RCU system interface disable register (RCU_SIDIS) lets the RCU assert a system interface disable request to
functional units in the processor. This register is set to its default values by a hard reset or any system reset event. For
information on mapping between
Figure 6-8: RCU_SIDIS Register Diagram
Table 6-13: RCU_SIDIS Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
1:0
SI[n]
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
RCU_SIDIS
bits and functional units, see the RCU functional description.
15
14
13
0
0
0
SI[n] (R/W)
System Interface Disable Request
[1:0]
31
30
29
0
0
0
LOCK (R/W)
Lock
Bit Name
Lock.
If the global lock bit is set (SPU_CTL.GLCK bit =1) and the RCU_SIDIS.LOCK
bit is set, the
System Interface Disable Request [1:0].
Each RCU_SIDIS.SI[n] bit corresponds to a functional unit in the processor that
supports the system interface disable request-acknowledge protocol.
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
register is read only (locked).
RCU_SIDIS
0 Unlock
1 Lock
0 RCU_SI_DISABLE_REQ[1:0] deasserted
3 RCU_SI_DISABLE_REQ[1:0] asserted
ADSP-SC58x RCU Register Descriptions
4
3
2
1
0
0
0
0
0
0
20
19
18
17
16
0
0
0
0
0
6–21

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