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Figure 19-1: PWM Block Diagram
The following list describes the primary blocks.
• Each pair of PWM signals references either the main timer or the independent timer.
• PWMTMR0 is the main timer and can trigger the delayed start of the other timers.
• Timing control units, one for each channel, together form the core of the PWM. The unit generates the re-
quired complex waveforms on the high-side and low-side outputs for the respective channel.
• Dead-time insertion occurs after the ideal PWM output pair is generated.
• The gate drive unit generates the high-frequency chopping signal and then mixes it with the requisite PWM
output signals.
• The PWM shutdown and interrupt controller manage the various PWM shutdown modes for the timing unit
and generate the requisite interrupt signals.
• The PWM sync pulse control unit generates the internal PWM_SYNC pulse and also controls whether the ex-
ternal PWM_SYNC input pulse is used.
Timer Units
Five timers make up the time base for the PWM module. The main timer, PWMTMR0 operates at a switching
frequency determined by the period register PWM_TM0. The four remaining timers (PWMTMR1 through
PWMTMR4) can operate at independent switching frequencies determined by their respective registers.
The respective time registers
timer frequency. In this case, the
timer based on the main timer PWMTMR0.
The delayed operation of a timer requires one of the following:
NOTE:
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
PWM_CTL
PWM_SYNC_WID
PWMTMR0
PWM_TM0
PWM_AH0, PWM_AL0
CHANNEL A
PWM_TM1
PWMTMR1
TIMING CONTROL UNIT
PWM_DLY1
PWM_BH0, PWM_BL0
CHANNEL B
PWM_TM2
PWMTMR2
TIMING CONTROL UNIT
PWM_DLY2
PWM_CH0, PWM_CL0
CHANNEL C
PWMTMR3
PWM_TM3
TIMING CONTROL UNIT
PWM_DLY3
PWM_DH0, PWM_DL0
PWM_TM4
CHANNEL D
PWMTMR4
PWM_DLY4
TIMING CONTROL UNIT
PWM_xCTL
PWM_IMASK
PWM_ILAT
(PWM_TM1
through PWM_TM4) can be programmed to work at a multiple of the main
through
PWM_DLYA
SYNC
PWM_SYNC_OUT
GENERATION
SECURITY
PWM_TRIPCFG
PWM_DT
PWM_CHOPCFG
CONTROL
DEAD-TIME
AND
GATE DRIVE
UNIT
DEAD-TIME
AND
GATE DRIVE
UNIT
TRIP
CTRL
DEAD-TIME
UNIT
AND
GATE DRIVE
UNIT
DEAD-TIME
AND
GATE DRIVE
UNIT
INTERRUPT
PWM_TRIP_INT
GENERATION
PWM_SYNC_INT
CIRCUITRY
registers control the lead-lag phase of a given
PWM_DLYD
Architectural Concepts
AH
AL
BH
BL
CH
CL
DH
DL
TRIP0
TRIP1
19–7
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