Analog Devices ADSP-SC58 Series Hardware Reference Manual page 873

EPPI Programming Model
2. Program the EPPI_LINE
3. Program the EPPI_VDLY
ing to read or transmit data.
4. Program the
EPPI_VCNT
of lines from the start of the frame.
5. Program the
EPPI_HDLY
is detected for the start of a new line.
6. Program the EPPI_HCNT
number of cycles have expired since the assertion of EPPI_FS1.
EPPI Mode Configuration
This section describes EPPI mode configurations, including support for all EPPI transmit and receive modes.
Configuring 8-Bit Receive Mode
For 8-bit non-split receive mode and if EPPI_CTL.PACKEN =1, the EPPI packs 4 bytes of incoming data into a
32-bit word. Alternate even or odd samples can be skipped based on the EPPI_CTL.SKIPEN and
EPPI_CTL.SKIPEO bits. The first incoming data can be placed either in the least significant bit positions or in
the most significant bit positions, based on the EPPI_CTL.SWAPEN bit setting.
Table 18-13: 8-Bit Receive Mode with Packing Enabled
Pin Data (8 bits) DMA DATA
SKIPEN=0
SKIPEO =X
SWAPEN=0
SIGNEXT=X
0x11
0x22
0x33
0x44 0x4433 2211
0x55
0x66
0x77
0x88 0x8877 6655
0x99
0xAA
0xBB
18–34
register with the number of samples per line in the frame.
register with the number of lines to wait after the start of a new frame before start-
register with the number of lines to read in or write out after
register with the number of clock cycles to delay after the assertion of EPPI_FS1
register with the number of samples to read in or write out after
DMA DATA DMA DATA
SKIPEN=0 SKIPEN=1
SKIPEO=X SKIPEO=1
SWAPEN=1 SWAPEN=0
SIGNEXT=X SIGNEXT=X
0x1122 3344
0x7755 3311
0x5566 7788
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DMA DATA DMA DATA
SKIPEN=1 SKIPEN=1
SKIPEO=0 SKIPEO=1
SWAPEN=0 SWAPEN=1
SIGNEXT=X SIGNEXT=X
0x1133 5577
0x8866 4422
number
EPPI_VDLY
EPPI_HDLY
DMA DATA
SKIPEN=1
SKIPEO=0
SWAPEN=1
SIGNEXT=X
0x2244 6688