Table of Contents
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Triggers .................................................................................................................................................... 55–7
SWU Programming Model .......................................................................................................................... 55–7
SWU Mode Configuration ....................................................................................................................... 55–8
Configuring the SWU for Bandwidth Mode ......................................................................................... 55–8
Configuring the SWU for Watchpoint Mode ....................................................................................... 55–9
ADSP-SC58x SWU Register Descriptions ................................................................................................ 55–10
Count Register n ................................................................................................................................... 55–11
Control Register n ................................................................................................................................. 55–12
Current Register n ................................................................................................................................. 55–17
Global Control Register ......................................................................................................................... 55–18
Global Status Register ........................................................................................................................... 55–19
Bandwidth History Register n ............................................................................................................... 55–23
ID Register n ......................................................................................................................................... 55–24
Lower Address Register n ....................................................................................................................... 55–25
Target Register n ................................................................................................................................... 55–26
Upper Address Register n ...................................................................................................................... 55–27
System Debug and Trace Unit (DBG)
DBG Features .............................................................................................................................................. 56–1
DBG Functional Description....................................................................................................................... 56–2
ADSP-SC58x CSPFT Register List .......................................................................................................... 56–2
ADSP-SC58x TAPC Register List ............................................................................................................ 56–3
ADSP-SC58x TAPC Register List ............................................................................................................ 56–3
ADSP-SC58x STM Trigger List ............................................................................................................... 56–4
ADSP-SC58x CTI Trigger List................................................................................................................. 56–5
ADSP-SC58x CTI Interrupt List ............................................................................................................ 56–6
DBG Block Diagram ................................................................................................................................ 56–6
DBG Definitions...................................................................................................................................... 56–7
Test Access Port Controller (TAPC) ......................................................................................................... 56–8
Embedded Trace Macrocell (ETM)........................................................................................................... 56–8
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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