Analog Devices ADSP-SC58 Series Hardware Reference Manual page 21

Shadow Output Transmit Buffer Register .............................................................................................. 15–26
Serial Peripheral Interface (SPI)
SPI Features................................................................................................................................................. 16–1
SPI Functional Description.......................................................................................................................... 16–2
ADSP-SC58x SPI Register List ................................................................................................................ 16–2
ADSP-SC58x SPI Interrupt List .............................................................................................................. 16–3
ADSP-SC58x SPI Trigger List.................................................................................................................. 16–4
ADSP-SC58x SPI DMA Channel List...................................................................................................... 16–5
SPI Block Diagram................................................................................................................................... 16–5
Transfer Protocol ...................................................................................................................................... 16–6
Clock Considerations .............................................................................................................................. 16–7
Controlling Delay Between Frames .......................................................................................................... 16–8
Flow Control ........................................................................................................................................... 16–9
Slave Select Operation ........................................................................................................................... 16–10
Beginning and Ending a Non-DMA SPI Transfer ................................................................................. 16–11
Transmit Operation in Non-DMA Mode .............................................................................................. 16–12
Receive Operation in Non-DMA Mode ................................................................................................. 16–12
Dual I/O Mode ...................................................................................................................................... 16–12
Quad I/O Mode (SPI2 only) ................................................................................................................. 16–13
Fast Mode .............................................................................................................................................. 16–14
Memory-Mapped Mode (SPI2 only)....................................................................................................... 16–15
Memory-Mapped Description of Operation........................................................................................ 16–16
Memory-Mapped Architectural Concepts............................................................................................ 16–17
Memory-Mapped Read Accesses.......................................................................................................... 16–19
Memory-Mapped High-Performance Features..................................................................................... 16–23
Merged Read Accesses ...................................................................................................................... 16–23
Wrap Around Accesses ..................................................................................................................... 16–23
Execute-In-Place (XIP, SPI2 only) .................................................................................................... 16–24
Memory-Mapped Mode Error Status Bits ........................................................................................... 16–25
Memory-Mapped Programming Guidelines ........................................................................................ 16–25
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference xxi