Table of Contents
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Autonomous Ring Mode (ARM) ............................................................................................................ 44–26
Target Command Mode (TCM) ............................................................................................................. 44–27
Direct Host Mode (DHM) ..................................................................................................................... 44–27
PKTE Event Control ................................................................................................................................. 44–28
PKTE Interrupt Signals.......................................................................................................................... 44–28
PKTE Programming Model....................................................................................................................... 44–30
PKTE Mode Configuration.................................................................................................................... 44–33
PKTE Programming Concepts ............................................................................................................... 44–33
Packet Engine Descriptor .................................................................................................................... 44–33
Descriptor Processing .......................................................................................................................... 44–35
Ownership of the Descriptor............................................................................................................... 44–36
Description and Use of the SA Record and State Record Structure...................................................... 44–37
SA Record Structure ........................................................................................................................ 44–37
SA State Structure ............................................................................................................................ 44–39
ARC4 State Structure .......................................................................................................................... 44–40
Configuring Operations in the PKTE ................................................................................................. 44–41
Basic Operations and Decoding .......................................................................................................... 44–41
Error Code Description ....................................................................................................................... 44–42
Extended Error Codes ......................................................................................................................... 44–42
Number Format .................................................................................................................................. 44–45
PKTE Programming Examples .................................................................................................................. 44–45
Calculating SHA in Direct Host Mode................................................................................................... 44–45
Performing AES Decryption in Direct Host Mode ................................................................................. 44–47
ADSP-SC58x PKTE Register Descriptions ............................................................................................... 44–48
Packet Engine ARC4 State Record Address ............................................................................................ 44–50
Starting Entry of 256-byte ARC4 State Buffer ....................................................................................... 44–51
Packet Engine Buffer Pointer Register ................................................................................................... 44–52
Packet Engine Buffer Threshold Register ............................................................................................... 44–53
Packet Engine Command Descriptor Ring Base Address ....................................................................... 44–55
Packet Engine Command Descriptor Count Register ............................................................................ 44–56
Packet Engine Command Descriptor Count Increment Register ........................................................... 44–57
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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