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Controller On Die Termination (ODT)
The controller ODT is enabled with the granularity of a byte lane. The description of this feature can be obtained in
the description of the corresponding PHY registers. Controller ODT involves extra overhead in terms of power con-
sumption during reads.
The DMC implements dynamic on die termination at processor pads. When controller ODT is enabled, the termi-
nation resistors in the pads are turned on when the controller reads data from the DRAM. These resistors are turned
off when the controller writes to the DRAM.
Mode Register Set and Extended Mode Register Set Command
The load mode register command initializes the SDRAM operation parameters. The DMC supports the mode regis-
ter set and extended mode register set commands. The controller automatically issues the mode register set com-
mand during power-on initialization and also when the
The mode register set command is sent after the ongoing data transfer completes.
The DMC automatically issues the mode register set command when the shadow EMR1/EMR2/EMR3 registers are
written. The corresponding DMC_MSK.EMR3DMC_MSK.EMR2/DMC_MSK.EMR1 bits must be enabled.
DDR3 Reset Functionality
DDR3 contains an additional pin corresponding to reset functionality. Reset is part of the initialization sequence
but it can be performed asynchronously when needed. The reset procedure is similar to the steps involved in the
initialization except the initial part of power-up.
To perform reset on the DDR3 module:
1. Check to ensure the module is in the idle state by polling the DMC_STAT.IDLE bit (0x0008).
2. Set the DMC_CTL.RESET bit (0x0004).
3. Monitor the DMC_STAT.RESETDONE bit for the completion of the reset function.
Do not perform any transactions during a module reset. Wait for the DMC_STAT.RESETDONE signal.
DDR3 SDRAM Organization
The DMC supports DDR3 SDRAM memory modules ranging from 512 Mb to 8 Gb. The following tables list the
address translation mechanism from the user interface to DDR3 memory interface. The controller also supports two
types of addressing modes: bank interleaving (DMC_CTL.ADDRMODE =1) and page interleaving
(DMC_CTL.ADDRMODE =0).
Bank Interleaving
The DDR3 Bank Interleaving table shows DDR3 bank interleaving.
Table 10-3: DDR3 Bank Interleaving
SDRAM size
Bank address bits
512 Mb
25:24
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DMC_MR
Row address bits
Column address bits
23:11
10:1
register is written with the DMC_MSK.MR bit.
Architectural Concepts
10–9
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