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Shadow EMR2 Register (DDR2)/Shadow EMR Register (LPDDR)
The
register in the DMC shadows the EMR2 register in the SDRAM when the DMC is in DDR2
DMC_EMR2
mode (DMC_CTL.LPDDR =0) and shadows the EMR register in the SDRAM when the DMC is in LPDDR mode
(DMC_CTL.LPDDR =1). If unmasked by the corresponding bit in the shadow mask register (DMC_MSK.EMR2
=1), a write to
DMC_EMR2
a write to
DMC_EMR2
only updates the register in the DMC, not the register in the SDRAM.
15
0
SRF (R/W)
High Temperature Self-Refresh
DS (R/W)
Drive Strength
31
0
Figure 10-11: DMC_EMR2 Register Diagram
Table 10-20: DMC_EMR2 Register Fields
Bit No.
(Access)
7
SRF
(R/W)
6:5
DS
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
triggers an extended "mode register set" command on the memory interface. If masked,
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
Bit Name
High Temperature Self-Refresh.
The DMC_EMR2.SRF bit enables the SDRAM's high temperature self-refresh rate
feature when the DMC is in DDR2 mode. (This bit is reserved in LPDDR mode.) For
more information about this operation, see the data sheet for the SDRAM being used
in your system.
Drive Strength.
The DMC_EMR2.DS bits select the drive strength value when the DMC is in LPDDR
mode. (These bits are reserved when the DMC is in DDR2 mode.) Note that all val-
ues other than those shown are reserved. For more information about this operation,
see the data sheet for the SDRAM being used in your system.
6
5
4
3
2
1
0
0
0
0
0
0
0
0
PASR (R/W)
Partial Array Self-Refresh
TCSR (R/W)
Temperature Compensated Self-Refresh
22
21
20
19
18
17
16
0
0
0
0
0
0
0
Description/Enumeration
0 Disable
1 Enable
4 Octant Drive strength
0 Full Drive Strength
1 1/2 Drive Strength
2 3/4 Drive Strength
3 1/4 Drive Strength
ADSP-SC58x DMC Register Descriptions
10–41
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